AN97798 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ Author: Shivendra Singh Associated Part Family: I 2 C F-RAM Associated Code Examples: None Related Application Notes: AN96578, AN87352 AN97798 provides an overview of the advantages of Cypress’s I2C F-RAM™ solution and the differences to be considered when migrating from an I2C EEPROM. It also describes the benefits of the migration. Contents 1 2 Introduction ...............................................................1 F-RAM Advantages ..................................................2 2.1 Faster Memory.................................................2 2.2 Easier Design ..................................................2 2.3 Data Security ...................................................2 2.4 Additional Features ..........................................2 3 Migrating from I2C EEPROM to I2C F-RAM ..............2 3.1 Pin and Package Compatibility ........................2 3.2 Parameter Compatibility...................................4 3.3 Feature and Access Protocol Compatibility .....6 4 Firmware Compatibility .............................................7 4.1 Multiple Pages in EEPROM Versus Single Page in F-RAM ........................................7 1 4.2 Page Write Delay ............................................. 9 5 Benefits of Migrating to I2C F-RAM......................... 10 5.1 Zero Clock Cycle Write Latency .................... 10 5.2 Low-Power Design......................................... 11 5.3 No Multidevice Design Required ................... 13 5.4 No Page Size Restriction ............................... 13 5.5 No Wear Leveling or Age Tracking Required ............................................ 13 5.6 No Action Required After Power Failure ........ 14 6 Summary ................................................................ 14 Document History............................................................ 15 Worldwide Sales and Design Support ............................. 16 Introduction EEPROMs are frequently used for the nonvolatile storage of a system’s data. However, the EEPROM’s slow nonvolatile write performance and limited write endurance limit its effectiveness in systems that need to execute frequent writes to the nonvolatile memory at bus speed. Many system designs have tried to resolve issues associated with EEPROMs by using a wear-leveling technique to increase the effective endurance, but this has been at the cost of increased EEPROM density and software overhead. Another alternative to save critical system data is to store data in the scratchpad RAM and then transfer it into nonvolatile memory, such as EEPROM or flash, at power down by using a backup power source. Both methods, however, are highly inefficient because of the increase in components, board space, hardware design complexities, and software overhead. Cypress’s I2C F-RAM is a serial nonvolatile memory that employs an advanced ferroelectric process and offers an energy-efficient, high-performance, and high-reliability nonvolatile RAM solution. It is available in both industrial and automotive grade temperatures. Cypress’s F-RAM has fast SRAM cells and provides virtually infinite (10 14) read/write endurance cycles, orders of magnitude higher than an EEPROM. The F-RAM performs write operations at the bus speed without incurring any write delays (NoDelay™), unlike serial EEPROMs and flash memories. Data is written directly into the F-RAM array, and the next bus cycle can start immediately, without checking the readiness of the device. Serial I2C F-RAM devices are available as drop-in replacements for standard I2C EEPROM devices. This application note shows the differences between an industry-standard I2C EEPROM and an I2C F-RAM. These differences need to be considered when migrating from an I2C EEPROM-based solution to Cypress’s I2C F-RAM solution. For more details on I2C F-RAM designs, refer to the application note AN96578 – Designing with I2C F-RAM. www.cypress.com Document No. 001-97798 Rev. ** 1 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ For more details on the benefits of Cypress’s F-RAM over a serial EEPROM, refer to the application note AN87352–F-RAM for Smart E-Meters. 2 F-RAM Advantages 2.1 Faster Memory 2.2 Virtually infinite (1014) read/write endurance cycles that do not require wear leveling Availability in industry-standard packages Reliable, advanced ferroelectric process No requirement for a battery or capacitor backup to store the last moment data Additional Features 3 No software overhead for managing page boundary Data Security 2.4 Full memory write at bus speed without any internal page program delay after each page write Easier Design 2.3 Random access: No page reads/writes needed Energy-efficient, fast nonvolatile RAM 151 years of data retention at 65 ºC Pb-free technology Migrating from I2C EEPROM to I2C F-RAM Cypress’s I2C F-RAM is available in two industry-standard packages: 8-pin SOIC and 8-pin DFN. These standard and versatile package options make I2C F-RAM drop-in replacements available for the majority of EEPROMs in the same package option and footprint without compromising system performance. In addition, the F-RAM solution provides performance advantages such as higher data throughput, NoDelay write, and energy-efficient operation. The following sections highlight the key differences and compatibilities between an I2C EEPROM and an I2C F-RAM. 3.1 Pin and Package Compatibility The 2C F-RAM is pin and package compatible with the I2C EEPROM. Table 1 shows the pin mapping, and Table 2 shows a package comparison of I2C EEPROM and I2C F-RAM. Table 1. I2C EEPROM and I2C F-RAM Pin Mapping Pin Name Pin Description 2 I2C F-RAM I C EEPROM Device select address E2, E1, E0 or A2, A1, A0 A2, A1, A0 Serial data/address input and serial data output SDA SDA Serial clock input SCL SCL Write protect input ̅̅̅̅̅ WP or WC WP Power supply VDD/ VCC VDD Ground VSS/GND VSS www.cypress.com Document No. 001-97798 Rev. ** 2 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ Table 2. I2C EEPROM and I2C F-RAM Package Comparison Feature/Function Package options I2C EEPROM 8-pin DFN 8-pin SOIC 8-pin PDIP 8-pin TSSOP 8-pin UDFN 8-WLCSP 8-pin MSOP I2C F-RAM Comments EEPROMs in the standard 8-pin DFN and 8-pin SOIC packages can be replaced by the I2C F-RAM. 8-pin DFN 8-pin SOIC Other I2C EEPROM packages are incompatible with the I2C F-RAM and will require changes to the PCB. The EXPOSED PAD of F-RAM in the 8-pin DFN package is an NC (no connect) pad, as shown in Figure 1. Note: This list shows the total package options available across all densities, but not necessarily all packages that are supported for all densities. Refer to the respective device datasheet to learn more about package differences before the migration. Figure 1. I2C F-RAM 8-pin DFN (4 mm × 4.5 mm × 0.75 mm) Package Outline EXPOSED PAD The I2C F-RAM EXPOSED PAD is not connected to the die and hence should be left floating. Ensure that the EXPOSED PAD of the I2C F-RAM DFN package is not soldered on the PCB when migrating to I2C F-RAM. Soldering it will cause the I2C F-RAM die to be exposed to excessive heat, which can result in bit failures and margin loss. www.cypress.com Document No. 001-97798 Rev. ** 3 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ 3.2 Parameter Compatibility Table 3 summarizes the key parameters that need to be evaluated for system-level compatibility when migrating from an I2C EEPROM to an I2C F-RAM. Table 3. Key Parameters Checklist Parameter Description I2C EEPROM I2C F-RAM Comments DC Parameters 1.5 V to 3.6 V VDD Power supply voltage VIH Input HIGH voltage Varies VIL Input LOW voltage Varies 2.0 V to 5.5 V 1.7 V to 5.5 V 0.7 × VDD to VDD + 0.3 V –0.3 V to 0.3 × VDD Varies VOL Output LOW voltage 0.6 V (max), IOL = +6 mA Varies 0.4 V (max), IOL = +3 mA 0.4 V (max), IOL = +2 mA 0.2 V (max), IOL = +150 µA I2C EEPROMs support a wider operating voltage range. When migrating to I2C F-RAM, the system must ensure that the I2C F-RAM operating voltage is within the operating range of the host controller accessing the I2C F-RAM. The I2C F-RAM follows the CMOS logic standard. The system must ensure that the logic levels are within the operating range of both the host and the I2C slave for proper operation. The I2C F-RAM output driver supports standard output drive strength, making it compatible with the majority of host controllers. The system must ensure that the logic levels are within the operating specification of both the I2C master (host) and the I2C F-RAM for proper operation. AC Parameters fSCL I2C clock frequency Cb Total capacitance of one I2C bus www.cypress.com Both devices follow the NXP specification for I2C access. Therefore, migrating from I2C EEPROM to I2C F-RAM does not require any system update for the same bus speed. Up to 1 MHz Varies (rated to NXP standard load or below) Up to 3.4 MHz A few crypto I2C EEPROM devices can support an I2C bus speed up to 5 MHz. The I2C F-RAM cannot replace these special devices due to incompatible features and access speed. Follows the NXP Migrating to I2C FRAM does not require any change or adjustment to the bus load. standard I2C bus load Document No. 001-97798 Rev. ** 4 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ Parameter Other I2C AC parameters Description All other AC parameters of the device I2C EEPROM I2C F-RAM Compatible with NXP I2C specification Compatible with NXP I2C specification Write cycle time tW/ tWC/ tWR (time to write data from page buffer to EEPROM memory) Varies, 5 ms to 10 ms Not applicable Comments Since I2C EEPROM and I2C F-RAM are both compatible with the NXP I2C specification, migration to I2C F-RAM does not require any change. It is always recommended to compare all AC parameters for any differences and evaluate their impact before migrating. With I2C F-RAM, a data byte is written directly into an intrinsic nonvolatile F-RAM cell. Therefore, the write cycle time is not applicable, and the device is immediately ready for the next access. Power Parameters 30 µs/V tVR VDD power-up ramp rate Varies 50 µs/V (minimum spec) 30 µs/V tVF VDD power-down ramp rate Varies 100 µs/V (minimum spec) tPU Power-up VDD (minimum) to first access (START condition) Not specified 1 ms When migrating to the I2C F-RAM, the system must ensure that the VDD power ramp rate is within the specification of the I2C F-RAM, as shown in Figure 2. Systems must ensure that the I2C F-RAM VDD power supply ramp rate is slower than the minimum specification. For example, the VDD power supply should not rise or fall 1.0 V in less than 30 µs (for a 30-µs/V ramp rate). I2C F-RAM needs to wait 1 ms to complete its bootup sequence and get ready. All devices have a finite bootup time, but some of them do not specify because their bootup time is not observable in a real system. When migrating from I2C EEPROM to I2C F-RAM, this parameter should be evaluated, and if necessary, the controller firmware should be modified to match the tPU time delay (for the first access only). Note: Other device parameters such as device current in different operating modes, ESD profile, latch-up current profile, soldering profile, and packages that differ between the I2C EEPROM and I2C F-RAM can warrant some system-level analysis before replacing the I2C EEPROM with the I2C F-RAM. www.cypress.com Document No. 001-97798 Rev. ** 5 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ Figure 2. I2C F-RAM Power Cycle Timing 3.3 Feature and Access Protocol Compatibility Table 4 compares the I2C EEPROM and the I2C F-RAM protocols and features and discusses key points to be considered when migrating from an I2C EEPROM to I2C F-RAM. Table 4. I2C EEPROM and I2C F-RAM Protocol and Feature Comparison Feature I2C EEPROM I2C F-RAM I2C START Standard I2C START I2C STOP Standard I2C STOP Data input Device samples SDA on SCL rising edge Data output Changes SDA when SCL is LOW Device addressing 7-bit addressing Comments No change required when migrating to the I2C F-RAM. No change required when migrating to the I2C F-RAM. Memory addressing Single-byte write Bulk write 2-byte or 1-byte, depending on the memory density Single byte write into page memory, followed by nonvolatile write cycle time. The next access can start only after the write cycle time (tWC). The maximum size of the bulk write is limited to the page size, followed by the nonvolatile write cycle time. Continuing to write beyond the page boundary will roll over to the beginning of the page and overwrite previously written data. The next access can start only after the write cycle time (tWC). www.cypress.com The most significant address byte is sent first followed by the least significant address byte. In a byte, the most significant address bit is transmitted first. Byte write into nonvolatile memory at bus speed. The next access can start immediately. No change required when migrating to the I2C F-RAM. The maximum size of the bulk write is the memory array. Continuing to write beyond the array size will roll over the address counter to the beginning of the memory array. However, the system can take advantage of the I2C F-RAM by reducing the write delay and increasing the bulk write size, which can significantly improve the system’s nonvolatile write performance. The next access can start immediately. Document No. 001-97798 Rev. ** 6 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ I2C EEPROM Feature I2C F-RAM Random address read A dummy write cycle is performed to load this (random) address into the address register, followed by a read. Current address read Reads from the current address, which is set after executing the write or read access in the previous cycle. Sequential read This can be used after a random or current address read. After the first successful read, the address counter auto-increments to the next address and sends data at the output. This continues until the I2C master sends NACK or generates a STOP condition. Write protect pin configuration Varies. Most devices have an internal weak pull-down resistor to keep this pin low when floating (not connected). All I2C F-RAM devices have an internal weak pull-down resistor to keep this pin low when floating (not connected). Slave select pin (A2, A1, A0) configuration Varies. Most devices have an internal weak pull-down resistor to keep these pins low when floating (not used). All I2C F-RAM devices have an internal weak pull-down resistor to keep these pins low when floating (not used). Some I2C EEPROMs define software reset by implementing one or all of the following protocols: Generate START condition Generate nine dummy clocks on SCL Generate START followed by STOP Software reset 4 Comments No change required when migrating to the I2C F-RAM. No change required when migrating to the I2C F-RAM. I2C F-RAM does not require this feature. However if implemented, it will have no impact on the device operation. Usually this feature is defined by the NXP I2C specification to bring the device out of a bus hang situation, which can arise when the I2C communication is terminated abruptly. Firmware Compatibility The I2C master firmware for the I2C EEPROM access will work as-is for the I2C F-RAM. This section discusses various operations in the system that can be improved by firmware updates when migrating from I2C EEPROM to the I2C F-RAM solution. 4.1 Multiple Pages in EEPROM Versus Single Page in F-RAM EEPROMs are written or programmed on a page-by-page basis. A typical page size of a 1-Mb EEPROM device is 256 bytes (2 Kb). This means that to write the full EEPROM memory, the host controller needs to initiate 512 page-write operations. It also needs to track the count of the total data bytes written in an individual page to prevent address counter rollover. F-RAM does not use the page architecture; therefore, the entire memory array can be treated as one page. The entire F-RAM array can be written in the burst mode with a single write command. Once the internal address counter reaches the last F-RAM location, the counter rolls over to the start address, 0h. Because the I2C F-RAM contains a single page, the host controller is required to keep track of only one counter, as opposed to tracking two counters for the page count and the byte count in a page. The I2C F-RAM simplifies firmware design by reducing the number of execution steps. Figure 3 demonstrates writing in I2C EEPROM versus writing in I2C F-RAM. www.cypress.com Document No. 001-97798 Rev. ** 7 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ Figure 3. Write Operation in I2C EEPROM and I2C F-RAM I2C master initiates write command I2C EEPROM Write I2C master sends data byte YES Is burst write continuing? NO Byte (address) counter will roll over to the start address of the page NO NO Is page boundary reached? YES YES Is page counter incremented? YES Is write continuing? NO I2C master sends STOP to initiate the write cycle NO Is write cycle completed? YES I2C master sends STOP, followed by START or Re-START to initiate new operation I2C master initiates write command I2C F-RAM Write I2C master sends data byte YES Is burst write continuing? NO YES NO Byte (address) counter will roll over to the start address of the memory Is page boundary reached? YES Is write continuing? NO I2C master sends STOP, followed by START or Re-START to initiate new operation www.cypress.com Document No. 001-97798 Rev. ** 8 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ 4.2 Page Write Delay EEPROMs require a page write delay, tWC (typically 5 ms), to transfer buffer data into the nonvolatile EEPROM. EEPROM shows busy and returns NACK during tWC time. Firmware can either wait for a fixed write cycle delay, tWC, or implement acknowledgement (ACK) polling. Figure 4 shows the ACK polling method to complete the EEPROM write cycle. The EEPROM page size varies between densities or between different vendors’ products for the same density. The system firmware must be designed to accommodate the page size variation and the page write delay between different EEPROM parts. The page write delay is not required in the I2C F-RAM; therefore, the write delay can be eliminated in the firmware to improve the system’s nonvolatile write performance. Figure 4. EEPROM Versus F-RAM Write Cycle EEPROM Write Cycle F-RAM Write Cycle (next operation after tWC, ACK polling or fixed delay) (immediate next operation, no ACK Polling or fixed delay) I2C master sends write command F-RAMs are immediately ready for the next operation unlike EEPROMs. Some controllers use fixed delay instead of ACK polling I2C master sends STOP condition to initiate write cycle I2C master sends STOP condition to stop/terminate current write cycle I2C master sends START command I2C master sends START command I2C master sends slave ID with R/W = 0 Did device send acknowledge ACK = 0? I2C master sends write command I2C master can initiate the next operation (any operation) NO YES Is the next operation memory write? NO YES I2C master sends address and receives ACK; sends data, continue write operation www.cypress.com I2C master sends STOP followed by START or Re-START Document No. 001-97798 Rev. ** 9 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ 5 Benefits of Migrating to I2C F-RAM This section describes the benefits of migrating from an I2C EEPROM to an I2C F-RAM solution. 5.1 Zero Clock Cycle Write Latency A typical EEPROM requires a 5-ms write cycle to transfer its page data to a nonvolatile EEPROM cell. This results in a long write time when several kilobytes of data need to be written. In contrast, with F-RAM, all writes occur at the bus speed, with no memory-based latency. The following Example demonstrates the F-RAM nonvolatile write performance improvement over an EEPROM due to zero clock cycle write latency. Figure 5 illustrates the impact of the write latency. 5.1.1 Example Equation 1 determines the total time to write in I2C EEPROM. 𝑇1 (𝐸𝐸𝑃𝑅𝑂𝑀) = Equation 1 𝑁𝑥8 𝑓 𝑥1000 + 𝑁 𝑃𝑆 𝑥 𝑇𝑤𝑐 Where: T1 – Total time to write in EEPROM (ms) N – Number of data bytes to be transferred over I2C bus f – I2C frequency (HZ) PS – EEPROM page size Twc – EEPROM write cycle time (ms) Equation 2 determines the total time to write in I2C F-RAM. 𝑇2 (F-RAM) = Equation 2 𝑁𝑥8 𝑓 𝑥1000 Where: T2 – Total time to write in F-RAM (ms) N – Number of data bytes to be transferred over I2C bus f – I2C frequency (HZ) EEPROM Write Time Example A 1-MHz I2C EEPROM with a 128-KB (1-Mb) density, 256-byte page, and 5-ms page write cycle time (tWC) takes about 28 ms to back up 8 Kb (4 pages) of data: 𝑇1 (𝐸𝐸𝑃𝑅𝑂𝑀) = 1024𝑥8 1024 𝑥1000 + 𝑥 5 = 28.192 𝑚𝑠 1000000 256 Similarly, it takes 3.608 seconds to back up 128-KB (1-Mb) of data in I2C EEPROM: 𝑇1 (𝐸𝐸𝑃𝑅𝑂𝑀) = 128𝑥1024𝑥8 1024𝑥128 𝑥1000 + 𝑥 5 = 3608 𝑚𝑠 𝑜𝑟 3.608 𝑠𝑒𝑐𝑜𝑛𝑑𝑠 1000000 256 F-RAM Write Time Example A 1-MHz I2C F-RAM with a 128-KB (1-Mb) density takes about 8 ms to back up 8 Kb of data: 𝑇2 (F-RAM) = 1024𝑥8 𝑥1000 = 8.192 𝑚𝑠 1000000 Similarly, it takes 1.049 seconds to back up 128 Kb (1 Mb) of data in I2C F-RAM: 𝑇2 (F-RAM) = www.cypress.com 1024𝑥128𝑥8 𝑥1000 = 1049 𝑚𝑠 𝑜𝑟 1.049 𝑠𝑒𝑐𝑜𝑛𝑑𝑠 1000000 Document No. 001-97798 Rev. ** 10 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ In addition, EEPROM can have varying page sizes for the same density; in this example, considering a lower page size EEPROM will require more page write operations and hence a longer time to complete the write cycle. The result will be additional write delays. Because F-RAM is not paged memory, the time to write a given set of data to it remains the same across all memory density options. Table 5 and Figure 5 illustrate the time to write to nonvolatile memory in F-RAM and EEPROM. Table 5. Time to Write to EEPROM and F-RAM Using1-MHz I2C Interface Time to Write (ms) to Nonvolatile Memory Data Bytes F-RAM EEPROM 1 0.008 5.008 16 0.128 5.128 32 0.256 5.256 64 0.512 5.512 128 1.024 6.024 256 2.048 7.048 512 4.096 14.096 1024 8.192 28.192 2048 16.384 56.384 Note: The calculation in Table 5 does not include the overhead for sending the control and address bytes before sending the data bytes to be written. A multipage write operation in the I2C EEPROM requires a new I2C write command to be sent for every page write. Figure 5. Write Performance in EEPROM Versus F-RAM 5.2 Low-Power Design F-RAM devices consume about one-third of the active current of EEPROM, while the standby/sleep current specifications of F-RAM are almost equal to those of EEPROM. This difference in active current has a huge impact on power consumption, especially when applications such as smart e-meters are write intensive due to frequent data logging. In addition to higher active current, EEPROM incurs an additional page write delay that causes the device to remain in active mode for an extended period, increasing power consumption. The amount of energy required to write to I2C F-RAM and I2C EEPROM is calculated using the Energy Calculation Example. Table 6 compares the energy consumption of F-RAM and EEPROM, as shown in Figure 6. This comparison demonstrates energy consumption. www.cypress.com Document No. 001-97798 Rev. ** 11 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ 5.2.1 Energ y Calculation Example Equation 3 determines the energy consumed by F-RAM and EEPROM during a write cycle: Equation 3 𝐸 =𝑉𝑥𝐼𝑥𝑡 Where: V – Operating voltage I – Active current during write t – Total time to write data to nonvolatile memory Table 6. Energy to Write to EEPROM and F-RAM Nonvolatile Memory Write Energy (µJ) Write Data Bytes F-RAM EEPROM 1 0.0096 45.072 16 0.1536 46.152 32 0.3072 47.304 64 0.6144 49.608 128 1.2288 54.216 256 2.4576 63.432 512 4.9152 126.864 1024 9.8304 253.728 2048 19.6608 507.456 Notes: 1. 2. A typical 3-V, 1-Mb I2C EEPROM consumes 3 mA of active current during the write operation. Therefore, the amount of energy an I2C EEPROM will require to write 128 bytes (1 Kb) of data is 54.22 µJ (3.0 V x 3 mA x 6.024 ms). A typical 3-V, 1-Mb I2C F-RAM consumes 0.4 mA of active current during the write operation. Therefore, the amount of energy an I2C F-RAM will require to write 128 bytes (1 Kb) of data is 1.23 µJ (3.0 V x 0.4 mA x 1.024 ms). Figure 6. Energy Consumption During Data Write to EEPROM Versus F-RAM www.cypress.com Document No. 001-97798 Rev. ** 12 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ 5.3 No Multidevice Design Required The EEPROM write operation has two stages of data transfer. Data is written to the page buffer, and then a nonvolatile memory write cycle occurs. During the write cycle, EEPROM access is disabled; therefore, the next access cannot start until the ongoing write cycle is complete. The I2C F-RAM, on the other hand, writes data at the bus speed. Therefore, it does not require pipeline implementation, simplifying the system firmware architecture and reducing the development cycle time and associated test overhead. 5.4 No Page Size Restriction The EEPROM page size can vary by density. So, the firmware program to interface to an EEPROM must be written flexibly and tested over a range of density options to support varying densities for different product versions. F-RAM imposes no page size restriction, enabling you to write arbitrarily sized blocks of data, independent of the total size of memory in use. 5.5 No Wear Leveling or Age Tracking Required All systems that require frequent write to EEPROM use careful address management. This method, called “wear leveling,” aims to equalize the number of times each page is written. Wear leveling is used in EEPROM to increase the effective endurance limit. In a wear-leveling implementation, the entire memory array is divided into multiple segments that are mapped to identical addresses of a microcontroller or processor. For example, if a write happens to some address location(s) in the current memory segment, the subsequent write to the same address location(s) will be executed in a different segment. The wear-leveling implementation is illustrated in Figure 7. Figure 7. Wear-Leveling Mechanism in EEPROM Memory Segment-4 4th write P1, P2 2 1 Memory Segment-3 3rd write P1, P2 Pn P3 P2 2 1 P1 Data Stream 2nd write P1, P2 Memory Segment-2 Physically divided into four segments but they are logically mapped to the same controller memory. 2 1 Aging Table 1st write P1,P2 Memory Segment-1 2 1 Wear leveling requires a fairly sophisticated driver routine in the controller, through which all nonvolatile accesses are managed. This routine translates the internal addressing of data structures into a physical addressing scheme for the memory. Usually, an “aging table” on the memory array tracks how the device is being used. This consumes a significant amount of code space in a miniature filing system. During an architectural change, it increases the design cycle time when migrating to a new processor family. A typical EEPROM device offers an endurance cycle of 106, whereas the endurance count for the F-RAM device is 1014, which is orders of magnitude higher (100 million times) than the typical EEPROM endurance cycle. Therefore, to match the F-RAM endurance, a system would require 100 million EEPROM devices or an EEPROM device with 100 million times the F-RAM density, which is virtually impossible. www.cypress.com Document No. 001-97798 Rev. ** 13 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ 5.6 No Action Required After Power Failure Data immediately becomes nonvolatile after it is written to F-RAM. This is one of the key benefits of using an F-RAM device: It increases confidence in system data integrity under extreme fault conditions. All writes happen directly to the nonvolatile memory. Therefore, no power backup or extended power supply is needed to save the data after a power failure. In contrast, to save valuable data in an EEPROM-based system, the controller must initiate and execute a complete write cycle to the desired data block size when a power fault is detected. The main power supply must store sufficient energy to reliably power the controller and its peripherals throughout this process. The controller must be protected against crashes caused by a rapid transition on the power supply during power failure. The system firmware must be thoroughly tested over a range of error conditions to ensure that the correct action is carried out at whatever system state existed before the power failure. 6 Summary Migrating from the I2C EEPROM to Cypress’s I2C F-RAM improves system performance, reliability, and energyefficiency. The I2C F-RAM industry-standard pin and package configuration and electrical compatibility simplify the migration. There are a few differences between devices, highlighted in this application note, that need to be considered. However, these differences typically do not preclude migration in most applications. About the Author Name: Shivendra Singh Title: Applications Engineer Principal www.cypress.com Document No. 001-97798 Rev. ** 14 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ Document History Document Title: AN97798 – Migrating from I2C EEPROM to Cypress's I2C F-RAM™ Document Number: 001-97798 Revision ** ECN 4911616 www.cypress.com Orig. of Change ZSK Submission Date 09/08/2015 Description of Change New application note. Document No. 001-97798 Rev. ** 15 Migrating From I2C EEPROM to Cypress's I2C F-RAM™ Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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