ATMEL TH7804ACC

Features
• Pixel Size: 13 µm x 13 µm (13 µm pitch)
• High Data Output Rate: 20 MHz typ
• High Responsivity and Resolution over a Wide Spectral Range: from Blue (400 nm) up
to Near Infrared (1100 nm)
• Improved Dark Signal and Photo Response Uniformity
• Low Temporal Noise and High Dynamic Range: Over 6000/1
• Ease and Flexibility of Operation:
– Only two External Basic Drive Clocks
– Internal or External Sample and Reset Clocks
• 24-lead DIL Package
Pin Identification
Pin Number
Symbol
Designation
1
VOSA
Video Output Signal A (Odd Channel)
2
ΦECHA
A Channel Sample-and-hold Gate Input
3
SΦECHA
A Channel Internal Sample Clock-output
4
ΦRA
A Channel External Reset Clock Input
8
VDD
Output Amplifier Drain And Internal Logic Supply
9
TP3
Test Point 3
10
TP2
Test Point 2
11
VT
Register And Photosensitive Zone DC Bias
12
TP1
Test Point 1
13
VSS
Substrate Bias (Ground)
15
ΦP
Transfer Clock
16
ΦT
Register Transport Clock
17
VGS
Output Gate DC Bias
18
ΦRB
B Channel External Reset Clock Input
19
VINH
Internal Sample Clock Inhibition
21
SΦECHB
B Channel Internal Sample Clock Input
22
ΦECHB
B Channel Sample-and-hold Gate Input
23
VOSB
Video Output Signal B (Even Channel)
24
VDR
Reset DC Bias
5, 6, 7, 14, 20
DNC
Do Not Connected
VOSA
ECHA
S ECHA
RA
DNC
DNC
DNC
VDD
TP3
TP2
VT
TP1
1
24
2
23
3
22
4
21
5
20
6
19
TH7804A
7
18
8
17
9
16
10
15
11
14
12
13
Linear Charged
Couple Device
(CCD) Image
Sensor 1024
Pixels
TH7804A
VDR
VOSB
ECHB
S ECHB
DNC
VINH
RB
VGS
T
P
DNC
VSS
Rev. 1989A–IMAGE–05/02
1
Absolute Maximum Ratings*
Storage Temperature ..................................... -55°C to +150°C
Operating Temperature....................................... 0°C to +70°C
Thermal Cycling..........................................................15°C/mn
*NOTICE:
Stresses above those listed under absolute maximum ratings may cause permanent device failure. Functionality at or above these limits is not
implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
Maximum Voltage:
• Pins: 2, 4, 8,12,15,16,18,19, 22, 24 ................-0.3V to +18V
• Pins: 9,10,11,17 .............................................. -0.3V to +18V
• Pin: 13 .............................................................................. 0V
Operating Range
The operating range defines the temperature limits between which functionality is guaranteed: 0°C to 70°C.
Operating Precautions
Shorting the video output to VSS or VDD, even temporarily, can permanently damage the
output amplifier.
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TH7804A
1989A–IMAGE–05/02
TH7804A
Operating Conditions (T = 25°)
Table 1. DC Bias Characteristics
Value
Parameter
Symbol
Min.
Typ.
Max
Unit
Output Amplifier Drain Supply
VDD
14
15
16
V
Reset DC Bias
VDR
VDD - 2.4
VDD - 2
VDD - 1
V
Output Gate DC Bias
VGS
5.5
6
6.5
V
Photosensitive Zone And
Register DC Bias
VT
0.95 VTN
VTN
1.05 V TN
V
Substrate Bias
VSS
0.0
0.0
V
Test Point 1
TP1
VDD
V
(2)
TP2, TP3
VSS
V
(2)
Tests Points 2 And 3
Notes:
Remark
(1)
1. Nominal value of VT:
VTN = 6.7V if ΦT clock levels are at their typical value.
2. No use for operation. For testing purpose only.
V
TN
VΦT )HIGH + ( VΦT )LOW ± 5%
= (---------------------------------------------------------------------2
Basic Internal
Configuration
SΦECHA and ΦRA
SΦECHB and ΦRA
internal to TH7804A
Table 2. Selection of Nominal Mode
Option
Implementation
Internal Sampling
VINH (19) Connected to VSS
SΦECHA (3) and ΦECHA (2) Strapped
SΦECHB (21) and ΦECHB (22) Strapped
Internal Reset
ΦRA (4) and ΦRB (18) Connected to VDD
Note:
Remarks
(1)
see note
1. Make the straps as short as possible to avoid any parasitic coupling to these connections. The load capacitance introduced
by the strap should not exceed 5 pF.
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1989A–IMAGE–05/02
Figure 1. Basic Test Configuration
Figure 2. Timing Diagram in Basic Mode
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1989A–IMAGE–05/02
TH7804A
Table 3. Drive Clock Characteristics (see Figure 2)
Value
Parameter
Transfer Clock
Register Transport Clock
Symbol
ΦP, ΦT
Logic
Min.
Typ.
Max.
High
11
13
14
Low
0.0
0.4
0.6
Unit
Remark
V
(1)
Register Transport Clock
Capacitance
CΦT
400
700
pF
Transfer Clock Capacitance
CΦP
130
200
pF
Note:
1. Transients under 0.0V in the clock pulses will lead to charge injection, causing a localized increase in the dark signal. If such
spurious negative transients are present, they can be suppressed by inserting a serial resistor of appropriate value (typically
20 to 100Ω) in the corresponding driver output.
Table 4. Static and Dynamic Electrical Characteristics
Value
Parameter
DC Output Level
Output Impedance
Symbol
Min.
Typ.
Max.
Logic
VREF
8
10
12
V
ZS
500
Ω
Remark
Register Single-stage Transfer
Efficiency
CTE
99.992
99.998
%
VOS = 1V (1)
Max. Data Output Frequency
FS max
12
20
MHz
(2)
µA
VIN = 15V
All other pins: 0V
Input Current On Pins: 2, 9, 10,
11, 12, 15, 16, 17, 18, 22
Ie
Peak Current Sink on ΦT Clock
(IΦT)P
250
mA
tRISE = 15 ns
Peak Current Sink on ΦP Clock
(IΦP)P
80
mA
tRISE = 15 ns
Output Amplifier + Internal Logic
Supply Current
IDD
17
mA
VINH = 0V
VDD = 15V
Static Power Dissipation
PD
255
mW
VINH = 0V
VDD = 15V
Notes:
2
300
1. VOS = average video output voltage.
2. Fs = 2 F ΦT. The minimum clock frequency is limited by the increase in dark signal.
Electro-optical
Performance
General measurement conditions: TC = 25°C; Ti = 1 ms; FΦT = 2.5 MHz (FDATA = 5 MHz)
Light source: tungsten filament lamp (2854 K) + B6 38 filter (2 mm thick), F/3.5 aperture.
The filter limits the spectrum to 700 nm; in these conditions 1µJ/cm2 corresponds to 3.5
lux.s.
Operating conditions (see Figure 1).
First and last pixels, as well as reference elements, are excluded from the specification.
Measurements taken on each output in succession.
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1989A–IMAGE–05/02
Table 5. Electro-optical Performance
Value
Parameter
Symbol
Min.
Typ.
Max.
Unit
Remark
Saturation Output Voltage
VSAT
1.3
1.8
2.3
V
(1) (2)
Saturation Exposure
ESAT
Responsivity
R
4.5
0.30
µJ/cm2
6
V/µJ/cm2
Responsivity Unbalance
∆R/R
2
8
%
(3)
Photo Response Non-uniformity
Peak-to-peak
PRNU
±3
±10
% VOS
VOS = 50 mV
to 1V
Contrast Transfer Function at FN
(38 I p/mm)
CTF
70
%
VOS = 0.9V
180
µVrms
(4)
Temporal Noise In Darkness
Dynamic Range (Relative to rms
Noise)
DR
Average Dark Signal
VDS
0.08
0.5
mV
DSNU
0.15
0.5
mV
Dark Signal Non-uniformity
Peak-to-peak
Notes:
4000
6000
1. Value measured with respect to zero reference level (see Figure 2).
2. Conversion factor is typically 1.5 µV/e-.
3. ∆R/R is defined as
200
RA – RB
---------------------------------RA + RB
where RA is responsivity of video output A, RB is responsivity of video output B.
4. Measured in Correlated Double Sampling (C.D.S.) mode.
Figure 3. Typical Spectral Response
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TH7804A
1989A–IMAGE–05/02
TH7804A
Figure 4. CTF Typical Curves (2854 K Source)
Electro-optical Performance Without Infrared Cut-off Filtering
The TH7804A’s special semiconductor process enables it to exploit the silicon's high
near infrared sensitivity while maintaining good imaging performance in terms of
response uniformity and resolution. Typical changes in performance with and without IR
filtering are summarized below.
With IR Cut-off Filter
No IR Cut-off Filter
Average Video Signal Due to a Given Scene Illumination
VOS
VOS x 4
PRNU (Single Defects Excluded)
±5%
±5%
CTF at Nyquist Frequency
70%
50%
Complementary
Operating Modes
TH7804A may be used in several configurations in regards to video output sampling and
charge sensing reset.
1. Sampling Options:
Inhibition of internal sampling pulses allows for two possibilities:
a. no sampling: video output delivered in unsampled form,
b. sampling by external clocks: external sampling pulses directly applied to
ΦECHA, ΦECHB inputs.
If internal sampling clocks SΦ ECHA and S ΦECHB are not used, it is recommended of
unpower the corresponding clock drivers, as this will greatly reduce on-chip power
consumption.
2. External Reset Option:
The position and period of the charge reset clocks may be optimized by using external
clocks on ΦRA and ΦRB inputs. This is specially interesting to optimize the video outputs
for Correlated Double Sampling (in order to reduce noise and improve S/N ratio).
Control signals to be applied in the different configurations are shown in Table 6.
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1989A–IMAGE–05/02
Table 6. Selection of Operating Modes
Option
Implementation
No Sampling
ΦECHA (2) and ΦECHB (22) connected to VDD
SΦECHA (3) and SΦECHB (21) unconnected
VINH (19) connected to VDD
Sampling by External Clocks
Sampling clocks connected to ΦECHA ΦECHB
SΦECHA and SΦECHB unconnected
VINH (19) connected to VDD
Reset Control by External Clocks
Note:
Remarks
(1)
see Figure 5 for
sampling clock timing
(1)
Ext. ΦRA on ΦRA (4) input
Ext. ΦRB on ΦRB (18)
see Figure 4 for
reset clock timing
1. Drain supply current IDD decreases from 10 mA to 8 mA typically when internal sampling clock is disabled.
Table 7. External ΦRA, ΦRB, ΦECHA, ΦECHB Clock Characteristics
Values
Parameter
External Reset Clock
Sampling Clocks
Reset and Sampling Clock
Capacitance
Symbol
Logic
Min.
Typ.
Max.
Unit
ΦRA, ΦRB
ΦECHA, ΦECHB
High
12
12.5
13
V
Low
0.0
0.4
0.6
V
10
15
pF
CΦRA, CΦRB
CΦECHA, CΦECHB
Insertion of a serial resistor (typically 100Ω) at the driver output avoids spurious negative transients.
8
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1989A–IMAGE–05/02
TH7804A
Figure 5. Timing Diagram — Clocks and Video Output Timing Diagram With and Without On-chip Sampling.
External reset clocks improve electro-optical performance, as listed below. Other operating conditions and other electrooptical parameters remain unchanged.
Table 8. Performance Improvements with External ΦRA and ΦRB Configuration
Value
Parameter
Saturation Output Voltage
Responsivity
Dynamic Range
Symbol
Typ.
Unit
VSAT
2.0
V
R
8
V/µJ/cm2
DR
8000
Electro-optical performances obtained with complementary modes are not guaranteed for the standard products.
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1989A–IMAGE–05/02
Outline Drawing
Z = 1.28 ± 0.23
2.16
Notes:
1. If an optical reference is needed, it is recommended to use the window face plane.
2. Variation of Z (azimuth) on the photosensitive area of a device is ≤ ±0.1 mm.
3. Value and tolerance of Y are applicable to each individual pixel of the photosensitive line.
Ordering Code
10
TH7804ACC
TH7804A
1989A–IMAGE–05/02
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Printed on recycled paper.
1989A–IMAGE–05/02
0M