ATMEL AT24C128SC-10WI

Features
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Low-voltage and Standard-voltage Operation, VCC = 2.7V to 5.5V
Internally Organized 16,384 x 8 and 32,768 x 8
2-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
1 MHz (5V) and 400 kHz (2.7V) Compatibility
64-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Typical)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 40 Years
– ESD Protection: > 4000V
Description
The AT24C128SC/256SC provides 131,072/262,144 bits of serial electrically erasable
and programmable read only memory (EEPROM) organized as 16,384/32,768 words
of 8 bits each. The devices are optimized for use in smart card applications where lowpower and low-voltage operation may be essential. The devices are available in several standard ISO 7816 smart card modules (see Ordering Information). All devices
are functionally equivalent to Atmel Serial EEPROM products offered in standard IC
packages (PDIP, SOIC, TSSOP, dBGA), with the exception of the slave address and
Write Protect functions which are not required for smart card applications.
Table 1. Pin Configurations
Pad Name
Description
VCC
Power Supply Voltage
C1
GND
Ground
C5
SCL
Serial Clock Input
C3
SDA
Serial Data Input/Output
C7
NC
No Connect
Two-wire Serial
EEPROM Smart
Card Modules
128K (16,384 x 8)
256 (32,768 x 8)
AT24C128SC
AT24C256SC
ISO Module Contact
C2, C4, C6, C8
Figure 1. Card Module Contact
VCC
NC
1661B–SEEPR–04/04
1
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground ........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC Output Current........................................................ 5.0 mA
Figure 2. Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or opencollector devices.
Memory Organization
2
AT24C128SC/256SC, 128K/256K SERIAL EEPROM: The 128K/256K is internally
organized as 256/512 pages of 64-bytes each. Random word addressing requires a
14/15-bit data word address.
AT24C128SC/AT24C256SC
1661B–SEEPR–04/04
AT24C128SC/AT24C256SC
Pin Capacitance
Table 2. Pin Capacitance (1)
Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +2.7V.
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (SCL)
6
pF
VIN = 0V
Symbol
Test Condition
CI/O
CIN
Note:
This parameter is characterized and is not 100% tested.
DC Characteristics
Table 3. DC Characteristics (1)
Symbol
Parameter
VCC
Supply Voltage
ICC1
Supply Current
VCC = 5.0V
Read at 400 kHz
ICC2
Supply Current
VCC = 5.0V
Write at 400 kHz
ISB
Standby Current)
VCC = 2.7V
Test Condition
ILI
Input Leakage Current
ILO
Output Leakage
Current
Max
Units
5.5
V
1.0
2.0
mA
2.0
3.0
mA
2.0
µA
VIN = VCC or GND
6.0
VIN = VCC or GND
0.10
3.0
µA
0.05
3.0
µA
−0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
0.4
V
VOUT = VCC or GND
Input Low Level(2)
(2)
VIH
Input High Level
VOL
Output Low Level
Note:
Typ
2.7
VCC = 5.5V
VIL
Min
VCC = 3.0V
IOL = 2.1 mA
1. Applicable over recommended operating range from: TAC = 0°C to +70°C, VCC = +2.7V to +5.5V (unless otherwise noted).
2. VIL min and VIH max are reference only and are not tested.
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1661B–SEEPR–04/04
AC Characteristics
Table 4. AC Characteristics(1)
2.7-volt
Min
5.0-volt
Symbol
Parameter
Max
Min
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
1.3
0.4
µs
tHIGH
Clock Pulse Width High
0.6
0.4
µs
tAA
Clock Low to Data Out Valid
0.05
tBUF
Time the bus must be free before a new
transmission can start(2)
1.3
0.5
µs
tHD.STA
Start Hold Time
0.6
0.25
µs
tSU.STA
Start Set-up Time
0.6
0.25
µs
tHD.DAT
Data In Hold Time
0
0
µs
tSU.DAT
Data In Set-up Time
100
100
ns
tR
Inputs Rise Time(2)
400
(2)
0.9
0.05
Max
Units
1000
kHz
0.55
µs
0.3
0.3
µs
300
100
ns
tF
Inputs Fall Time
tSU.STO
Stop Set-up Time
0.6
0.25
µs
tDH
Data Out Hold Time
50
50
ns
tWR
Write Cycle Time
Endurance
Notes:
4
(2)
25°C, Page Mode
5
1M
5
1M
ms
Write Cycles
1. Applicable over recommended operating range from TA = 0°C to +70°C, VCC = +2.7V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 3.
2. This parameter is characterized and is not 100% tested.
3. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.7V, 5V),
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤ 50ns
Input and output timing reference voltages: 0.5V CC
AT24C128SC/AT24C256SC
1661B–SEEPR–04/04
AT24C128SC/AT24C256SC
Device Operation
CLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C128SC/256SC features a low power standby mode
which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the
completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition as SDA is high.
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1661B–SEEPR–04/04
Timing Diagrams
Bus Timing
Figure 3. Bus Timing
Note:
Write Cycle Timing
SCL: Serial Clock; SDA: Serial Data I/O
Figure 4. Write Cycle Timing
tWR(1)
Note:
Data Validity
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to
the end of the internal clear/write cycle.
SCL: Serial Clock; SDA: Serial Data I/O
Figure 5. Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
6
AT24C128SC/AT24C256SC
1661B–SEEPR–04/04
AT24C128SC/AT24C256SC
Start and Stop
Definition
Figure 6. Start and Stop Definition
SDA
SCL
START
Output Acknowledge
STOP
Figure 7. Output Acknowledge
SCL
DATA IN
DATA OUT
START
ACKNOWLEDGE
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1661B–SEEPR–04/04
Device Addressing
The 128K/256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 8). The device
address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices.
The next three bits of the device address word are unused. These three unused bits
should be set to “0”.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the device will return to a standby state.
Figure 8. Device Address
1
0
MSB
Write Operations
1
0
0
0
0
R/W
LSB
BYTE WRITE: A write operation requires two 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device,
such as a microcontroller, then must terminate the write sequence with a stop condition.
At this time the EEPROM enters an internally-timed write cycle, t WR, to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not
respond until the write is complete (refer to Figure 9).
Figure 9. Byte Write
PAGE WRITE: The 128K/256K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 63
more data words. The EEPROM will respond with a zero after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (refer
to Figure 10).
The data word address lower six bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 64 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address “roll over” during write is from
the last byte of the current page to the first byte of the same page.
8
AT24C128SC/AT24C256SC
1661B–SEEPR–04/04
AT24C128SC/AT24C256SC
Figure 10. Page Write
Note:
1. * = DON’T CARE bit
2. † = DON’T CARE bit for the 128K
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero, allowing the read or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page, to the first
byte of the first page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (refer to Figure 11).
Figure 11. Current Address Read
S
T
A
R
T
DEVICE
ADDRESS
R
E
A
D
S
T
O
P
SDA LINE
M
S
B
L R A
S / C
B WK
DATA
N
O
A
C
K
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
9
1661B–SEEPR–04/04
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (refer to Figure 12).
Figure 12. Random Read
P0
Notes:
1. * = DON’T CARE bit
2. † = DON’T CARE bit for the 128K
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 13).
Figure 13. Sequential Read
10
AT24C128SC/AT24C256SC
1661B–SEEPR–04/04
AT24C128SC/AT24C256SC
AT24C128SC Ordering Information
Ordering Code
Package
Voltage Range
Operation Range
AT24C128SC-09AT
M2 – A Module
2.7V–5.5V
Commercial (0°C–70°C)
AT24C128SC-09BT
M2 – B Module
2.7V–5.5V
Commercial (0°C–70°C)
AT24C128SC-10WI
7 mil Wafer
2.7V–5.5V
Industrial (−40°C–85°C)
Package
Voltage Range
Operation Range
AT24C256SC-09AT
M2 – A Module
2.7V–5.5V
Commercial (0°C–70°C)
AT24C256SC-09BT
M2 – B Module
2.7V–5.5V
Commercial (0°C–70°C)
AT24C256SC-10WI
7 mil Wafer
2.7V–5.5V
Industrial (−40°C–85°C)
AT24C256SC Ordering Information
Ordering Code
Package Type(1)
Description
M2 – A Module
M2 ISO 7816 Smart Card Module
M2 – B Module
M2 ISO 7816 Smart Card Module with Atmel Logo
Note:
Formal drawings may be obtained from an Atmel sales office.
11
1661B–SEEPR–04/04
Smart Card Modules
Ordering Code: 09AT-00
Module Size: M2
Dimension*: 12.6 x 11.4 [mm]
Glob Top: Square: 8.6 x 8.6 [mm]
Thickness: 0.58 [mm] max
Pitch: 14.25 [mm]
Ordering Code: 09BT-00
Module Size: M2
Dimension*: 12.6 x 11.4 [mm]
Glob Top: Square: 8.6 x 8.6 [mm]
Thickness: 0.58 [mm] max
Pitch: 14.25 [mm]
*Note: The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions
of the module after excise or punching from the carrier tape are generally 0.4 mm greater in both directions
(i.e., a punched M2 module will yield 13.0 x 11.8 mm).
12
AT24C128SC/AT24C256SC
1661B–SEEPR–04/04
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1661B–SEEPR–04/04