ATMEL PC8260VTPU150

Features
• PC603e™ Microprocessor (Embedded PowerPC™ Core) at 100 - 200 MHz
•
•
•
•
•
•
•
– 140 MIPS at 100 MHz (Dhrystone 2.1)
– 280 MIPS at 200 MHz (Dhrystone 2.1)
– High-performance, Superscalar Microprocessor
– Disable CPU Mode
– Improved Low-power Core
– 16-Kbyte Data and 16-Kbyte Instruction Cache, Four-way Set Associative
– Memory Management Unit
– No Floating Point Unit
– Common On-chip Processor (COP)
System Integration Unit (SIU)
– Memory Controller, Including Two Dedicated SDRAM Machines
– PCI up to 66 MHz (Available in Subsequent Versions)
– Hardware Bus Monitor and Software Watchdog Timer
– IEEE 1149.1 JTAG Test Access Port
High-performance Communications Processor Module (CPM) with Operating
Frequency up to 166 MHz
– PowerPC and CPM May Run at Different Frequencies
– Supports Serial Bit Rates up to 710 Mbps at 133 MHz
– Parallel I/O Registers
– On-board 24 KBytes of Dual-port RAM
– Two Multi-channel Controllers (MCCs) Each Supporting 128 Full-duplex, 64-Kbps,
HDLC Lines
– Virtual DMA Functionality
Two Bus Architectures: One 64-bit PowerPC and One 32-bit Local Bus (or PCI on
PC8265)
Two UTOPIA Level-2 Master/Slave Ports, Both with Multi-PHY Support. One Can
Support 8/16 bit Data
Three MIL Interfaces
Eight TDM Interfaces (T1/E1), Two TDM Ports Can Be Glueless to T3/E3
Power Consumption: 2.5W at 133 MHz
PowerPC-based
Communications
Processors
PC8260
PowerQUICC II™
Description
The PC8260 PowerQUICC II™ is a versatile communications processor that integrates on one chip, a high-performance PowerPC (PC603e) RISC microprocessor, a
highly flexible system integration unit, and many communications peripheral controllers that can be used in a variety of applications, particularly in communications and
networking systems.
The core is an embedded variant of the PC603e microprocessor, specifically referred
to later in this document as the EC603e, with 16 Kbytes of instruction cache and 16
Kbytes of data cache and no floating-point unit (FPU). The system interface unit (SIU)
consists of a flexible memory controller that interfaces to almost any user-defined
memory system, a 60x-to-PCI bus bridge (available in future revisions) and many
other peripherals, making this device a complete system on a chip.
The communications processor module (CPM) includes all the peripherals found in
the PC860, with the addition of three high-performance communication channels that
support new emerging protocols (for example, 155-Mbps ATM and Fast Ethernet).
Equipped with dedicated hardware, the PC8260 can handle up to 256 full-duplex,
time-division, multiplexed logical channels.
Rev. 2131B–HIREL–02/03
1
Screening Quality
Packaging
This product is manufactured in full compliance with:
•
Upscreening based upon Atmel standards.
•
Full military temperature range (TJ = -55°C, TJ = +125°C)
•
Industrial temperature range (TJ = -40°C, TJ = +110°C)
•
Core power supply:
2.5V ± 5% (L-Spec for 200 MHz)
2.50V to 2.75V (R-Spec for 250 MHz) (tbc)
2
•
I/O power supply: 3.0V to 3.6V
•
480-ball Tape Ball Grid Array package (TBGA 37.5 mm x 37.5 mm)
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
PC8260 Architecture
General Overview
The PC8260 has two external buses to accommodate bandwidth requirements from the
highspeed system core and the very fast communications channels. The device is composed of the following three major functional blocks:
•
A 64-bit PowerPC core derived from the EC603e with MMUs and caches.
•
A system interface unit (SIU).
•
A communications processor module (CPM). Both the system core and the CPM
have an internal PLL, which allows independent optimization of the frequencies at
which they run. The system core and CPM are both connected to the 60x bus.
Figure 1. PC8260 Block Diagram
16-Kbyte
Instruction Cache
60x Bus
IMMU
EC603e
PowerPC
Core
60x-to-PCI Bus Bridge
(PC8265 only)
16-Kbyte
Data Cache
60x-to-Local Bus Bridge
DMMU
PCI/
Local
Bus
Memory Controller
Timers
Interrupt
Controller
24-Kbyte DualPort RAM
Bus Interface Unit
Serial DMAs
Parallel I/O
Baud Rate
Generator
MCC
MCC
Clock Counter
32-Bit RISC Communications
Processor (CP) and
Program ROM
FCC
FCC
FCC
SCC
SCC
4 Virtual
IDMAs
SCC
SCC
System Functions
SMC
SMC
SPI
I 2C
Time Slot Assigner
Serial Interface
2 UTOPIA
3 Mlls
Non-Multiplexed I/O
8 TDMs
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2131B–HIREL–02/03
EC603e Core
The EC603e core is derived from the PowerPC603e microprocessor without the floating-point unit and with power management modifications.The core is a highperformance low-power implementation of the PowerPC family of reduced instruction
set computer (RISC) microprocessors. The EC603e core implements the 32-bit portion
of the PowerPC architecture, which provides 32-bit effective addresses, integer data
types of 8, 16 and 32 bits. The EC603e cache provides snooping to ensure data coherency with other masters. This helps ensure coherency between the CPM and system
core.
The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a
64-bit split-transaction external data bus which is connected directly to the external
PC8260 pins.
The EC603e core has an internal common on-chip (COP) debug processor. This processor allows access to internal scan chains for debugging purposes. It is also used as
a serial connection to the core for emulator support.
The EC603e core performance for the SPEC 95 benchmark for integer operations
ranges between 4.4 and 5.1 at 200 MHz. In Dhrystone 2.1 MIPS, the EC603e is 280
MIPS at 200 MHz (compared to 86 MIPS of the PC860 at 66 MHz).
The EC603e core can be disabled. In this mode, the PC8260 functions as a slave
peripheral to an external core or to another PC8260 device with its core enabled.
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PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
System Interface Unit
(SIU)
The SIU consists of the following:
•
A 60x-compatible parallel system bus configurable to 64-bit data width. The PC8260
supports 64-, 32-, 16-, and 8-bit port sizes.The PC8260 internal arbiter arbitrates
between internal components that can access the bus (system core, PCI bridge,
CPM, and one external master). This arbiter can be disabled, and an external
arbiter can be used if necessary.
•
A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is
used to enhance the operation of the very high-speed communication controllers.
Without requiring extensive manipulation by the core, the bus can be used to store
connection tables for ATM or buffer descriptors (BDs) for the communication
channels or raw data that is transmitted between channels. The local bus is
synchronous to the 60x bus and runs at the same frequency.
•
The local bus can be configured as a 32-bit data and up to 66 MHz PCI (version 2.1)
bus. In PCI mode the bus can be programmed as a host or as an agent. The PCI
bus can be configured to run synchronously or asynchronously to the 60x bus. The
PC8260 has an internal PCI bridge with an efficient 60x-to-PCI DMA for memory
block transfers.
•
Applications that require both the local bus and PCI bus need to connect an external
PCI bridge.
•
A memory controller supporting 12 memory banks that can be allocated for either
the system or the local bus. The memory controller is an enhanced version of the
PC8260 memory controller. It supports three user-programmable machines.
Besides supporting all PC8260 features, the memory controller also supports
SDRAM with page mode and address data pipeline
•
Supports JTAG controller IEEE 1149.1 test access port (TAP).
•
A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt
timer, and other system functions useful in embedded applications.
•
Glueless interface to L2 cache and 4-/16-K-entry CAM.
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2131B–HIREL–02/03
Communication
The CPM contains features that allow the PC8260 to excel in a variety of applications
Processor Module (CPM) targeted mainly for networking and telecommunication markets.
The CPM is a superset of the PC8260 PowerQUICC CPM, with enhancements on the
CP performance and additional hardware and microcode routines that support high bit
rate protocols like ATM (up to 155 Mbps full-duplex) and Fast Ethernet (100 Mbps fullduplex).
The following list summarizes the major features of the CPM:
Software Compatibility
Issues
•
The communications processor (CP) is an embedded 32-bit RISC controller
residing on a separate bus (CPM local bus) from the 60x bus (used by the system
core). With this separate bus, the CP does not affect the performance of the
PowerPC core. The CP handles the lower layer tasks and DMA control activities,
leaving the PowerPC core free to handle higher layer activities. The CP has an
instruction set optimized for communications, but can also be used for generalpurpose applications, relieving the sys-tem core of small often repeated tasks.
•
Two serial DMAs (SDMAs) that can do simultaneous transfers, optimized for burst
transfers to the 60x bus and to the local bus.
•
Three full-duplex, serial fast communications controllers (FCCs) supporting ATM
(155 Mbps) protocol through UTOPIA2 interface (there are two UTOPIA interfaces
on the PC8260), IEEE 802.3 and Fast Ethernet protocols, HDLC up to E3 rates (45
Mbps) and totally transparent operation. Each FCC can be configured to transmit
fully transparent and receive HDLC, or vice-versa.
•
Two multichannel controllers (MCCs) that can handle an aggregate of 256 x 64
Kbps HDLC or transparent channels, multiplexed on up to eight TDM interfaces.
The MCC also supports super-channels of rates higher than 64 Kbps and
subchanneling of the 64-Kbps channels.
•
Four full-duplex serial communications controllers (SCCs) supporting
IEEE802.3/Ethernet, high-level synchronous data link control, HDLC, local talk,
UART, synchronous UART, BISYNC and transparent.
•
Two full-duplex serial management controllers (SMC) supporting GCI, UART, and
transparent operations.
•
Serial peripheral interface (SPI) and I2C bus controllers.
•
Time-slot assigner (TSA) that supports multiplexing of data from any of the four
SCCs, three FCCs, and two SMCs.
As much as possible, the PC8260 CPM features were made similar to those of the previous devices (PC860). The code ports easily from previous devices to the PC8260,
except for new protocols supported by the PC8260.
Although many registers are new, most registers retain the old status and event bits, so
an understanding of the programming models of the 68360, PC860, or PC850 is helpful.
Note that the PC8260 initialization code requires changes from the PC8260 initialization
code.
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PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Differences Between
PC860 and PC8260
Serial Protocol Table
The following PC860 features are not included in the PC8260:
•
On-chip crystal oscillators (must use external oscillator)
•
4 MHz oscillator (input clock must be at the bus speed)
•
Low power (standby) modes
•
Battery-backup real-time clock (must use external battery-backup clock)
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BDM (COP offers most of the same functionality)
•
True little endian mode (except the PCI bus)
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PCMCIA interface
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Infrared (IR) port
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QMC protocol in SCC (256 HDLC channels are supported by the MCCs)
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Multiply and accumulate (MAC) block in the CPM
•
Centronics port (PIP)
•
Asynchronous HDLC protocol (optional RAM microcode)
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Pulse-width modulated outputs
•
SCC Ethernet controller option to sample 1 byte from the parallel port when a
receive frame is complete.
•
Parallel CAM interface for SCC (Ethernet)
Table 1 summarizes available protocols for each serial port.
Table 1. PC8260 Serial Protocols
Port
Protocol
FCC
SCC
ATM (Utopia)
x
100BaseT
x
10BaseT
x
x
HDLC
x
x
HDLC_BUS
Transparent
SMC
x
x
x
x
UART
x
DPLL
x
Multichannel
MCC
x
x
x
x
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2131B–HIREL–02/03
Pin Assignment
Table 2 shows the pinout of the PC8260.
Table 2. Pinout
Pin Name
Ball
BR
W5
BG
F4
ABB/IRQ2
E2
TS
E3
A0
G1
A1
H5
A2
H2
A3
H1
A4
J5
A5
J4
A6
J3
A7
J2
A8
J1
A9
K4
A10
K3
A11
K2
A12
K1
A13
L5
A14
L4
A15
L3
A16
L2
A17
L1
A18
M5
A19
N5
A20
N4
A21
N3
A22
N2
A23
N1
A24
P4
A25
P3
A26
P2
A27
P1
A28
R1
A29
R3
A30
R5
8
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 2. Pinout (Continued)
Pin Name
Ball
A31
R4
TTO
F1
TT1
G4
TT2
G3
TT3
G2
TT4
F2
TBST
D3
TSIZ0
C1
TSIZ1
E4
TSIZ2
D2
TSIZ3
F5
AACK
F3
ARTRY
E1
DBG
V1
DBB/IRQ3
V2
D0
B20
D1
A18
D2
A16
D3
A13
D4
E12
D5
D9
D6
A6
D7
B5
D8
A20
D9
E17
D10
B15
D11
B13
D12
A11
D13
E9
D14
B7
D15
B4
D16
D19
D17
D17
D18
D15
D19
C13
D20
B11
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2131B–HIREL–02/03
Table 2. Pinout (Continued)
Pin Name
Ball
D21
A8
D22
A5
D23
C5
D24
C19
D25
C17
D26
C15
D27
D13
D28
C11
D29
B8
D30
A4
D31
E6
D32
E18
D33
B17
D34
A15
D35
A12
D36
D11
D37
C8
D38
E7
D39
A3
D40
D18
D41
A17
D42
A14
D43
B12
D44
A10
D45
D8
D46
B6
D47
C4
D48
C18
D49
E16
D50
B14
D51
C12
D52
B10
D53
A7
D54
C6
D55
D5
D56
B18
10
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 2. Pinout (Continued)
Pin Name
Ball
D57
B16
D58
E14
D59
D12
D60
C10
D61
E8
D62
D6
D63
C2
DPO/RSRV/EXT_BR2
B22
IRQ1/DP1/EXT_BG2
A22
IRQ2/DP2/TLBISYNC/EXT DBG2
E21
IRQ3/DP3/CKSTP_OUT/EXT BR3
D21
IRQ4/DP4/CORE_SRESET/EXT BG3
C21
IRQ5/DP5/TBEN/EXT_DBG3
B21
IRQ6/DP6/CSEO
A21
IRQ7/DP7/CSE1
E20
PSDVAL
V3
TA
C22
TEA
V5
GBL/IRQ1
W1
CI/BADDR29/IRQ2
U2
WT/BADDR30/IRQ3
U3
L2_HIT/IRQ4
Y4
CPU_BG/BADDR31/IRQ5
U4
CPU_DBG
R2
CPU_BR
Y3
CS0
F25
CS1
C29
CS2
E27
CS3
E28
CS4
F26
CS5
F27
CS6
F28
CS7
G25
CS8
D29
CS9
E29
CS10/BCTL1
F29
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2131B–HIREL–02/03
Table 2. Pinout (Continued)
Pin Name
Ball
CS11/APO
G28
BADDR27
T5
BADDR28
U1
ALE
T2
BCTL0
A27
PWE0/PSDQM0/PBS0
C25
PWE1/PSDDQM1/PBS1
E24
PWE2/PSDDQM2/PBS2
D24
PWE3/PSDDQM3/PBS3
C24
PWE4/PSDDQM4/PBS4
B26
PWE5PSDDQM5/PBS5
A26
PWE6/PSDDQM6/PBS6
B25
PWE7/PSDDQM7/PBS7
A25
PSDA10/PGL0
E23
PSDWE/PGPL1
B24
POE/OSDRAS/PGPL2
A24
PSDCAS/PGPL3
B23
PGTA/PUPMWAIT/PGPL4/PPBS
A23
PSDAMUX/PGPL5
D22
LWE0/LSDDQM0/LBS0
H28
LWE1/LSDDQM1/LBS1
H27
LWE2/LSDDQM2/LBS2
H26
LWE3/LSDDQM3/LBS3
G29
LSDA10/LGPL0
D27
LSDWE/LGPL1
C28
LOE/LSDRAS/LGPL2
E26
LSDCAS/LGPL3
D25
LGTA/LUPMWAIT/LGPL4/LPBS
C26
LGPL5
B27
LWR
D28
L A14
N27
L A15/SMI
T29
L A16
R27
L A17/CKSTP_OUT
R26
L A18
R29
L A19
R28
12
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 2. Pinout (Continued)
Pin Name
Ball
L A20
W29
L A21
P28
L A22
N26
L A23
AA27
L A24
P29
L A25
AA26
L A26
N25
L A27
AA25
L A28/CORE_SRESET
AB29
L A29
AB28
L A30
P25
L A31
AB27
LCL D0
H29
LCL D1
J29
LCL D2
J28
LCL D3
J27
LCL D4
J26
LCL D5
J25
LCL D6
K25
LCL D7
L29
LCL D8
L27
LCL D9
L26
LCL D10
L25
LCL D11
M29
LCL D12
M28
LCL D13
M27
LCL D14
M26
LCL D15
N29
LCL D16
T25
LCL D17
U27
LCL D18
U26
LCL D19
U25
LCL D20
V29
LCL D21
V28
LCL D22
V27
LCL D23
V26
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2131B–HIREL–02/03
Table 2. Pinout (Continued)
Pin Name
Ball
LCL_D24
W27
LCL_D25
W26
LCL_D26
W25
LCL_D27
Y29
LCL_D28
Y28
LCL_D29
Y25
LCL_D30
AA29
LCL_D31
AA28
LCL_DP0
L28
LCL_DP1
N28
LCL_DP2
T28
LCL_DP3
W28
IRQ0/NMI_OUT
T1
IRQ7INT_OUT/APE
D1
TRST
AH3
TCK
AG5
TMS
AJ3
TDI
AE6
TDO
AF5
TRIS
AB4
PORESET
AG6
HRESET
AH5
SRESET
AF6
QREQ
AA3
RSTCONF
AJ4
MODCK1/AP1/TC0/BNKSEL0
W2
MODCK2/AP2/TC1/BNKSEL1
W3
MODCK3/AP3/TC2/BNKSEL2
W4
XFC
AB2
CLKIN
AH4
PA0/RESTART1/DREQ/FCC2_UTM_TXADDRS
AC29
PA1/REJECT1/FCC2_UTM_TXADDR1/DONE3
AC25
PA2/CLK20/FCC2_UTM_TXADDR0/DACK3
AE28
PA3/CLK19/FCC2_UTM_RXADDR0/DACK4/L1RXD1A2
AG29
PA4/REJECT2/FCC2/RXADDR1/DONE4
AG28
PA5/RESTART2/DREQ4/FCC2_UTM RXADDR2
AG26
14
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 2. Pinout (Continued)
Pin Name
Ball
PA6/L1RSYNCA1
AE24
PA7/SMSYN2/L1TSYNCA1/L1GNTA1
AH25
PA8/SMRSXD2/L1RXD0A1/L1RXDA1
AF23
PA9/SMTXD2/L1TXD0A1
AH23
PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5
AE22
PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4
AH22
PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3
AJ21
PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2
AH20
PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3
AG19
PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2
AF18
PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1
AF17
PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD
AE16
PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD
AJ16
PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1
AG15
PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2
AJ13
PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3
AE13
PA22/FCC1_UT8_TXD3/FCC1_UT16_TXD11
AF12
PA23/FCC1_UT8_TXD2/FCC1_UT16_TXD10
AG11
PA24/FCC1_UT8_TXD1/FCC1_UT16_TXD9/MSNUM1
AH9
PA25/FCC1_UT8_TXD0/FCC1_UT16_TXD8/MSNUM0
AJ8
PA26/FCC1_UTM_RXCLAV/FCC1_UTS_RXCLAV/FCC1_MII_RX_ER
AH7
PA27/FCC1_UT_RXSOC/FCC1_MII_RX DV
AF7
PA28/FCC1_UTM_RXENB/FCC1_UTS_RXENB/FCC1_MII_TX_EN
AD5
PA29/FCC1_UT_TXSOC/FCC1_MII_TX_ER
AF1
PA30/FCC1_UTM_TXCLAV/FCC1_UTS_TXCLAV/FCC1_MII_CRS/FCC1_RTS
AD3
PA31/FCC1_UTM_TXENB/FCC1_UTS_TXENB/FCC1_MII_COL
AB5
PB4/FCC3_TXD3/FCC2_UT8_RXD0/L1RSYNCA2/FCC3_RTS
AD28
PB5/FCC3_TXD2/FCC2_UT8_RXD1/L1TSYNCA2/L1GNTA2
AD26
PB6/FCC3_TXD1/FCC2_UT8_RXD2/L1RXDA2/L1RXD0A2
AD25
PB7/FCC3_TXD0/FCC3_TXD/FCC2_UT8_RXD3/L1TXDA2/L1TXD0A2
AE26
PB8/FCC2_UT8_TXD3/FCC3_RXD0/FCC3 RXD/TXD3/L1RSYNCD1
AH27
PB9/FCC2_UT8_TXD2/FCC3_RXD1/L1TXD2A2/L1TSYNCD1/L1GNTD1
AG24
PB10/FCC2_UT8_TXD1/FCC3_RXD2/L1RXDD1
AH24
PB11/FCC3_RXD3/FCC2_UT8_TXD0/L1TXDD1
AJ24
PB12/FCC3_MII_CRS/L1CLKOB1/L1RSYNCC1/TXD2
AG22
PB13/FCC3_MII_COL/L1RQB1/L1TSYNCC1/L1GNTC1/L1TXD1A2
AH21
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2131B–HIREL–02/03
Table 2. Pinout (Continued)
Pin Name
Ball
PB14/FCC3_MIL_TX_EN/RXD3/L1RXDC1
AG20
PB15/FCC3_MIL_TX_ER/RXD2/L1TXDC1
AF19
PB14/FCC3_MIL_RX_ER/L1CLKOA1/CLK18
AJ18
PB17FCC3_MIL_RX_DV/L1RQA1/CLK17
AJ17
PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2
AE14
PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2
AF13
PB20/FCC2_UT8_RXD6/FCC2 RXD1/L1RSYNCD2/L1TXD1A1
AG12
PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/
L1TSYNCD2/L1GNTD2/L1TXD2A1
AH11
PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_L1RXD1A1/L1RXDD2
AH16
PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1RXDD2
AE15
PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2
AJ9
PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1
AE9
PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2
AJ7
PB27/FCC2_MII_COL/FCC2_UT8_TXD0/L1TXDC2
AH6
PB28/FCC2_MII RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1
AE3
PB29/FCC2_UTM_RXCLAV/FCC2_UTS_RXCLAV/
L1RSYNCB2/FCC2_MII_TX_EN
AE2
PB30/FCC2_MII_RX_DV/FCC2_UT_TXSOC/1RXDB2
AC5
PB31/FCC2_MII_TX_ER/FCC2_UT_RXSOC/L1TXDB2
AC4
PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2
AB26
PC1/DREQ2/BRGO6/L1RQA2
AD29
PC2/FCC3_CD/FCC2_UT8_TXD3/DONE2
AE29
PC3/FCC3_CTS/FCC2_UT8_TXD2/DACk2/CTS4
AE27
PC4/FCC2_UTM_RXENB/FCC2_UTS_RXENB/SI2_L1ST4/FCC2_CD
AF27
PC5/FCC2_UTM_TXCLAV/FCC2_UTS_TXCLAV/SI2_L1ST3/FCC2_CTS
AF24
PC6/FCC1_CD/L1CLKOC1/FCC1_UTM_RXADDR2/FCC1_UTS RXADDR2/
FCC1_UTM_RXCLAV1
AJ26
PC7/FCC1_CTS/L1RQC1/
FCC1_UTM_TXADDR2/FCC1_UTS_TXADDR2/FCC1_UTM_TSCLAV1
AJ25
PC8/CD4/RENA4/FCC1_UT16_TXD0/SI2_L1ST2/CTS3
AF22
PC9/CTS4/CLSN4/FCC1_UT16_TXD1/SI2_L1ST1/L1TSYNCA2/L1GNTA2
AE21
PC10/CD3/RENA3/FCC1_UT16_TXD2/SI1_L1ST4/FCC2_UT8_RXD3
AF20
PC11/CTS3/CLSN3/L1CLKOD1/L1TXD3A2/FCC2_UT8_RXD2
AE19
PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/FCC1_UTS_RXADDR1
AE18
PC13/CTS2/SLSN2/L1RQD1/FCC1_UTM_TXADDR1/FCC1_UTS_TXADDR1
AH18
PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0
AH17
16
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 2. Pinout (Continued)
Pin Name
Ball
PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/FCC1_UTS_TXADDR0
AG16
PC16/CLK16/TIN3
AF15
PC17/CLK15/TIN4/BRGO8
AJ15
PC18/CLK14/TGATE2
AH14
PC19/CLK13/BRGO7
AG13
PC20/CLK12/TGATE1
AH12
PC21/CLK11/BTGO6
AJ11
PC22/CLK10/DONE1
AG10
PC23/CLK9/BRGO5/DACK1
AE10
PC24/FCC2_UT8_TXD3/CLK8/TOUT4
AF9
PC25/FCC2_UT8_TXD2/CLK7/BRGO4
AE8
PC26/CLK6/TOUT3/TMCLK
AJ6
PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3
AG2
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2
AF3
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
AF2
PC30/FCC2_UT8_TXD3/CLK2/TOUT1
AE1
PC31/CLK1/BRGO1
AD1
PD4/BRGO8/L1TSYNCD1/L1GNTD1/FCC3_RTS/SMRXD2
AC28
PD5/FCC1_UT16_TXD3/DONE1
AD27
PD6/FCC1_UT16_TXD4/DACK1
AF29
PD7/SMSYN1/FCC1_UTM_TXADDR3/FCC1_UTS_TXADDR3/FCC1_TXCLAV2
AF28
PD8/SMRXD1/FCC2_UT_TXPRTY/BRGO5
AG25
PD9/SMTXD1/FCC2_UT_RXPRTY/BRGO3
AH26
PD10/L1CLKOB2/FCC2_UT8_RXD1/L1RSYNCB1/BRGO4
AJ27
PD11/L1RQB2/FCC2_UT8_RXD0/L1TSYNCB1/L1GNTB1
AJ23
PD12/SI1_L1ST2/L1RXDB1
AG23
PD13/SI1_L1ST1/L1RTDB1
AJ22
PD14/FCC1_UT16_RXD0/L1CLKOC2/L2CSCL
AE20
PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA
AJ20
PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO
AG18
PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI
AG17
PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM_RXCLAV3/
SPICLK
AF16
PD19/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM
TXCLAV3/SPISEL/BRGO1
AH15
PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2
AJ14
PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2
AH13
17
2131B–HIREL–02/03
Table 2. Pinout (Continued)
Pin Name
Ball
PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2
AJ12
PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1
AE12
PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1
AF10
PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1
AG9
PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1
AH8
PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1
AG7
PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1
AE4
PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/
FCC1 UTM RXCLAV2
AG1
PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1
AD4
PD31/RXD1
AD2
VCCSYN
AB3
VCCSYN1
B9
GNDSYN
AB1
THERMAL0 (thermal ball)(3)
AA1
(3)
AG4
THERMAL1 (thermal ball)
SPARE1
(1)
AE11
SPARE4
(1)
U5
SPARE5(2)
SPARE6
(1)
AF25
V4
I/O Power
AG21,AG14, AG8, AJ1, AJ2, AH1, AH2,AG3,
AF4, AE5, AC27, Y27, T27, P27, K26, G27,
AE25, AF26, AG27, AH28, AH29, AJ28, AJ29,
C7,C14,C16,C20,C23, E10, A28, A29, B28,
B29, C27, D26, E25, H3, M4, T3, AA4, A1, A2,
B1, B2, C3, D4, E5
Core Power
U28, U29, K28, K29, A9, A19, B19, M1, M2, Y1,
Y2, AC1, AC2, AH19, AJ19, AH10, AJ10, AJ5
Ground
AA5, AF21, AF14, AF8, AE7, AF11,
AE17, AE23, AC26, AB25, Y26, V25,
T26, R25, P26, M25, K27, H25,
G26, D7, D10, D14, D16, D20, D23,
C9, E11, E13, E15, E19, E22, B3,
G5, H4, K5, M3, P5, T4, Y5, AA2,
AC3
Notes:
18
1. Must be pulled down or left floating.
2. Must be pulled down or left floating. However, if compatibility with HiP4 silicon is required, this pin must be pulled up or left
floating.
3. For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide available at
www.motorola.com/semiconductors.
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Symbols used in Table 2 are described in Table 4.
Table 3. Symbol Legend
OVERBAR
Signals with overlines, such as TA, are active low
UTM
Indicates that a signal is part of the UTOPIA master interface
UTS
Indicates that a signal is part of the UTOPIA slave interface
2UT8
Indicates that a signal is part of the 8-bit UTOPIA interface
UT16
Indicates that a signal is part of the 16-bit UTOPIA interface
MII
Indicates that a signal is part of the media independent interface
19
2131B–HIREL–02/03
Figure 2. PowerQUICC II External Signals
VCCSYN/GNDSYN/VCCSYN1/VDDH/VDD/VSS
P AR / L_A14
SMI/FRAME / L_A15
TRDY / L_A16
CKSTOP_OUT/IRDY / L_A17
STOP/ L_A18
DEVSEL / L_A19
IDSEL / L_A20
PERR / L_A21
SERR / L_A22
REQ0 / L_A23
REQ1 / L_A24
GNT0 / L_A25
GNT1 / L_A26
CLK / L_A27
CORE_SRESET/RST / L_A28
INTA/ L_A29
LOCK/ L_A30
L_A31
AD[0:31]/LCL_D[0:31]
C/BE[0:3] /LCL_DP[0:3]
LBS[0:3]/LSDDQM [0:3]/LWE [0:3]
LGPL0/LSDA10
LGPL1/LSDWE
LGPL2/LSDRAS/LOE
LGPL3/LSDCAS
LPBS/LGPL4/LUPWAIT/LGTA
LGPL5
LWR
PA[0:31]
PB[4:31]
PC[0:31]
PD[4:31]
PORESET
RSTCONF
HRESET
SRESET
QREQ
XFC
CLKIN
TRIS
BNKSEL[0]/TC[0]/AP[1]/MODCK1
BNKSEL[1]/TC[1]/AP[2]/MODCK2
BNKSEL[2]/TC[2]/AP[3]/MODCK3
TERM[0:1]
NC
20
100
1
1
1
1
1
1 L
1
O
1
C
A
1
L
1
1
1 B
1
U
1
1 S
1
1
1
32
4
4
1
1
M
1
E
1
M
1
C
1
1
32
P
28
32 I
28 O
1
1
1
1 R
1
S
1 T
1
1
1
1
1
2
4
C
L
K
32
5
4
1
1
1
1
1
1
1
1
6 1
0 1
1
x 1
1
B 1
1
U 1
S 64
1
1
1
1
1
1
1
1
1
1
1
1
1
10
1
1
2
1
M 1
E 8
M 1
C 1
1
1
1
1
1
J 1
T 1
A 1
G1
A[0:31]
TT[0:4]
TSIZ[0:3]
TBST
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
BR
BG
ABB/IRQ2
TS
AACK
ARTRY
DBG
DBB/IRQ3
D[0:63]
NC/DP0/RSRV/EXT_BR2
IRQ1/DP1/EXT_BG2
IRQ2/DP2/TLBISYNC/EXT_DBG2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
IRQ4/DP4/CORE_SRESET /EXT_BG
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
PS_DVAL
TA
TEA
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
CS[0:9]
CS[10]/BCTL1/DBG_DIS
CS[11]/AP[0]
BADDR[27:28]
ALE
BCTL0
PWE[0:7]/PSDDQM[0:7]/PBS[0:7]
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
TMS
TDI
TCK
TRST
TDO
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Signal Descriptions
The PowerQUICC II system bus signals consist of all the lines that interface with the external bus. Many of these lines perform different functions, depending on how the user assigns them. Each signal’s pin number can be found in Table 4.
Table 4. External Signals
Pin
Signal Name
BR
60x Bus Request
I/O
This is an output when an external arbiter is used and an input when an
internal arbiter is used. As an output, the PowerQUICC II asserts this pin
to request ownership of the 60x bus. As an input, an external master
should assert this pin to request 60x bus ownership from the internal
arbiter.
BG
60x BusGrant
I/O
This is an output when an internal arbiter is used and an input when an
internal arbiter is used. As an output, the PowerQUICC II asserts this pin
to grant 60x bus ownership to an external bus master. As an input, an
external arbiter should assert this pin to grant 60x bus ownership to the
PowerQUICC II.
ABB
IRQ2
60x Address Bus Busy
I/O
As an output the PowerQUICC II asserts this pin for the duration of the
address bus tenure. Following an AACK, which terminates the address
bus tenure, the PowerQUICC II negates ABB for a fraction of a bus cycle
and than stops driving this pin. As an input, the PowerQUICC II will not
assume 60x bus ownership, as long as it senses this pin is asserted by
an external 60x bus master.
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
Interrupt Request 2
Type
Description
TS
T-S 60x Bus Transfer Start
I/O
Assertion of this pin signals the beginning of a new address bus tenure.
The PowerQUICC II asserts this signal when one of its internal 60x bus
masters (core, dma, PCI bridge) begins an address tenure. When the
PowerQUICC II senses this pin being asserted by an external 60x bus
master, it will respond to the address bus tenure as required (snoop if
enabled, access internal PowerQUICC II resources and memory
controller support).
A[0:31]
60x Address Bus
I/O
When the PowerQUICC II is in the external master bus mode, these pins
function as the 60x address bus. The PowerQUICC II drives the address
of its internal 60x bus masters and will respond to addresses generated
by external 60x bus masters. When the PowerQUICC II is in the internal
master bus mode, these pins are used as address lines connected to
memory devices and controlled by the PowerQUICC II’s memory
controller.
TT[0:4]
60x Bus Transfer Type
I/O
The 60x bus master drives these pins during the address tenure to
specify the type of the transaction.
TBST
60x Bus Transfer Burst
I/O
The 60x bus master asserts this pin to indicate that the current
transaction is a burst transaction (transfers 4 double words).
TSIZ[0:3]
60x Transfer Size
I/O
The 60x bus master drives these pins with a value indicating the amount
of bytes transferred in the current transaction.
AACK
60x Address Acknowledge
I/O
A 60x bus slave asserts this signal to indicate that it has identified the
address tenure. Assertion of this signal terminates the address tenure.
ARTRY
60x Address Retry
I/O
Assertion of this signal indicates that the bus transaction should be
retried by the 60x bus master. The PowerQUICC II asserts this signal to
enforce data coherency with its internal cache and to prevent deadlock
situations.
21
2131B–HIREL–02/03
Table 4. External Signals (Continued)
Pin
Signal Name
Type
Description
DBG
60x Data Bus Grant
I/O
This is an output when an internal arbiter is used and an input when an
external arbiter is used. As an output, the PowerQUICC II asserts this
pin to grant 60x data bus ownership to an external bus master. As an
input, the external arbiter should assert this pin to grant 60x data bus
ownership to the PowerQUICC II.
DBB
IRQ3
60x Data Bus Busy
I/O
As an output the PowerQUICC II asserts this pin for the duration of the
data bus tenure. Following a TA, which terminates the data bus tenure,
the PowerQUICC II negates DBB for a fraction of a bus cycle and then
stops driving this pin. As an input, the PowerQUICC II will not assume
60x data bus ownership, as long as it senses this pin is asserted by an
external 60x bus master.
Interrupt Request 3
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
D[0:63]
60x Data Bus
I/O
In write transactions, the 60x bus master drives the valid data on this
bus. In read transactions, the 60x slave drives the valid data on this bus.
DP[0]
RSRV
EXT BR2
60x Data Parity 0
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 0 pin should provide odd
parity (odd number of 1’s) on the group of signals that include data parity
0 and D[0:7].
Reservation
O
The value driven on this output pin represents the state of the coherency
bit in the reservation address register that is used by the Iwarx and
stwcx. instructions.
External Bus Request 2
I
An external master should assert this pin to request 60xbus ownership
from the internal arbiter.
Interrupt Request 1
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
IRQ1
DP[1]
EXT BG2
IRQ2
DP[2]
TLBISYNC
EXT DBG2
22
60x Data Parity 1
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 1 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 1 and D[8:15].
External Bus Grant 2
O
The PowerQUICC II asserts this pin to grant 60x bus ownership to an
external bus master.
Interrupt Request 2
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
60x Data Parity 2
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 2 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 2 and S[16:23].
TLB Sync:
I
This input pin can be used to synchronize 60x core instruction execution
to hardware indications. Asserting this pin will force the core to stop
instruction execution following a tlbsinc instruction execution. The core
resumes instruction execution once this pin is negated.
External Data Bus Grant 2
O
The PowerQUICC II asserts this pin to grant 60x data bus ownership to
an external bus master.
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 4. External Signals (Continued)
Pin
Signal Name
IRQ3
DP[3]
CKSTP OUT
EXT BR3
Interrupt Request 3
IRQ4
DP[4]
CORE SRESET
EXT BG3
IRQ5
DP[5]
TBEN
EXT DBG3
IRQ6
DP[6]
CSE[0]
IRQ7
DP[7]
CSE[1]
Type
I
Description
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
60x Data Parity 3
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 3 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 3 and D[24:31].
Checkstop Output
O
Assertion of this pin indicates that the core is in its checkstop mode.
External Bus Request 3
I
An external master should assert this pin to request 60x bus ownership
from the internal arbiter.
Interrupt Request 4
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
60x Data Parity 4
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 4 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 4 and D[32:39].
Core system reset
I
Asserting this pin will force the core to branch to its reset vector.
External Bus Grant 3
O
The PowerQUICC II asserts this pin to grant 60x data bus ownership to
an external bus master.
Interrupt Request 5
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
60x Data Parity 5
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 5 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 5 and D[40:47].
Time Base Enable
I
This is a count enable input to the Time Base counter in the core.
External Bus Grant3
O
The PowerQUICC II asserts this pin to grant 60x data bus ownership to
an external bus master.
Interrupt Request 6
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
60x Data Parity 6
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 6 pin should provide odd
parity (odd number of 1’s) on the group of signals that include data parity
6 and D[48:55].
Cache Set Entry 0
O
The cache set entry outputs from the core, represent the cache
replacement set element for the current core transaction reloading into,
or writing out of, the cache.
Interrupt Request 7
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
60x Data Parity 7
I/O
The 60x master or slave that drives the data bus, also drives the data
parity signals. The value driven on the data parity 7pin should provide
odd parity (odd number of 1’s) on the group of signals that include data
parity 7 and D[56:63].
Cache Set Entry 1
O
The cache set entry outputs from the core, represent the cache
replacement set element for the current core transaction reloading into,
or writing out of, the cache.
23
2131B–HIREL–02/03
Table 4. External Signals (Continued)
Pin
Signal Name
Type
PSDVAL
60x Data Valid
I/O
Assertion of the PSDVAL pin indicates that a data beat is valid on the
data bus. The difference between the TA pin and the PSDVAL pin is that
the TA pin is asserted to indicate 60x data transfer terminations, while
the PSDVAL signal is asserted with each data beat movement. Thus,
always when TA is asserted, PSDVAL will be asserted, but, when
PSDVAL is asserted, TA is not necessarily asserted. For example, when
a double-double word (2x64 bits) transfer is initiated by the SDMA to a
memory device that has 32 bits port size, PSDVAL will be asserted 3
times without TA and, finally, both pins will be asserted to terminate the
transfer.
TA
Transfer Acknowledge
I/O
Assertion of theTA pin indicates that a 60x data beat is valid on the data
bus. For 60x single beat transfers, assertion of this pin indicates the
termination of the transfer. For 60x burst transfers, this pin will be
asserted four times to indicate the transfer of four data beats, with the
last assertion indicating the termination of the burst transfer.
TEA
Transfer Error
Acknowledge
I/O
Assertion of this pin indicates a bus error. 60x masters within the
PowerQUICC II monitor the state of this pin. PowerQUICC II’s internal
bus monitor may assert this pin if it has identified a 60x transfer that is
hung.
GBL
IRQ1
Global
I/O
When a 60x master within the chip initiates a bus transaction it drives
this pin. When an external 60x master initiates a bus transaction, it
should drive this pin. Assertion of this pin indicates that the transfer is
global and it should be snooped by caches in the system. The
PowerQUICC II data cache monitors the state of this pin.
CI
BADDR29
IRQ2
WT
BADDR30
IRQ3
24
Description
Interrupt Request 1
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
Cache Inhibit
O
This pin is an output pin. It is used for L2 cache control. For each
BADDR29 PowerQUICC II 60x transaction initiated in the core, the state
of this pin indicates if this transaction should be cached or not. Assertion
of the CI pin indicates that the transaction should not be cached.
Burst Address 29
O
There are five burst address output pins. These pins are outputs of the
60x memory controller. These pins are used in external master
configuration and are connected directly to memory devices controlled
by PowerQUICC II memory controller.
Interrupt Request 2
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
Write Through
O
Output used for L2 cache control. For each core initiated PowerQUICC II
60x transaction, the state of this pin indicates if the transaction should be
cached using write-through or copy-back mode. Assertion of WT
indicates that the transaction should be cached using the write-through
mode.
Burst Address 30
O
There are five burst address output pins. These pins are outputs of the
60x memory controller. These pins are used in external master
configuration and are connected directly to memory devices controlled
by PowerQUICC II’s memory controller.
Interrupt Request 3
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 4. External Signals (Continued)
Pin
Signal Name
Type
L2 HIT
IRQ4
L2 Cache Hit
I
This pin is used for L2 cache control. Assertion of this pin indicates that
the 60x transaction will be handled by the L2 cache. In this case, the
memory controller will not start an access to the memory it controls.
Interrupt Request 4
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
CPU BusGrant
O
The value of the60x core bus grant is driven on this pin for the
BADDR31 use of an external L2 cache. The driven bus grant is non
qualified. that is, in the IRQ5 case of external arbiter, the user should
qualify this signal with the bus grant input to the PowerQUICC II before
connecting it to the L2 Cache.
Burst address 31
O
There are five burst address outputs of the 60x memory controller used
in the external master configuration and are connected directly to the
memory devices controlled by PowerQUICC II’s memory controller.
Interrupt Request 5
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
CPU DBG
CPU Bus Data Bus Grant
O
The value of the 60x core data bus grant is driven on this pin for the use
of an external L2 cache.
CPU BR
CPU Bus Request
O
The value of the 60x core bus request is driven on this pin for the use of
an external L2 cache.
CS[0:9]
Chip Select
O
These are output pins that enable specific memory devices or
peripherals connected to PowerQUICC II buses.
CS[10]
BCTL1
DBG DIS
Chip Select
O
This is an output pin that enables specific memory devices or
peripherals connected to PowerQUICC II buses.
Buffer Control 1
O
Output signal whose function is to control buffers on the 60x data bus.
This pin will usually be used with BCTL0. The exact function of this pin is
defined by the value of SIUMCR[BCTLC]. See 6.5.1.8 SIU Module
Configuration Register for details.
Data Bus Grant Disable
O
This is an output when the PowerQUICC II is in external arbiter mode
and an input when the PowerQUICC II is in internal arbiter mode. When
this pin is asserted, the 60x bus arbiter should negate all of its DBG
outputs to prevent data bus contention.
Chip Select
O
Output that enables specific memory devices or peripherals connected
to PowerQUICC II buses.
Address Parity 0
I/O
The 60x master that drives the address bus, also drives the address
parity signals. The value driven on address parity 0 pin should provide
odd parity (odd number of 1’s) on the group of signals that includes
address parity 0 and A[0: 7].
BADDR[27:28]
Burst Address 27:28
O
There are five burst address output pins. These pins are outputs of the
60x memory controller. Used in external master configuration and
connected directly to the memory devices controlled by PowerQUICC
II’s memory controller.
ALE
Address Latch Enable
O
This output pin controls the external address latch that should be used in
external master 60x bus configuration.
BCTLO
Buffer Control 0
CPU BG
BADDR31
IRQ5
CS[11]
AP[0]
Description
An Output whose function is to control buffers on the 60x data bus. This
pin will usually be used with BCTL1 that is MUXed on CS10. The exact
function of this pin is defined by the value of SIUMCR[BCTLC]. See
6.5.1.8 SIU Module Configuration Register for details.
25
2131B–HIREL–02/03
Table 4. External Signals (Continued)
Pin
Signal Name
PWE[0:7]
PSDDQM[0:7]
PBS[0:7]
60x Bus Write Enable
O
Outputs of the 60x bus GPCM, these pins select byte lanes for
PSDDQM[0-7] write operations.
60x Bus SDRAM DQM
O
The DQM pins are outputs of the SDRAM control machine. These pins
select specific byte lanes of SRAM devices.
60x Bus UPM Byte Select
O
The byte select pins are outputs of the UPM in the memory controller.
They are used to select specific byte lanes during memory operations.
The timing of these pins is programmed in the UPM. The actual driven
value depends on the address and size of the transaction and the port
size of the accessed device.
60x Bus SDRAM A10
O
An output from the 60x bus SDRAM controller, this pin is part of the
address when a row address is driven and is part of the command when
a column address is driven.
60x Bus UPM General
Purpose Line 0
O
This is one of six general purpose output lines from UPM. The values
and timing of this pin are programmed in the UPM;
60x Bus SDRAM Write
Enable
O
An output from the 60x bus SDRAM controller. This pin should be
connected to SRAM’s WE input.
60x Bus UPM General
Purpose Line 1
O
This is one of six general purpose output lines from UPM. The values
and timing of this pin are programmed in the UPM.
60x Bus Output Enable
O
The output enable pin is an output of the 60x bus GPCM. This pin
controls the output buffer of memory devices during read operations.
60x Bus SDRAM RAS
O
Output from the 60x bus SDRAM controller. This pin should be
connected to SDRAM’s RAS input.
60xBus UPM General
Purpose Line 2.
O
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
60x bus SDRAM CAS
O
Output from the 60x bus SDRAM controller. This pin should be
connected to SDRAM’s CAS input.
60x Bus UPM General
Purpose line 3
O
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
60x GPCM TA
I
This input pin is used for transaction termination during GPCM
operation. This pin requires external pull up resistor for proper operation.
60x Bus UPM Wait
I
This is an input to the UPM. An external device may hold this pin low to
force the UPM to wait until the device is ready for the continuation of the
operation.
60x Bus UPM General
Purpose Line 4
O
This is one of six general purpose output lines from UPM. The values
and timing of this pin are programmed in the UPM.
60 x Bus Parity Byte Select
O
In systems in which data parity is stored in a separate chip, this output is
used as the byte select for that chip.
60x SDRAM Address
Multiplexer
O
This output pin controls the 60x SDRAM address multiplexer when the
PowerQUICC II is in external master mode.
60x Bus General Purpose
Line 5
O
This is one of six general purpose output lines from UPM. The values
and timing of this pin are programmed in the UPM.
PSDA10
PGPLO
PSDWE
PGPL1
POE
PSDRAS
PGPL2
PSDCAS
PGPL3
PGTA
PUPMWAIT
PGPL4
PPBS
PSDAMUX
PGPL5
26
Type
Description
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 4. External Signals (Continued)
Pin
Signal Name
LWE[0:3]
LSDDQM[0:3]
LBS[0:3]
Local Bus Write Enable
O
The write enable pins are outputs of the Local bus GPCM. These pins
select specific byte lanes for write operations.
Local Bus SDRAM DQM
O
The DQM pins are outputs of the SDRAM control machine. These pins
select specific byte lanes of SDRAM devices.
Local Bus UPM byte select
O
The byte select pins are outputs of the UPM in the memory controller.
They are used to select specific byte lanes during memory operations.
The timing of these pins is programmed in the UPM. The actual driven
value depends on the address and size of the transaction and the port
size of the accessed device.
Local Bus SDRAM A10
O
Output from the 60x bus SDRAM controller. This pin is part of the
address when a row address is driven and is part of the command when
a column address is driven.
Local Bus UPM General
Purpose Line 0
O
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
Local Bus SDRAM Write
Enable
O
Output from the local bus SDRAM controller. This pin should be
connected to SDRAM’s WE input.
Local Bus UPM General
Purpose Line 1
O
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
Local Bus Output Enable
O
The output enable pin is an output of the Local bus GPCM. This pin
controls the output buffer of memory devices during read operations.
Local Bus SDRAM RAS
O
Output from the Local bus SDRAM controller. This pin should be
connected to the SDRAM RAS input.
Local bus UPM General
Purpose Line 2
O
This is one of six general purpose output lines from UPM. The values
and timing of this pin are programmed in the UPM.
Local Bus SDRAM CAS
O
Output from the Local bus SDRAM controller. This pin should be
connected to SDRAM’s CAS input.
Local Bus UPM General
Purpose Line 3
O
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
Local Bus GPCM TA
I
This input pin is used for transaction termination during GPCM
operation. This pin requires an external pull up resistor for proper
operation.
Local Bus UPM Wait
I
This is an input to the UPM. An external device may hold this pin low to
force the UPM to wait until the device is ready for the continuation of the
operation.
Local Bus UPM General
Purpose Line 4
O
This is one of six general purpose output lines from UPM. The values
and timing of this pin is programmed in the UPM.
Local Bus Parity Byte
Select
O
In systems in which the data parity is stored in a separate chip, this
output is used as the byte select for that chip.
LGPL5
Local Bus UPM General
Purpose Line 5
O
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
LWR
Local Write
O
The local write pin is an output from the local bus memory controller. It is
used to distinguish between read and write transactions.
LSDA10
LGPL0
LSDWE
LGPL1
LOE
LSDRAS
LGPL2
LSDCAS
LGPL3
LGTA
LUPWAIT
LGPL4
LPBS
Type
Description
27
2131B–HIREL–02/03
Table 4. External Signals (Continued)
Pin
Signal Name
L_A14
PCI_PAR
Local Bus Address 14
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI Parity
I/O
Assertion of this pin indicates that odd parity is driven across
PCI_AD[0:31] and PCI_C/BE[0-3] during address and data phases.
Negation of this pin indicates that even parity is driven across the
PCI_AD[0-31] and PCI_C/BE[0-3] signals during address and data
phases.
Local Bus Address 15
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI Frame i
I/O
This pin is driven by the PowerQUICC II when its interface is the initiator
of a PCI transfer. This pin is asserted to indicate that a PCI transfer is on
going.
L_A15
PCI_FRAME
SMI
L-A16
PCI_TRDY
L_A17
PCI_IRDY
CKSTP_OUT
L_A18
PCI_STOP
L_A19
PCI_DEVESEL
L_A20
PCI_IDSEL
L_A21
PCI_PERR
28
Type
Description
System Management
Interrupt
I
System management interrupt input to the core.
Local Bus Address 16
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI Target Ready
I/O
This pin is driven by the PowerQUICC II when its PCI interface is the
target of a PCI transfer. Assertion of this pin indicates that the PCI target
is ready to send or accept a data beat.
Local Bus Address 17
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI Initiator Ready
I/O
This pin is driven by the PowerQUICC II when its PCI interface is the
initiator of a PC] transfer. Assertion of this pin indicates that the PCI
initiator is ready to send or accept a data beat.
Checkstop Output
O
Assertion of CKSTP_OUT indicates the core is in checkstop mode.
Local Bus Address 18
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI Stop
I/O
This pin is driven by the PowerQUICC II when its PCI interface is the
target of a PCI transfer. Assertion of this pin indicates that the PCI target
is requesting to stop the PCI transfer.
Local Bus Address 19
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI Device Select
I/O
This pin is driven by the PowerQUICC II when its PCI interface is the
target of a PCI transfer. Assertion of this pin indicates that a PCI target
has recognized a new PCI transfer with an address that belongs to the
PCI target.
Local Bus Address 20
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI ID select
I
Used to select PowerQUICC II’s PCI interface during a PCI configuration
cycle.
Local Bus Address 21
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI Parity Error
I/O
Assertion of this pin indicates that a parity error was detected during a
PCI transfer.
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 4. External Signals (Continued)
Pin
Signal Name
L_A22
PCI_SERR
Local Bus Address 22
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI System Error
I/O
Assertion of this pin indicates that a PCI system error was detected
during a PCI transfer.
Local Bus Address 23
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI Arbiter Request 0
I/O
When PowerQUICC II’s internal PCI arbiter is used, this is an input pin.
In this mode assertion of this pin indicates that an external PCI agent is
requesting the PCI bus. When an external PCI arbiter is used, this is an
output pin. In this mode assertion of this pin indicates that PowerQUICC
II’s PCI interface is requesting the PCI bus.
Local Bus Address 24
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI Arbiter Request 1
I
When PowerQUICC II’s internal PCI arbiter is used, assertion of this pin
indicates that an external PCI agent is requesting the PCI bus.
Local Bus Address 25
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI Arbiter Grant 0
I/O
When PowerQUICC II’s internal PCI arbiter is used, this is an output pin.
In this mode, assertion of this pin indicates that an external PCI agent
that requested the PCI bus with the REQ0 pin is granted the bus. When
an external PCI arbiter is used, this is an input pin. In this mode,
assertion of this pin indicates that PowerQUICC II’s PCI interface is
granted the PCI bus.
Local Bus Address 26
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI Arbiter Grant 1
O
When PowerQUICC II’s internal PCI arbiter is used, assertion of this pin
indicates that the external PCI agent that requested the PCI bus with the
REQ1 pin is granted the bus.
Local Bus Address 27
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
Clock Output pin
O
In a PCI system where PC8260’s PCI interface is configured to operate
from an external PCI clock, the 60x bus clock is driven on CLKOUT. In a
PCI system where the PC8260’s PCI interface is configured to generate
the PCI clock, the PCI clock is driven on CLKOUT. The PCI clock
frequency range is 25-66MHz.
Local Bus Address 28
O
In the local address bus bit 14 is most significant and bit 31 is least
significant.
PCI Reset
I/O
When the PC8260 is the host in the PCI system, PCI_RST is an output.
When the PC8260is not the host of the PCI system, PCI_RST is an
input.
L_A23
PCI_REQ0
L_A24
PCI_REQ1
L_A25
PCI_GNT0
L_A26
PCI_GNT1
L_A27
CLKOUT
L_A28
PCI_RST
CORE_SRESET
Core System Reset
Type
I
Description
This an input to the core. When this input pin is asserted the core
branches to its reset vector.
29
2131B–HIREL–02/03
Table 4. External Signals (Continued)
Pin
Signal Name
L_A29
PCI_INTA
Local Bus Address 29
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI INTA
I/O
When the PowerQUICC II is the host in the PCI system, this pin is an
input for delivering PCI interrupts to the host. When the PowerQUICC II
is not the host of the PCI system, this pin is an output used by the
PowerQUICC II to signal an interrupt to the PCI host.
L_A30
Local Bus Address 30
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
L_A31
DLLSYNC
Local Bus Address 31
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
DLL Synchronization
I
DLLSYNC is used to eliminate skew for the clock driven on CLKOUT.
LCL_D[0:31]
PCI_AD[0:31]
LCL_DP[0:3]
PCI_C/BE[0:3]
IRQ0
NMI_OUT
Type
Description
Local Bus Data
I/O
In the local data bus, bit 0 is most significant and bit 31 is least
significant.
PCI Address Data
I/O
PCI bus address data input/output pins. In the PCI address data bus, bit
31 is most significant and bit 0 is least significant.
Local Bus Data Parity
I/O
In local bus write operations the PowerQUICC II drives these pins. In
local bus read operations the accessed device drives these pins.
LCL_DP(0) is driven with a value that gives odd parity with LCL_D(0:7).
LCL-DP(1) is driven with a value that gives odd parity with LCL_D(8:15).
LCL_DP(2) is driven with a value that gives odd parity with
LCL_D(16:23).
LCL_DP(3) is driven with a value that gives odd parity with
LCL_D(24:31)
PCP Command/Byte
Enable
I/O
The PowerQUICC II drives these pins when it is the initiator of a PCI
transfer.
Interrupt request 0
I
This input is one of the eight external lines that can request (by means of
the NMI-OUT internal interrupt controller) a service routine from the
core.
Non Maskable Interrupt
Output
O
This is an output driven from PowerQUICC II’s internal interrupt
controller. Assertion of this output indicates that an unmasked interrupt
is pending in PowerQUICC II’s internal interrupt controller.
Interrupt Request 7
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
Interrupt Output
O
This is an output driven from PowerQUICC II’s internal interrupt
controller. Assertion of this output indicates that an unmasked interrupt
is pending in PowerQUICC II’s internal interrupt controller.
Address Parity Error
O
This output pin will be asserted when the PowerQUICC II’s detects
wrong parity driven on its address parity pins by an external master
TRST
Test Reset (JTAG)
I
This is the reset input to PowerQUICC II’s JTAG/COP controller.
TCK
Test Clock (JTAG)
I
This pin provides the clock input for PowerQUICC II’s JTAG/COP
controller.
TMS
Test Mode Select (JTAG)
I
This pin controls the state of PowerQUICC II’s JTAG/COP controller.
TDI
Test Data In (JTAG)
I
This pin is the data input to PowerQUICC II’s JTAG/COP controller.
TDO
Test Data Out (JTAG)
O
This pin is the data output from PowerQUICC II’s JTAG/COP controller.
IRQ7
INT_OUT
APE
30
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 4. External Signals (Continued)
Pin
Signal Name
TRIS
Three State
I
Asserting TRIS forces all other PowerQUICC II’s pins to high impedance
state.
PORESET
Power-on Reset
I
When asserted, this input line causes the PowerQUICC II to enter
power-on reset state.
HRESET
Hard Reset
I/O
This open drain line, when asserted, causes the PowerQUICC II to enter
hard reset state.
SRESET
Soft Reset
I/O
This open drain line, when asserted, causes the PowerQUICC II to enter
soft reset state.
QREQ
Quiescent Request
O
This pin indicates that PowerQUICC II’s internal core is about to enter its
low power mode. In the PowerQUICC II, this pin will be typically used for
debug purposes.
RSTCONF
Reset Configuration
I
This input lien is sampled by the PowerQUICC II during the assertion of
the HRESET signal. If the line is asserted, the configuration mode is
sampled in the form of the hard reset configuration word driven on the
data bus. When this line is negated, the default configuration mode is
adopted by the PowerQUICC II. Notice that the initial base address of
internal registers is determined in this sequence.
MODCK1
AP[1]
TC[0]
BNKSEL[0]
Clock Mode Input
I
Defines the operating mode of internal clock circuits.
Address Parity 1
I/O
The 60x master that drives the address bus, also drives the address
parity signals. The value driven on the address parity 1 pin should
provide odd parity (odd number of 1’s) on the group of signals that
includes address parity 1 and [A8:15].
Transfer Code 0
O
The transfer code output pins supply information that can be useful for
debug purposes for each of the PowerQUICC II initiated bus
transactions.
Bank Select 0
O
The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x compatible bus mode.
Clock Mode Input
I
Defines the operating mode of internal clock circuits.
Address Parity 2
I/O
The 60x master that drives the address bus, also drives the address
parity signals. The value driven on the address parity 2 pin should
provide odd parity (odd number of 1’s) on the group of signals that
includes address parity 2 and [A16:23].
Transfer Code 1
O
The transfer code output pins supply information that can be useful for
debug purposes for each of the PowerQUICC II initiated bus
transactions.
Bank Select 1
O
The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x compatible bus mode.
MODCK2
AP[2]
TC[1]
BNKSEL[1]
Type
Description
31
2131B–HIREL–02/03
Table 4. External Signals (Continued)
Pin
Signal Name
MODCK3
AP[3]
TC[2]
BNKSEL[2]
Clock Mode Input
I
Address Parity 3
I/O
The 60x master that drives the address bus, also drives the address
parity signals. The value driven on the address parity 3 pin should
provide odd parity (odd number of 1’s) on the group of signals that
includes address parity 3and [A24:314].
Transfer Code 2
O
The transfer code output pins supply information that can be useful for
debug purposes for each of the PowerQUICC II initiated bus
transactions.
Bank Select 2
O
The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x compatible bus mode.
XFC
External Filter Capacitance
I
Input connection for an external capacitor filter for PLL circuity.
CLKIN
Clock In
I
Primary clock input to PowerQUICC II’s PLL.
PA[0:31]
Port A Bits 0:31
I/O
General Purpose I/O Port
PB[4:31]
Port B Bits 4:31
I/O
General Purpose I/O Port
PC[0:31]
Port C Bits 0:31
I/O
General Purpose I/O Port
PD[4:31]
Port D Bits 4:31
I/O
General Purpose I/O Port
VDD
VDDH
VCCSYN
GNDSYN
VCCSYN1
Power Supply
Power Supply
Power Supply
Special Ground
Power Supply
32
Type
Description
Defines the operating mode of internal clock circuits.
Power supply of the internal logic
Power supply of the I/O buffers
Power supply of the PLL circuity
Special ground of the PLL circuity
Power supply of the core’s PLL circuity
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Applicable Documents
1. MIL-STD-883: Test methods and procedures for electronics.
2. SQ32S0100.0: Quality levels for supplied components.
Requirements
General
The microcircuits are in accordance with the applicable documents and as specified
herein.
Terminal Connections
The terminal connections are shown in Table 2 on page 8.
Absolute Maximum Ratings
Table 5. Maximum Ratings
Symbol
Rating
Value
Unit
VDD
Core Supply Voltage
-0.3/2.75
V
VCCSYN
PLL Supply Voltage
-0.3/2.75
V
VDDH
I/O Supply Voltage
-0.3/3.6
V
VIN
Input Voltage
(GND-0.3)/3.6
V
TSTG
Storage Temperature Range
-65/+150
°C
Note:
Warning
Absolute maximum ratings are stress ratings only. Functional operation (see Table on
page 34) at the maximums is not guaranteed. Stress beyond those listed may affect
device reliability or cause permanent damage.
VIN must not exceed VDDH by more than 2.5V at any time, including during power-on
reset. VDDH must not exceed VDD/VCCSYN by more than 1.6V at any time, including during
power-on reset. V DD/V CCSYN must not exceed VDDH by more than 0.4V at any time,
including during power-on reset. It is recommended to use a bootstrap diode between
the power rails, as shown in Figure 3.
Figure 3. Bootstrap Diodes for Power-up Sequencing
3.3V (VDDH)
I/O Power
MUR420
MUR420
Core/Pll
Power
2.5V(VDD/VCCSYN)
Select the bootstrap diodes so that a nominal VDD/VCCSYN is sourced from the VDDH
power supply until the V DD /V CCSYN power supply becomes active. In Figure 3, two
MUR420 Schottky barrier diodes are connected in a series; each has a forward voltage
(VF) of 0.6V at high currents, and so provides a 1.2V drop, maintaining 2.1V on the 2.5V
power line. Once the core/PLL power supply stabilizes at 2.5V, the bootstrap diode(s)
will be reverse biased with negligible leakage current.
33
2131B–HIREL–02/03
The forward voltage should be effective at the current levels needed by the processor,
approximately 2-3 amps. That is, do not use diodes with only a nominal VF which drops
too low at high current.
Recommended Operating
Conditions
Table 6. Recommended Operational Voltage Conditions
Symbol
Rating
2.5V Device
Unit
VDD
Core Supply Voltage
2.4 / 2.7
V
VCCSYN
PLL Supply Voltage
2.4 / 2.7
V
VDDH
I/O Supply Voltage
3.15 / 3.465
V
VIN
Input Voltage
GND -0.3 / 3.6
V
TJ
Junction Temperature
-55 / + 125
°C
Note:
The recommended and tested operating conditions. Proper device operation outside of
these conditions is not guaranteed.
This device contains circuitry to protect against damage due to high static voltage or
electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Operational reliability is enhanced if unused inputs are tied to an appropriate
logic voltage level (either GND or VCC).
Table 7. Thermal Characteristics
Symbol
Value
Unit
Air Flow
(1)
°C/W
NC(2)
ΘJA
11.0(1)
°C/W
1 m/s
ΘJA
10.8(3)
°C/W
NC
°C/W
1 m/s
ΘJA
Characteristics
Thermal Resistance for TBGA
ΘJA
Notes:
34
13.5
8.5
(3)
1. Assumes a single layer board with no thermal bias
2. Natural convection
3. Assumes a four layer board
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Power Considerations
The average chip-junction temperature, TJ, in °C can be obtained from the following:
T J = T A + ( P D • Θ JA )
(1)
where
TA = ambient temperature °C
QJA = package thermal resistance, junction to ambient, °C/W
PD = PINT + PI/O
PINT =IDD x VDD Watts–chip internal power
PI/O = power dissipation on input and output pins–user determined
P I ⁄ O < 0,3 • P INT
Can be neglected for most applications. If PI/O is neglected, an approximate relationship
between PD and TJ is the following:
PD = K / (TJ + 273 °C)
(2)
Solving equations (1) and (2) for K gives:
K = P D • ( T A + 273°C ) + Θ • P D 2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P D (at equilibrium) for a known TA. Using this value of K, the
values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any
value of TA.
Layout Practices
Each V CC pin on the PC8260 should be provided with a low-impedance path to the
board’s power supply. Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The
V CC power supply should be bypassed to ground using at least four 0.1 µF by-pass
capacitors located as close as possible to the four sides of the package. The capacitor
leads and associated printed circuit traces connecting to chip VCC and ground should be
kept to less than half an inch per capacitor lead. A four-layer board is recommended,
employing two inner layers as VCC and GND planes.
All output pins on the PC8260 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly
applies to the address and data busses. Maximum PC trace lengths of six inches are
recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these
loads create higher transient currents in the VCC and GND circuits. Pull up all unused
inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
35
2131B–HIREL–02/03
Electrical Characteristics
DC Electrical Specification
This section describes the DC electrical characteristics for the PC8260. The measurements in Table 8 assume the following system conditions:
TC = -55°C to +125°C
VDD = 2.0 ± 5% VDC
VDDH = 3.3 ± 5% VDC
GND = 0 VDC
The leakage current is measured for nominal VDDH and VDD, or both. VDDH and VDD must
vary in the same direction (for example, both VDDH and VDD vary by either +5% or -5%).
Table 8. DC Electrical Characteristics
36
Symbol
Characteristic
Min
Max
Unit
VIH
Input High Voltage, All Inputs Except CLKIN
2.0
3.465
V
VIL
Input Low Voltage
GND
0.8
V
VIHC
CLKIN Input High Voltage
2.4
3.465
V
VILC
CLKIN Input Low Voltage
GND
0.4
V
IIN
Input Leakage Current, VIN= VDDH
10
µA
IOZ
Hi-Z (off state) Leakage Current, VIN = VDDH
10
µA
IL
Signal Low Input Current, VIL= 0.8V
TBD
TBD
µA
IH
Signal High Input Current, VIH = 2.0V
TBD
TBD
µA
VOH
Output High Voltage, IOH = -2 mA
Except XFC, and Open Drain Pins
2.4
V
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 8. DC Electrical Characteristics (Continued)
Symbol
Characteristic
VOL
IOL = 7.0 mA
Min
Max
Unit
0.4
V
BR
BG
ABB/IRQ2
TS
A[0:31]
TT[0:4]
TBST
TSIZE[0:3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0:63]
DP(0)/RSRV
DP(1)/IRQ1
DP(2)/TLBISYNC/IRQ2
DP(3)/IRQ3
DP(4)/IRQ4
DP(5)/TBEN/IRQ5
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
PORESET
SRESET
RSTCONF
QREQ
37
2131B–HIREL–02/03
Table 8. DC Electrical Characteristics (Continued)
Symbol
Characteristic
VOL
IOL = 5.3 mA
Min
Max
Unit
0.4
V
CS[0:9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE(0:7)/PSDDQM(0:7)/PBS(0:7)
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM(0:3)/LBS([0–3]
LSDA10/LGPL0
LSDWE/LGPL1
LOE/LSDRAS/LGPL2
LSDCAS/LGPL3
LGTA/LUPMWAIT/LGPL4/LPBS
LGPL5
LWR
MODCK1/AP(1)/TC(0)/BNKSEL(0)
MODCK2/AP(2)/TC(1)/BNKSEL(1)
MODCK3/AP(3)/TC(2)/BNKSEL(2)
IOL = 3.2 mA
L_A14
L_A15/SMI
L_A16
L_A17/CKSTP_OUT
L_A18
L_A19
L_A20
L_A21
L_A22
L_A23
L_A24
L_A25
L_A26
L_A27
L_A28/CORE_SRESET
38
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 8. DC Electrical Characteristics (Continued)
Symbol
Characteristic
VOL
L_A29
L_A30
L_A31
LCL_D(0:31)
LCL_DP(0:3)
PA[0:31]
PB[4:31]
PC[0:31]
PD[4:31]
TDO
Min
Max
Unit
0.4
V
39
2131B–HIREL–02/03
AC Electrical Specifications
Included in this section are illustrations and tables of clock diagrams, signals, and CPM
outputs and inputs. Note that AC timings are based on a 50 pF load. Typical output
buffer impedances are shown in Table 9.
Table 9. Output Buffer Impedances
Output Buffers
Typical Impedance (Ω)
60x bus
40
Local bus
40
Memory Controller
40
Parallel I/O
46
PCI
25
Note:
These are typical values at 65°C. The impedance may vary by ± 25% with process and
temperature.
Although the specifications generally refer to the rising edge of the clock, the following
AC timing diagrams also apply when the falling edge is the active edge.
Figure 4. FCC External Clock Diagram
Serial CLKin
sp17b
FCC Input Signals
sp16b
sp36b/sp37b
FCC Output Signals
Figure 5. FCC Internal Clock Diagram
sp17a
BRG_OUT
FCC Input Signals
sp16a
sp36a/sp37a
FCC Output Signals
40
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Figure 6. SCC/SMCSPI/I2C External Clock
Serial CLKin
sp19b
sp18
SCC/SMCSPI/I2C Input Signals
sp38b/sp39b
SCC/SMCSPI/I2C Output Signals
Figure 7. SCC/SMC/SPI/I2C Internal Clock Diagram
BRG_OUT
sp18a
sp19a
SCC/SMC/SPI/I2C Input Signals
sp38a/sp39a
SCC/SMC/SPI/I2C Output Signals
Figure 8. PIO, Timer and DMA Signal Diagram
CLKin
sp23
PIO/TIMER/DMA Input Signals
sp22
sp42/sp43
PIO/TIMER/DMA Output Signals
sp42
PIO Output Signals
41
2131B–HIREL–02/03
Figure 9. TDM Signal Diagram
Serial CLKin
sp20
sp21
TDM Input Signals
sp40/sp41
TDM Output Signals
Table 10. AC Characteristics for CPM Outputs
Spec_num
Characteristics
Max Delay (ns)
Min Delay (ns)
sp36a/sp37a
FCC Outputs – Internal clock
(NMSI)
6
0
sp36b/sp37b
FCC Outputs – External clock
(NMSI)
18
2
sp40/sp41
TDM Outputs
35
5
sp38a/sp39a
SCC/SMC/SPI/I2C Outputs –
Internal Clock (NMSI)
20
0
sp38b/sp39b
EX_SCC/SMC/SPI/I2C Outputs –
External Clock (NMSI)
30
0
sp42/sp43
PIO/TIMER/DMA Outputs
14
1
Note:
Output specifications are measured from the 1.4V level of the rising edge of CLKIN to the
TTL level (0.8 or 2.0V) of the signal. Timing is measured at the pin.
Table 11. AC Characteristics for CPM Inputs
Spec_num
Characteristics
Setup (ns)
Hold (ns)
sp16a/sp17a
FCC Inputs – Internal clock (NMSI)
10
0
sp16b/sp17b
FCC Inputs – External clock (NMSI)
5
3
sp20/sp21
TDM Inputs
20
20
sp18a/sp19a
ISCC/SMC/SPI/I2C Inputs –
Internal Clock (NMSI)
20
0
sp18b/sp19b
SCC/SMC/SPI/I2C Inputs –
External Clock (NMSI)
5
5
sp22/sp23
PIO/TIMER/DMA Outputs
10
3
Note:
42
Input specifications are measured from the TTL level (0.8 or 2.0V) of the signal to the 1.4
level of the rising edge of CLKIN. Timing is measured at the pin.
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Figure 10. Interaction of Bus Signals
CLKin
AACK/ARTRY/TA/TEA/DBG/BG/BR Input Signals
sp11
sp10
sp12
sp10
sp15
sp10
Data Bus Name Input Signal
All Other Input Signals
sp31/sp30
PSDVAL/TEA/TA Output Signals
sp32/sp30
ADD/ADD_atr/BADDR/CI/GBL/WT Output Signals
sp33a/sp30
DATA Bus Output Signals
sp35/sp30
All Other Output Signals
Figure 11. ECC Mode Diagram
sp10
sp10
sp13
DATA Bus, ECC, and PARITY Mode Input Signals
sp10
sp14
DP Mode Input Signal
DP Mode Output Signal
sp33b/sp30
43
2131B–HIREL–02/03
Figure 12. MEMC Mode Diagram
CLKin
V_CLK
sp34/sp30
Memory Controller Signals
Table 12. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
PLL Clock Radio
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6
1/4 CLKin
1/2 CLKin
3/4 CLKin
1:2.5
3/10 CLKin
1/2 CLKin
8/10 CLKin
1:3.5
4/14 CLKin
1/2 CLKin
11/14 CLKin
Note:
Generally, all PC8260 bus and system output signals are driven from the rising edge of
the input clock (CLKin). Memory controller signals, however, trigger on four points within
a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always
occurs at the rising edge of CLKin (and T3 at the falling edge), but the spacing of T2 and
T4 depends on the PLL clock ratio selected, as shown in Table 12.
Figure 13. Internal Tick Spacing for Memory Controller Signals
CLKin
for 1:2, 1:3, 1:4, 1:5, 1:6
T1
T2
T3
T4
CLKin
for 1:2.5
T1
T2
T3
T4
for 1:3.5
CLKin
T1
Note:
44
T2
T3
T4
The UPM machine and GPCM machine outputs change on the internal tick determined
by the memory controller programming. The AC specifications are relative to the internal
tick. Note that SDRAM machine outputs change only on the CLKin’s rising edge.
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 13. AC Characteristics for SIU Inputs
Spec_num
Characteristics
Setup (ns)
Hold (ns)
sp11/sp10
AACK/ARTRY/TA/TEA/DBG/BG/BR
6
1
sp12/sp10
Data Bus in Normal mode
5
1
sp13sp10
Data Bus in ECC and PARITY Modes
8
1
sp14/sp10
DP pins
8
1
sp15/sp10
All Other Pins
5
1
Notes:
1. Input specifications are measured from TTL level (0.8 or 2.0V) of the signal to the 1.4
level of the rising edge of CLKIN.
2. Timings are measured at the pins.
Table 14. AC Characteristics for SIU Outputs
Spec_num
Characteristics
Max Delay (ns)
Min Delay (ns)
sp31/sp30
PSDVAL/TEA/TA
10
1
sp32/sp30
ADD/ADD_atr./BADDR/CIGBL/WT
8
1
sp33a/sp30
Data Bus
8
1
sp33b/sp30
DP
12
1
sp34/sp10
Memc Signals/ALE
6
1
sp35/sp10
All Other Signals
7
1
Notes:
1. Output specifications are measured from the 1.4V level of the rising edge of CLKIN to
the TTL level (0.8 or 2.0V) of the signal.
2. Timings are measured at the pin.
Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC
timing. When data pipelining is activated, sp12 can be used for data bus setup even
when ECC or PARITY are used. Also, sp33a can be used as the AC specification for DP
signals.
45
2131B–HIREL–02/03
Clock Configuration Modes
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the MODCK[1:3] pins are
sampled while HRESET is asserted. Table 15 shows the eight basic configuration modes. Another 49 modes are available
by using the configuration pin (RSTCONF) and driving four pins on the data bus.
Table 15. Clock Default Modes
MODCK[1–3]
Input Clock
Frequency
(MH)z
CPM Multiplication
Factor
CPM
Frequency
(MHz)
Core Multiplication
Factor
Core
Frequency
(MHz)
000
33
3
100
4
133
001
33
3
100
5
166
010
33
4
133
4
133
011
33
4
133
5
166
100
66
2
133
2.5
166
101
66
2
133
3
200
110
66
2.5
166
2.5
166
111
66
2.5
166
3
200
Table 16. Clock Configuration Modes
MODCK_H–
MODCK[1–3]
Input Clock
Frequency
(MHz)
CPM Multiplication
Factor
CPM
Frequency
(MHz)
Core Multiplication Factor
Core
Frequency
(MHz)
0001_000
33
2
66
4
133
0001_001
33
2
66
5
166
0001_010
33
2
66
6
200
0001_011
33
2
66
7
233
0001_100
33
2
66
8
266
0001_101
33
3
100
4
133
0001_110
33
3
100
5
166
0001_111
33
3
100
6
200
0010_000
33
3
100
7
233
0010_001
33
3
100
8
266
0010_010
33
4
133
4
133
0010_011
33
4
133
5
166
0010_100
33
4
133
6
200
0010_101
33
4
133
7
233
0010_110
33
4
133
8
266
46
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Table 16. Clock Configuration Modes (Continued)
MODCK_H–
MODCK[1–3]
Input Clock
Frequency
(MHz)
CPM Multiplication
Factor
CPM
Frequency
(MHz)
Core Multiplication Factor
Core
Frequency
(MHz)
0010_111
33
5
166
4
133
0011_000
33
5
166
5
166
0011_001
33
5
166
6
200
0011_010
33
5
166
7
233
0011_011
33
5
166
8
266
0011_100
33
6
200
4
133
0011_101
33
6
200
5
166
0011_110
33
6
200
6
200
0011_111
33
6
200
7
233
0100_000
33
6
200
8
266 MHz
0100_001
Reserved
0100_010
0100_011
0100_100
0100_101
0100_110
0100_111
Reserved
0101_000
0101_001
0101_010
0101_011
0101_100
0101_101
66
2
133
2
133
0101_110
66
2
133
2.5
166
0101_111
66
2
133
3
200
0110_000
66
2
133
3.5
233
0110_001
66
2
133
4
266
0110_010
66
2
133
4.5
300
0110_011
66
2.5
166
2
133
0110_100
66
2.5
166
2.5
166
47
2131B–HIREL–02/03
Table 16. Clock Configuration Modes (Continued)
MODCK_H–
MODCK[1–3]
Input Clock
Frequency
(MHz)
CPM Multiplication
Factor
CPM
Frequency
(MHz)
Core Multiplication Factor
Core
Frequency
(MHz)
0110_101
66
2.5
166
3
200
0110_110
66
2.5
166
3.5
233
0110_111
66
2.5
166
4
266
0111_000
66
2.5
166
4.5
300
0111_001
66
3
200
2
133
0111_010
66
3
200
2.5
166
0110_101
66
2.5
166
3
200
0110_110
66
2.5
166
3.5
233
0110_111
66
2.5
166
4
266
0111_000
66
2.5
166
4.5
300
0111_001
66
3
200
2
133
0111_010
66
3
200
2.5
166
0111_011
66
3
200
3
200
0111_100
66
3
200
3.5
233
0111_101
66
3
200
4
266
0111_110
66
3
200
4.5
300
0111_111
66
3.5
233
2
133
1000_000
66
3.5
233
2.5
166
1000_001
66
3.5
233
3
200
1000_010
66
3.5
233
3.5
233
1000_011
66
3.5
233
4
266
1000_100
66
3.5
233
4.5
300
Notes:
48
1. This table describes all possible clock configurations when using the hard reset configuration sequence. Note that clock
configuration changes only after POR is asserted.
2. Because of speed dependencies, not all of the possible configurations in this table may be applicable.
3. The 66 MHz configurations are required for input clock frequencies higher than 50 MHz. 33 MHz configurations are required
for input clock frequencies below 50 MHz.
4. The user should choose the input clock frequency, and the multiplication factor of the CPM so that the frequency of the CPM
will be between 50 MHz and 166 MHz for a 2V part, and between 66 MHz and 233 MHz for a 2.5V part.
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Status
Table 17. Datasheet Status
Datasheet Status
Validity
Objective Specification
This datasheet contains target and goal specification for
discussion with customer and application validation.
Valid before design phase
Target Specification
This datasheet contains target or goal specifications for
product development.
Valid during the design phase
Preliminary Specification ∝ Site
This datasheet contains preliminary data. Additional data
may be published later. This could include simulation
results.
Valid before the characterization
phase
Preliminary Specification β Site
This datasheet also contains characterization results.
Valid before the industrialization
phase.
Product Specification
This datasheet contains final product specifications.
Valid for production purposes
Limiting Values
Limiting values given are in accordance with the Absolute Maximum Rating System
(IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device
reliability.
Application Information
Where application information is given, it is advisory and does not form part of the
specification.
Life Support Applications
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. ATMEL-Grenoble customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel-Grenoble for any
damages resulting from such improper use or sale.
49
2131B–HIREL–02/03
Package Dimensions TBGA480
±F±
B
CORNER
±E±
±T ±
0.150 T
MIN
A1
INDEX
A
4X
MAX
A
37.5 BSC
B
37.5 BSC
C
1.45
1.65
D
0.65
0.85
G
1.27 BSC
H
0.85
K
35.56 BSC
L
0.50
0.95
0.70
0.2
Top View
28 26 24 22 20 18 16 14 12 10 8 6 4 2
29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
A
C
E
G
J
L
N
R
U
W
B
D
F
H
K
M
P
K
T
V
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
Bottom View
480X ϕ D
C
G
K
H
L
All measurements are in mm.
Notes:
1. Dimensions and tolerancing per asme Y14.5M-1994.
2. Dimensions in millimeters.
3. Dimension b is measured at the maximum solder ball diameter. Parallel to primary datum A.
4. Primary datum A and the seating plane are defined by the spherical crowns of the solder balls.
50
PC8260 PowerQUICC II
2131B–HIREL–02/03
PC8260 PowerQUICC II
Ordering Information
Revision A1
PC (X)
Prefix
8260
M
TP
U
200
(A1 )
Revision Level
(1)
Prototype
Type
Temperature Range: Tj
M:
V:
-55, +125 ˚C
-40, +110 ˚C
Max. Internal Processor Speed
(2)
200/200 MHz
150/150 MHz
Package
TP: TBGA
Screening Level
(2)
U: Upscreening
(1) Atmel-Grenoble
(2) For availability of the different versions, contact your sales office.
51
2131B–HIREL–02/03
Revision B1 and Above
PC (X)
Prefix
8260
M TP
U
IFB
B1
Revision Level
(1)
Prototype
Core Voltage
Type
= 2.5 V + 0.2, -0.1 Volt
V = 1.8 V ± 0.1 Volt
Temperature Range: Tj
M:
V:
-55, +125 °C
-40, +110 °C
CPU/CPM/Bus Speed (MHz)
A = 50, B = 66, C= 75
D = 83, E = 100, F = 133
G = 150, H = 166, I = 200
J = 233, K = 266, L = 300
M = 333
Package:
TP: TBGA
Screening Level
(2)
U: Upscreening
(1) Atmel-Grenoble
(2) For availability of the different versions, contact your sales office.
52
PC8260 PowerQUICC II
2131B–HIREL–02/03
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
© Atmel Corporation 2003.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL ® is the registered trademark of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
2131B–HIREL–02/03
0M