Philips Semiconductors Product specification N-channel enhancement mode TrenchMOSTM transistor GENERAL DESCRIPTION N-channel enhancement mode standard level field-effect power transistor in a surface mounting plastic envelope using ’trench’ technology. The device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in switched mode power supplies and general purpose switching applications. PINNING - SOT404 (D2PAK) PIN IRFZ44NS QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot Tj RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 10 V PIN CONFIGURATION MAX. UNIT 55 49 110 175 22 V A W ˚C mΩ SYMBOL DESCRIPTION d mb 1 gate 2 drain 3 source mb drain g 2 1 s 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C - - 55 55 55 20 49 35 160 110 175 V V V A A A W ˚C MIN. MAX. UNIT - 2 kV TYP. MAX. UNIT - 1.4 K/W 50 - K/W ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Electrostatic discharge capacitor voltage, all pins Human body model (100 pF, 1.5 kΩ) THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient - Rth j-a February 1999 Minimum footprint, FR4 board 1 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOSTM transistor IRFZ44NS STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage VGS = 0 V; ID = 0.25 mA; VGS(TO) Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; VGS = ±10 V; VDS = 0 V IGSS Gate source leakage current ±V(BR)GSS RDS(ON) Gate source breakdown voltage IG = ±1 mA; Drain-source on-state VGS = 10 V; ID = 25 A resistance Tj = 175˚C Tj = 175˚C Tj = 175˚C MIN. TYP. MAX. UNIT 55 50 2.0 1.0 16 - 3.0 0.05 0.04 15 - 4.0 4.4 10 500 1 20 22 42 V V V V µA µA µA µA V mΩ mΩ MIN. TYP. MAX. UNIT DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 25 V; ID = 25 A 6 - - S Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1350 330 155 1800 400 215 pF pF pF Qg Qgs Qgd Total gate charge Gate-cource charge Gate-drain (miller) charge VDD = 44 V; ID = 50 A; VGS = 10 V - - 62 15 26 nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 25 A; VGS = 10 V; RG = 10 Ω Resistive load - 18 50 40 30 26 75 50 40 ns ns ns ns Ld Internal drain inductance - 2.5 - nH Ls Internal source inductance Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT - - 49 A IF = 25 A; VGS = 0 V IF = 40 A; VGS = 0 V - 0.95 1.0 160 1.2 - A V IF = 40 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V - 47 0.15 - ns µC REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IDR IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge February 1999 CONDITIONS 2 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOSTM transistor IRFZ44NS AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS WDSS Drain-source non-repetitive unclamped inductive turn-off energy ID = 45 A; VDD ≤ 25 V; VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C 120 Normalised Power Derating PD% MIN. TYP. MAX. UNIT - - 110 mJ 1000 110 ID/A 100 90 tp = RDS(ON) =VDS/ID 80 1 us 100 10us 70 60 100 us 50 DC 40 10 1 ms 30 20 10ms 100ms 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 180 1 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 10 100 VDS/V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Current Derating ID% 1 10 Zth/(K/W) 110 100 1 90 0.5 80 0.2 70 60 0.1 50 0.1 0.05 PD 0.02 40 30 0.01 tp D= t T 0 tp T 20 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 0.001 180 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V February 1999 1E-06 0.0001 0.01 t/s 1 100 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 3 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOSTM transistor 100 16 IRFZ44NS 30 9 VGS/V = ID/A 8.0 8.5 10 gfs/S 25 80 7.5 20 60 7.0 15 6.5 40 10 6.0 20 0 0 2 4 VDS/V 6 8 5.5 5 5.0 4.5 10 4.0 0 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS 40 20 40 ID/A 60 80 100 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V RDS(ON)/mOhm VGS/V = 35 0 2.5 BUK959-60 a Rds(on) normlised to 25degC 6 2 30 6.5 7 1.5 25 8 9 20 10 1 15 10 0 10 20 30 40 ID/A 50 60 70 80 0.5 -100 90 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS -50 0 50 Tmb / degC 100 150 200 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 10 V 100 5 VGS(TO) / V BUK759-60 ID/A max. 80 4 typ. 60 3 40 2 min. 1 20 Tj/C = 0 0 2 175 4 25 6 VGS/V 8 10 0 -100 12 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj February 1999 -50 0 50 Tj / C 100 150 200 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 4 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOSTM transistor IRFZ44NS 100 Sub-Threshold Conduction 1E-01 IF/A 80 1E-02 2% 1E-03 typ 60 98% Tj/C = 175 25 40 1E-04 20 1E-05 0 1E-06 0 1 2 3 4 0 0.2 0.4 0.6 0.8 VSDS/V 5 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 1 1.2 1.4 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 2.5 120 WDSS% 110 100 2 Thousands pF 90 80 1.5 70 Ciss 60 50 1 40 30 20 .5 0 0.01 0.1 1 VDS/V 10 Coss 10 Crss 0 20 40 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 60 80 100 120 Tmb / C 140 160 180 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 49 A 12 VGS/V VDD + 10 L VDS = 14V 8 VDS VDS = 44V - VGS 6 -ID/100 0 4 RGS 2 0 T.U.T. 0 10 20 QG/nC 30 40 50 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 50 A; parameter VDS February 1999 R 01 shunt 5 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOSTM transistor + IRFZ44NS VDD RD VDS - VGS RG 0 T.U.T. Fig.17. Switching test circuit. February 1999 6 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOSTM transistor IRFZ44NS MECHANICAL DATA Plastic single-ended package (Philips version of D2-PAK); 2 leads SOT404 A A1 E D1 D HD Lp c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D D1 E mm 4.5 4.1 1.40 1.27 0.85 0.60 0.64 0.46 9.65 8.65 1.6 1.2 10.3 9.7 OUTLINE VERSION e Lp HD Q 2.54 2.9 2.1 15.4 14.8 2.60 2.20 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-16 SOT404 Fig.18. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". February 1999 7 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode TrenchMOSTM transistor IRFZ44NS MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.19. SOT404 : soldering pattern for surface mounting. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. February 1999 8 Rev 1.000