PHILIPS TDA1305T

INTEGRATED CIRCUITS
DATA SHEET
TDA1305T
Stereo 1fs data input up-sampling
filter with bitstream continuous dual
DAC (BCC-DAC2)
Preliminary specification
Supersedes data of September 1994
File under Integrated Circuits, IC01
1995 Dec 08
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
TDA1305T
FEATURES
• Easy application
• 16fs Finite-duration Impulse-Response (FIR)
filter incorporated
• Selectable system clock (fsys) 256fs or 384fs
• I2S-bus serial input format (at fsys = 256fs) or LSB fixed
16, 18 or 20 bits serial input mode (at fsys = 384fs)
• Slave-mode clock system
bitstream converter for low signals while large signals are
generated using the dynamic continuous calibration
technique, thus resulting in low power consumption, small
chip size and easy application.
• Cascaded 4-stage digital filter incorporating 2-stage FIR
filter, linear interpolator and sample-and-hold
• Smoothed transitions before and after muting
(soft mute)
The TDA1305T is a dual CMOS DAC with up-sampling
filter and noise shaper. The combination of high
oversampling up to 16fs, 2nd order noise shaping and
continuous calibration conversion ensures that only simple
1st order analog post filtering is required.
• Digital de-emphasis filter for three sampling rates of
32 kHz, 44.1 kHz and 48 kHz
• 12 dB attenuation via the attenuation input control
• Double speed mode
• 2nd order noise shaper
The TDA1305T supports the I2S-bus data input mode with
word lengths of up to 20 bits (at fsys = 256fs) and the LSB
fixed serial data input format with word lengths of 16, 18
and 20 bits (at fsys = 384fs). Four cascaded FIR filters
increase the oversampling rate to 16 times. A
sample-and-hold function increases the oversampling rate
to 96 times (fsys = 384fs) or 128 times (fsys = 256fs). A
2nd order noise shaper converts this oversampled data to
a bitstream for the 5-bit DACs.
• 96 (fsys = 384fs) or 128 (fsys = 256fs) times oversampling
in normal speed mode
• 48 (fsys = 384fs) or 64 (fsys = 256fs) times oversampling
in double speed mode
• Bitstream continuous calibration concept
• Small outline SO28 package
• Voltage output 1.5 V (RMS) at line drive level
• Low total harmonic distortion
The DACs are of the continuous calibration type and
incorporate a special date coding. This ensures an
extremely high signal-to-noise ratio, superior dynamic
range and immunity to process variation and component
ageing.
• No zero crossing distortion
• Inherently monotonic
• No analog post filtering required
• Superior signal-to-noise ratio
Two on-board operational amplifiers convert the
digital-to-analog current to an output voltage. Externally
connected capacitors perform the required 1st order
filtering so that no further post filtering is required.
• Wide dynamic range (18-bit)
• Single rail supply (3.4 to 5.5 V).
The unique combination of bitstream and continuous
calibration techniques, together with a high degree of
analog and digital integration, results in a single filter-DAC
with 18-bit dynamic range, high linearity and simple low
cost application.
GENERAL DESCRIPTION
The TDA1305T is a new generation of filter-DAC which
features a unique combination of bitstream and continuous
calibration techniques. The converter functions as a
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TDA1305T
1995 Dec 08
NAME
DESCRIPTION
VERSION
SO28
plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
2
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
TDA1305T
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
note 1
3.4
5.0
5.5
V
VDDA
analog supply voltage
note 1
3.4
5.0
5.5
V
VDDO
operational amplifier
supply voltage
note 1
3.4
5.0
5.5
V
IDDD
digital supply current
VDDD = 5 V;
at code 00000H
−
30
−
mA
IDDA
analog supply current
VDDA = 5 V;
at code 00000H
−
5.5
8
mA
IDDO
operating amplifier supply VDDO = 5 V;
current
at code 00000H
−
6.5
9
mA
VFS(rms)
full-scale output voltage
(RMS value)
VDDD = VDDA = VDDO = 5 V
1.425
1.5
1.575
V
(THD + N)/S
total harmonic distortion
plus noise-to-signal ratio
at 0 dB signal level
−
−90
−81
dB
−
0.003
0.009
%
at −60 dB signal level
−
−44
−40
dB
−
0.63
0.1
%
at −60 dB signal level;
A-weighted
−
−46
−
dB
−
0.5
−
%
A-weighting;
at code 00000H
100
108
−
dB
S/N
signal-to-noise ratio at
bipolar zero
BRns
input bit rate at data input fs = 48 kHz; normal speed
−
−
3.072
Mbits
BRds
input bit rate at data input fs = 48 kHz; double speed
−
−
6.144
Mbits
fsys
system clock frequency
6.4
−
18.432
MHz
TCFS
full scale temperature
coefficient at analog
outputs (VOL and VOR)
−
±100 ×
Tamb
operating ambient
temperature
−30
−
Note
1. All VDD and VSS pins must be connected to the same supply.
1995 Dec 08
3
10−6
−
+85
°C
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
BLOCK DIAGRAM
Fig.1 Block diagram.
1995 Dec 08
4
TDA1305T
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
TDA1305T
PINNING
SYMBOL
PIN
DESCRIPTION
VDDA
1
analog supply voltage
VSSA
2
analog ground
TEST1
3
test input; pin should be connected
to ground (internal pull-down
resistor)
BCK
4
bit clock input
WS
5
word select input
DATA
6
data input
CLKS1
7
clock selection 1 input
CLKS2
8
clock selection 2 input
VSSD
9
digital ground
VDDD
10
digital supply voltage
TEST2
11
test input; pin should be connected
to ground (internal pull-down
resistor)
SYSCLKI
12
system clock input
n.c.
13
not connected (this pin should be left
open-circuit)
n.c.
14
not connected (this pin should be left
open-circuit)
VSSD
15
digital ground
SYSCLKO
16
system clock output
DEEM1
17
de-emphasis on/off; fDEEM 32 kHz,
44 kHz and 48 kHz
DEEM2
18
de-emphasis on/off; fDEEM 32 kHz,
44 kHz and 48 kHz
MUSB
19
mute input (active LOW)
DSMB
20
double-speed mode input
(active LOW)
ATSB
21
12 dB attenuation input
(active LOW)
VOL
22
left channel output
FILTCL
23
capacitor for left channel 1st order
filter function should be connected
between pins 22 and 23
FILTCR
24
capacitor for right channel 1st order
filter function should be connected
between pins 25 and 24
VOR
25
right channel output
Vref
26
internal reference voltage for output
channels (0.5VDD)
VSSO
27
operational amplifier ground
VDDO
28
operational amplifier supply voltage
1995 Dec 08
Fig.2 Pin configuration.
5
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
provide a system clock of 256 or 384fs (fs = 32, 44.1 or
48 kHz). The system frequency is selectable by means of
pin CLKS1 and pin CLKS2. The SYSCLKO output (pin 16)
provides the system clock for external use.
FUNCTIONAL DESCRIPTION
The TDA1305T CMOS digital-to-analog bitstream
converter incorporates an up-sampling filter and noise
shaper which increase the oversampling rate of 1fs input
data to 96fs (fsys = 192fs) or 128fs (fsys = 256fs) in the
normal speed mode. In the double speed mode the
oversample rate of 1fs input data is increased to 48fs
(fsys = 384fs) or 64fs (fsys = 256fs). This oversampling,
together with the 5-bit DAC, enables the filtering required
for waveform smoothing and out-of-band noise reduction
to be achieved by simple 1st order analog post filtering.
The TDA1305T supports the following data input modes:
• I2S-bus with data word lengths of up to 20 bits
(at fsys = 256fs).
• LSB fixed serial format with data word lengths of 16, 18
and 20 bits (at fsys = 384fs). As this format idles on the
MSB it is necessary to know how many bits are being
transmitted.
System clock and data input format
The input format is shown in Fig.3. Left and right
data-channel words are time-multiplexed.
The TDA1305T accommodates slave mode only, this
means that in all applications the system devices must
Table 1
TDA1305T
Data input format and system clock.
SYSTEM
CLOCK
DATA
CLOCK(1)
I2S up to 20 bits
256fs
>20
256fs
1
LSB fixed 16 bits
384fs
24
384fs
1
0
LSB fixed 18 bits
384fs
24
384fs
0
1
1
LSB fixed 20 bits
384fs
24
384fs
1
0
0
reserved
−
−
−
1
0
1
LSB fixed 16 bits
384fs
32
384fs
1
1
0
LSB fixed 18 bits
384fs
32
384fs
1
1
1
LSB fixed 20 bits
384fs
32
384fs
TEST1
CLKS1
CLKS2
0
0
0
0
0
0
DATA INPUT FORMAT
Note
1. Number of clock pulses within half an audio sample.
1995 Dec 08
6
SYSCLKO
Philips Semiconductors
7
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
1995 Dec 08
Preliminary specification
TDA1305T
Fig.3 Input formats.
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
TDA1305T
Mute
Oversampling filter (normal-speed mode)
Soft mute is controlled by the MUSB at pin 9. When the
input is active LOW the value of the samples is decreased
smoothly to zero following a cosine curve. To step down
the value of the data 32 coefficients are used, each one
being used 31 times before stepping onto the next. When
MUTE is released (pin 19 = HIGH), the samples are
returned to the full level again following a cosine curve with
the same coefficients being used in the reverse order.
Mute is synchronized to prevent operation in the middle of
a word.
In the normal-speed mode the oversampling filter
consists of:
• A 91st order half-band low-pass FIR filter which
increases the oversampling rate from 1 time to 2 times.
• A 23rd order quarter band low-pass FIR filter which
increases the oversampling rate from 2 times to 8 times.
• A linear interpolation section which increases the
oversampling rate to 16 times. This removes the
spectral components around 8fs.
• A sample-and-hold section which provides another
6 times oversampling to 96 times. The zero-order hold
characteristic of this sample-and-hold section plus the
1st order analog filtering remove the spectral
components around 16fs.
De-emphasis
A digital de-emphasis is implemented for three sample
rates (32, 44.1 and 48 kHz). By selecting DEEM1 and
DEEM2 de-emphasis can be applied by means of a FIR
filter. Time constants of the de-emphasis are 50 µs and
15 µs. De-emphasis is synchronized to prevent operation
in the middle of a word. The de-emphasis deviation from
ideal 50 µs and 15 µs de-emphasis is given in Table 4.
Table 2
Pass-band ripple and stop-band attenuation for
normal-speed are given in Table 3.
Oversampling filter (double-speed mode)
In the double-speed mode the oversampling filter
consists of:
De-emphasis.
DEEM1
DEEM2
CONDITION
0
0
de-emphasis disabled
0
1
de-emphasis for fs = 32 kHz
1
0
de-emphasis for fs = 4.1 kHz
1
1
de-emphasis for fs = 48 kHz
• A 51st order half-band low-pass FIR filter which
increases the oversampling rate from 1 time to 2 times.
• A 7th order half-band low-pass FIR filter which
increases the oversampling rate from 2 times to 4 times.
• A linear interpolation section which increases the
oversampling rate to 8 times. This removes the spectral
components around 4fs.
Attenuation
• A sample-and-hold section which provides another
6 times oversampling to 48 times. The zero-order hold
characteristic of this sample-and-hold section plus the
1st order analog filtering remove the spectral
components around 8fs.
Attenuation is controlled by the ATSB input (pin 21). When
the input is active LOW the sample is multiplied by a
coefficient that provides 12 dB attenuation. If the input is
HIGH the multiplication factor is 1. Attenuation is
synchronized to prevent operation in the middle of a word.
Pass-band ripple and stop-band attenuation for
double-speed are given in Table 3.
Double-speed mode
Double speed is controlled by the DSMB input (pin 20).
When the input is active LOW the device operates in the
double-speed mode.
1995 Dec 08
8
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
TDA1305T
(input 00000H). Using this technique extremely high
signal-to-noise performance is achieved.
Noise shaper
In the normal speed mode the 2nd order digital noise
shaper operates at 96fs (fsys = 384fs) or 128fs
(fsys = 256fs). The digital noise shaper operates at 48fs
(fsys = 384fs) or 64fs (fsys = 256fs) in double-speed mode. It
shifts in-band quantization noise to frequencies well above
the audio band. This noise shaping technique used in
combination with a special data coding enables extremely
high signal-to-noise ratios to be achieved. The noise
shaper outputs a 5-bit pulse duration modulation (PDM)
bitstream signal to the DAC.
Operational amplifiers
High precision, low-noise amplifiers together with the
internal conversion resistors RCONV1 and RCONV2 convert
the converter output current to a voltage capable of driving
a line output. This voltage is available at VOL and VOR
(1.5 V RMS typical).
Connecting external capacitors CEXT1 and CEXT2
between FILTCL and VOL and between FILTCR and VOR
respectively provides the required 1st order post filtering
for the left and right channels (see Fig.1). The
combinations of RCONV1 with CEXT1 and RCONV2 with
CEXT2 determine the 1st order fall-off frequencies.
Continuous calibration DAC
The dual 5-bit DAC uses the continuous calibration
technique. This method, based on charge storage,
involves exact duplication of a single reference current
source. In the TDA1305T, 32 such current sources plus
1 spare source are continuously calibrated. The spare
source is included to allow continuous converter operation.
Internal reference circuitry
Internal reference circuitry ensures that the output voltage
signal is proportional to the supply voltage, thereby
maintaining maximum dynamic range for supply voltages
from 3.4 to 5.5 V and making the circuit also suitable for
battery-powered applications.
The DAC receives a 5-bit data bitstream from the noise
shaper. This data is then converted so that only small
currents are switched to the output during digital silence
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDD
digital supply voltage
−
7.0
V
VDDA
analog supply voltage
−
7.0
V
VDDO
operational amplifier supply voltage
−
7.0
V
Txtal
maximum crystal temperature
−
+150
°C
Tstg
storage temperature
−65
+150
°C
Tamb
ambient operating temperature
−30
+85
°C
Ves
electrostatic handling
note 1
−2000
+2000
V
note 2
−200
+200
V
Notes
1. Human body model; C = 100 pF, R = 1500 Ω, V = 2000 V, 3 pulses positive and 3 pulses negative.
2. Machine model; C = 200 pF, R = 10 Ω, L = 0.5 µH.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1995 Dec 08
PARAMETER
thermal resistance from junction to ambient in free air
9
VALUE
UNIT
75
K/W
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
TDA1305T
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611E”. The number of this quality specification can be found in the “Quality Reference
Handbook”. The handbook can be ordered using the code 9398 510 63011.
DIGITAL CHARACTERISTICS
VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDD
digital supply voltage
note 1
3.4
5.0
5.5
V
IDDD
digital supply current
VDDD = 5 V;
at code 00000H
−
30
40
mA
VDDA
analog supply voltage
note 1
3.4
5.0
5.5
V
IDDA
analog supply current
VDDA = 5 V;
at code 00000H
−
5.5
8
mA
VDDO
operational amplifier supply
voltage
note 1
3.4
5.0
5.5
V
IDDO
operational amplifier supply
current
VDDO = 5 V;
at code 00000H
−
6.5
9
mA
RR
ripple rejection to VDDA
note 2
−
25
−
dB
System clock input
fsys
VIL
system frequency
LOW level input voltage
fsys = 384fs
9.6
16.93
18.4
MHz
fsys = 256fs
6.4
11.29
12.28
MHz
note 3
−0.5
−
0.2VDD
V
VIH
HIGH level input voltage
note 3
0.8VDD
−
VDD + 0.5
V
ILI
input leakage current
note 4
−
−
10
µA
Ci
input capacitance
−
−
10
pF
Tcy
clock cycle time
fsys = 384fs
104
59.1
54.2
ns
fsys = 256fs
156
88.6
81.3
ns
Digital inputs; WS, BCK, DATA, DSMB, MUSB, DEEM1, DEEM2, ATSB, CLKS1, CLKS2, TEST1 and TEST2
VIL
LOW level input voltage
−0.5
note 3
−
0.3VDD
V
VIH
HIGH level input voltage
note 3
0.7VDD
−
VDD + 0.5
V
ILI
input leakage current
note 4
−
−
10
µA
Ci
input capacitance
−
−
10
pF
Digital output; CDEC
VOL
LOW level output voltage
IOL = 0.4 mA
0
−
0.5
V
VOH
HIGH level output voltage
IOH = −0.2 mA
VDD − 0.5
−
VDD
V
tr
output rise time
note 5
−
−
20
ns
tf
output fall time
note 5
−
−
20
ns
CL
load capacitance
−
−
30
pF
1995 Dec 08
10
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
SYMBOL
PARAMETER
TDA1305T
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Serial input data timing (see Fig.4)
bit-clock input (data input
rate) frequency
fsys = 384fs
−
48fs
−
MHz
fsys = 256fs
−
64fs
−
MHz
fWS
word select input frequency
normal speed
25
44.1
48
kHz
50
88.2
96
kHz
tr
rise time
−
−
20
ns
tf
fall time
−
−
20
ns
tH
bit clock time HIGH
55
−
−
ns
tL
bit clock time LOW
55
−
−
ns
tsu
data set-up time
40
−
−
ns
th
data hold time
10
−
−
ns
tsuWS
word select set-up time
40
−
−
ns
thWS
word select hold time
10
−
−
ns
fBCK
double speed
Notes
1. All VDD and VSS pins must be connected externally to the same supply.
2. Vripple = 1% of supply voltage; fripple = 100 Hz. Ripple rejection RR to VDDA is dependent on the value of the external
capacitor (CEXT3 in Fig.1) connected to Vref. The value here assumes that CEXT3 = 1 µF.
3. Minimum VIL and maximum VIH are peak values to allow for transients.
4. ILImni measured at VI = 0 V; ILImax measured at VI = 5.5 V.
5. Reference levels = 10% and 90%.
ANALOG CHARACTERISTICS
VDD = VDDA = VDDO = 5 V; VSS = 0 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reference values
Vref
reference voltage level
2.45
2.5
2.55
V
RCONV
current-to-voltage
conversion resistor
1.6
2.2
2.8
kΩ
Analog outputs
RES
resolution
−
−
18
bit
VFS(rms)
full-scale output voltage
(pins 23 and 25)
(RMS value)
1.425
1.5
1.575
V
VOFF
output voltage DC offset with
respect to reference voltage
level Vref
−80
−65
−50
mV
TCFS
full scale temperature
coefficient
−
±100 × 10−6
−
1995 Dec 08
11
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
SYMBOL
PARAMETER
TDA1305T
CONDITIONS
(THD + N)/S total harmonic distortion plus at 0 dB input level;
noise-to-signal ratio
note 1
MIN.
TYP.
MAX.
UNIT
−
−90
−81
dB
−
0.003
0.009
%
at −60 dB input level;
note 2
−
−44
−40
dB
−
0.63
1.0
%
at −60 dB input level;
A-weighted; note 3
−
−46
−
dB
−
0.5
−
%
at 0 dB input level;
(20 Hz to 20 kHz);
note 4
−
−90
−81
dB
−
0.003
0.003
%
A weighted;
at code (00000H)
100
108
−
dB
S/N
signal-to-noise ratio at
bipolar zero
αcs
channel separation
85
100
−
dB
δVO
unbalance between outputs
−
0.2
0.3
dB
ZO
dynamic output impedance
−
10
−
Ω
RL
output load resistance
3
−
−
kΩ
CL
output load capacitance
−
−
200
pF
Notes
1. Measured with a 1 kHz, 0 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured
over a bandwidth of 20 Hz to 20 kHz.
2. Measured with a 1 kHz, -60 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured
over a bandwidth of 20 Hz to 20 kHz. For 16-bit input signals, the performance is limited to the theoretical maximum.
3. Measured with a 1 kHz, -60 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured
over a bandwidth of 20 Hz to 20 kHz and filtered with a A-weighted characteristic. For 16-bit input signals, the
performance is limited to the theoretical maximum.
4. Measured with a sine wave from 20 Hz to 20 kHz generated at a sampling rate of 48 kHz. The (THD + N)/S
measured over a bandwidth of 20 Hz to 20 kHz.
TEST AND APPLICATION INFORMATION
Filter characteristics (theoretical values)
Table 3
Normal speed filter characteristics.
ITEM
SAMPLE FREQUENCY
RANGE
Pass band
44.1 kHz
0 to 20 kHz
32 kHz
14.5 to 15 kHz
Stop band
44.1 kHz
24.1 to 150 kHz
150 kHz to infinity
32 kHz
1995 Dec 08
17 to 17.5 kHz
12
CONDITIONS
CHARACTERISTICS
0 ±0.025 dB
−0.15 dB (min.)
typical
−60 dB (max.)
worst case
−57 dB (max.)
typical
−57 dB (max.)
worst case
−47 dB (max.)
−40 dB (max.)
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
TDA1305T
De-emphasis filter characteristics (theoretical values)
Table 4
De-emphasis deviation from ideal 50 µs to 15 µs de-emphasis network.
ITEM
Gain deviation
SAMPLE FREQUENCY
RANGE
44.1 and 48 kHz
0 to 18 kHz
0 ±0.05 dB
18 to 20 kHz
0.12 dB (max.)
0 to 13 kHz
0 ±0.06 dB
13 to 15 kHz
0.22 dB (max.)
32 kHz
Phase deviation
44.1 and 48 kHz
CHARACTERISTICS
0 to 15 kHz
10 deg (max.)
15 to 20 kHz
15 deg (max.)
0 to 9 kHz
10 deg (max.)
9 to 15 kHz
16 deg (max.)
32 kHz
Double-speed characteristics
Table 5
Double-speed filter characteristics.
ITEM
Pass band
Stop band
RANGE
CONDITIONS
0 to 17 kHz
0 ±0.075 dB
17 to 20 kHz
−0.3 dB (min.)
24.1 to 150 kHz
typical
−47 dB (max.)
worst case
−45 dB (max.)
150 kHz to infinite
typical
−33 dB (max.)
worst case
−25 dB (max.)
Fig.4 Timing of input signals.
1995 Dec 08
CHARACTERISTICS
13
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
APPLICATION INFORMATION
Fig.5 Application diagram.
1995 Dec 08
14
TDA1305T
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
A typical application diagram is illustrated in Fig.5. The left
and right channel outputs can drive a line output directly.
The series inductor (L) in the digital supply line, though not
strictly necessary, helps to reduce crosstalk between the
digital and analog circuits.
measurement values of a small amount of engineering
samples. No guarantee for typical values is implied.
In Fig.6 measurements were taken with an 18-bit sine
wave generated at a sampling rate of 48 kHz. The
(THD + N)/S was measured over a bandwidth of
20 Hz to 20 kHz and filtered with A-weighted
characteristics. The graph was constructed from average
measurement values of a small amount of engineering
samples. No guarantee for typical values is implied.
In Fig.6 measurements were taken with an 18-bit sine
wave generated at a sampling rate of 48 kHz. The
(THD + N)/S was measured over a bandwidth of
20 Hz to 20 kHz. The graph was constructed from average
(1) Level = −60 dB.
(2) Level = 0 dB.
Fig.6 Total harmonic distortion as a function of signal frequency.
1995 Dec 08
TDA1305T
15
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
Fig.7 Total harmonic distortion as a function of signal level; (A-weighted).
1995 Dec 08
16
TDA1305T
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
TDA1305T
PACKAGE OUTLINE
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
HE
v M A
Z
15
28
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
14
e
bp
0
detail X
w M
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.71
0.69
0.30
0.29
0.050
0.419
0.043
0.055
0.394
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
inches
0.10
Z
(1)
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT136-1
075E06
MS-013AE
1995 Dec 08
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
17
o
8
0o
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
TDA1305T
SOLDERING
Wave soldering
Introduction
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1995 Dec 08
18
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
TDA1305T
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1995 Dec 08
19
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SCD47
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
513061/50/02/pp20
Document order number:
Date of release: 1995 Dec 08
9397 750 00517