INTEGRATED CIRCUITS P89C668 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM Preliminary data Supersedes data of 2001 Jul 19 IC28 Data Handbook 2001 Jul 27 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 • Parallel programmed with 87C51 compatible hardware interface to DESCRIPTION The P89C668 device contains a non-volatile 64 kbytes Flash program memory that is both parallel programmable and serial In-System Programmable. In-System Programming allows devices to alter their own program memory, in the actual end product, under software control. This opens up a range of applications that can include the ability to field update the application firmware. programmer • Speed up to 20 MHz with 6 clock cycles per machine cycle (40 MHz equivalent performance); up to 33 MHz with 12 clocks • Full static operation • RAM expandable externally to 64 kbytes • 4 level priority interrupt • 8 interrupt sources • Four 8-bit I/O ports • Full-duplex enhanced UART A default serial loader (boot loader) program in ROM allows serial In-System programming of the Flash memory without the need for a loader in the Flash code. User programs may erase and reprogram the Flash memory at will through the use of standard routines contained in ROM. This device is a Single-Chip 8-Bit Microcontroller manufactured in advanced CMOS process and is a derivative of the 80C51 microcontroller family. The device has the same instruction set as the 80C51. – Framing error detection – Automatic address recognition • Power control modes The device also has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. – Clock can be stopped and resumed – Idle mode – Power down mode The added features of the P89C668 makes it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. • Programmable clock out • Second DPTR register • Asynchronous port reset • Low EMI (inhibit ALE) • I2C serial interface • Programmable Counter Array (PCA) FEATURES • 80C51 Central Processing Unit • On-chip Flash Program Memory with In-System Programming (ISP) capability • Boot ROM contains low level Flash programming routines for – PWM downloading via the UART – Capture/compare • Can be programmed by the end-user application (IAP) ORDERING INFORMATION MEMORY RAM TEMPERATURE RANGE °C AND PACKAGE VOLTAGE RANGE 64 KB 8 KB 0 to +70, PLCC P89C668HFA 64 KB 8 KB P89C668HBBD 64 KB 8 KB MEMORY SIZE 64K × 8 FLASH P89C668HBA 2001 Jul 27 FREQ. (MHz) 6 CLOCK MODE 12 CLOCK MODE DWG. # 4.5 to 5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 –40 to +85, PLCC 4.5 to 5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2 0 to +70, LQFP 4.5 to 5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1 2 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 BLOCK DIAGRAM P0.0–P0.7 P2.0–P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC VSS RAM ADDR REGISTER PORT 0 LATCH RAM PORT 2 LATCH FLASH 8 B REGISTER STACK POINTER ACC PROGRAM ADDRESS REGISTER TMP1 TMP2 BUFFER ALU SFRs TIMERS PSW PC INCREMENTER P.C.A. 8 16 PSEN ALE EAVPP TIMING AND CONTROL RST INSTRUCTION REGISTER PROGRAM COUNTER DPTR’S MULTIPLE PORT 1 LATCH PD PORT 3 LATCH I2C OSCILLATOR PORT 1 DRIVERS XTAL1 PORT 3 DRIVERS SCL XTAL2 P1.0–P1.7 SDA P3.0–P3.7 su01089 2001 Jul 27 3 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM LOGIC SYMBOL P89C668 LOW QUAD FLAT PACKAGE PIN FUNCTIONS VCC VSS 44 34 XTAL1 PORT 0 ADDRESS AND 1 33 DATA BUS LQFP XTAL2 T2 T2EX PORT 2 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADDRESS BUS SU01090 PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS 6 1 39 PLCC 17 29 18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NIC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/SCL P1.7/SDA RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 * NO INTERNAL CONNECTION 2001 Jul 27 28 Function P3.4/T0/CEX3 P3.5/T1/CEX4 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 Function P1.5/CEX2 P1.6/SCL P1.7/SDA RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0/CEX3 P3.5/T1/CEX4 P3.6/WR P3.7/RD XTAL2 XTAL1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 * NO INTERNAL CONNECTION 40 7 23 12 SCL SDA PORT 3 SECONDARY FUNCTIONS PSEN ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD 11 PORT 1 RST EA/VPP Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15 PSEN ALE NIC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC SU01091 4 22 Function VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NIC* EA/VPP P0.7/AD7 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NIC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 SU01401 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 PIN DESCRIPTIONS MNEMONIC PIN NUMBER NAME AND FUNCTION PLCC LQFP VSS 22 16 I Ground: 0 V reference. VCC 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. 2–9 40–44, 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). 2 3 4 5 6 7 8 9 40 41 42 43 44 1 2 3 I/O I I I/O I/O I/O I/O I/O P2.0–P2.7 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. P3.0–P3.7 11, 13–19 5, 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the P89C668, as listed below: 11 13 14 15 16 17 18 19 5 7 8 9 10 11 12 13 I O I I I I O O RST 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. ALE 33 27 O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. PSEN 32 26 O Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. P0.0–0.7 P1.0–P1.7 2001 Jul 27 Alternate functions for P89C668 Port 1 include: T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out) T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control ECI (P1.2): External Clock Input to the PCA CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 SCL (P1.6): I2C bus clock line (open drain) SDA (P1.7): I2C bus data line (open drain) RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt CEX3/T0 (P3.4): Timer 0 external input; Capture/Compare External I/O for PCA module 3 CEX4/T1 (P3.5): Timer 1 external input; Capture/Compare External I/O for PCA module 4 WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe 5 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM MNEMONIC PIN NUMBER P89C668 NAME AND FUNCTION PLCC LQFP EA/VPP 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations. If EA is held high, the device executes from internal program memory. The value on the EA pin is latched when RST is released and any subsequent changes have no effect. Since the P89C668 has 64k internal memory, the P89C668 will execute only from internal memory when EA is held high. This pin also receives the programming supply voltage (VPP) during Flash programming. XTAL1 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin (other than VPP) must not be higher than VCC + 0.5 V or less than VSS – 0.5 V. 2001 Jul 27 6 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 Table 1. Special Function Registers SYMBOL DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H AUXR# Auxiliary 8EH – – – – – – EXTRAM AO xxxxxx10B – GF2 0 – DPS xxxxxxx0B F4 F3 F2 F1 F0 AUXR1# Auxiliary 1 A2H – – ENBOOT B* B register F0H F7 F6 F5 CCAP0H# CCAP1H# CCAP2H# CCAP3H# CCAP4H# CCAP0L# CCAP1L# CCAP2L# CCAP3L# CCAP4L# Module 0 Capture High Module 1 Capture High Module 2 Capture High Module 3 Capture High Module 4 Capture High Module 0 Capture Low Module 1 Capture Low Module 2 Capture Low Module 3 Capture Low Module 4 Capture Low FAH FBH FCH FDH FEH EAH EBH ECH EDH EEH CCAPM0# Module 0 Mode C2H – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM1# Module 1 Mode C3H – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM2# Module 2 Mode C4H – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM3# Module 3 Mode C5H – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM4# Module 4 Mode C6H – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B C7 C6 C5 C4 C3 C2 C1 C0 00H xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB CCON*# CH# CL# PCA Counter Control PCA Counter High PCA Counter Low C0H F9H E9H CF CR – CCF4 CCF3 CCF2 CCF1 CCF0 00x00000B 00H 00H CMOD# PCA Counter Mode C1H CIDL WDTE – – – CPS1 CPS0 ECF 00xxx000B DPTR: DPH DPL Data Pointer (2 bytes) Data Pointer High Data Pointer Low 83H 82H 00H 00H AF AE AD AC AB AA A9 A8 IEN0* Interrupt Enable 0 A8H EA EC ES1 ES0 ET1 EX1 ET0 EX0 00H IEN1* Interrupt Enable 1 E8 – – – – – – – ET2 xxxxxxx0B BF BE BD BC BB BA B9 B8 PT2 PPC PS1 PS0 PT1 PX1 PT0 PX0 B7 B6 B5 B4 B3 B2 B1 B0 PT2H PPCH PS1H PS0H PT1H PX1H PT0H PX0H 87 86 85 84 83 82 81 80 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 97 96 95 94 93 92 91 90 SCL CEX2 CEX1 CEX0 ECI T2EX T2 IP* IPH# P0* Interrupt Priority Interrupt Priority High Port 0 B8H B7H 80H x0000000B x0000000B FFH P1* Port 1 90H SDA A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 B7 B6 B5 B4 B3 B2 B1 B0 P3* Port 3 B0H RD WR T1/ CEX4 T0/ CEX3 INT1 INT0 TxD RxD FFH SMOD0 – POF GF1 GF0 PD IDL 00xxx000B PCON#1 Power Control 87H SMOD1 * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. – Reserved bits. 1. Reset value depends on reset source. 2001 Jul 27 7 FFH FFH Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 Table 1. 89C51RC+/RD+ Special Function Registers (Continued) DESCRIPTION DIRECT ADDRESS PSW* Program Status Word D0H RCAP2H# RCAP2L# Timer 2 Capture High Timer 2 Capture Low CBH CAH 00H 00H SADDR# SADEN# Slave Address Slave Address Mask A9H B9H 00H 00H S0BUF Serial Data Buffer 99H SYMBOL BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 CY AC F0 RS1 RS0 OV F1 P RESET VALUE 00000000B xxxxxxxxB 9F 9E 9D 9C 9B 9A 99 98 SM0/FE SM1 SM2 REN TB8 RB8 TI RI S0CON* Serial Control 98H SP Stack Pointer 81H 00H 07H S1DAT# Serial 1 Data DAH 00H S1IST Serial 1 Internal Status DCH S1ADR# Serial 1 Address DBH S1STA# Serial 1 Status D9H SC4 DF DE S1CON*# Serial 1 Control D8H CR2 ENS1 8F 8E TR1 xxxxxxxx SLAVE ADDRESS SC3 SC2 0 GC 00H 0 F8H SC1 SC0 0 DD DC DB DA D9 D8 STA STO SI AA CR1 CR0 8D 8C 8B 8A 89 88 TF0 TR0 IE1 IT1 IE0 IT0 TCON* Timer Control 88H TF1 CF CE CD CC CB CA C9 C8 T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 T2MOD# Timer 2 Mode Control C9H – – – – – – T2OE DCEN TH0 TH1 TH2# TL0 TL1 TL2# Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 8CH 8DH CDH 8AH 8BH CCH TMOD Timer Mode 89H 00000000B 00H 00H xxxxxx00B 00H 00H 00H 00H 00H 00H GATE C/T M1 M0 GATE C/T M1 M0 00H WDTRST Watchdog Timer Reset A6H * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. – Reserved bits. OSCILLATOR CHARACTERISTICS RESET XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. A reset is accomplished by holding the RST pin high for at least two machine cycles (12 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH1 (min.) is applied to RESET. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. Minimum and maximum high and low times specified in the data sheet must be observed. The value on the EA pin is latched when RST is deasserted and has no further effect. 2001 Jul 27 8 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM LOW POWER MODES P89C668 Design Consideration • When the idle mode is terminated by a hardware reset, the device Stop Clock Mode normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested. Idle Mode ONCE Mode In the idle mode (see Table 2), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. Power-Down Mode To save even more power, a Power Down mode (see Table 2) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0 V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated. Programmable Clock-Out A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. to input the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz operating frequency. Either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down. 2 Oscillator Frequency (65536 * RCAP2H, RCAP2L) Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same. POWER OFF FLAG The Power Off Flag (POF) is set by on-chip circuitry when the VCC level on the P89C668 rises from 0 V to 5 V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3 V for the POF to remain unaffected by the VCC level. Table 2. External Pin Status During Idle and Power-Down Mode MODE PROGRAM MEMORY ALE PSEN Idle Internal 1 Idle External 1 Power-down Internal 0 Power-down External 0 2001 Jul 27 PORT 0 PORT 1 1 Data 1 Float 0 0 9 PORT 2 PORT 3 Data Data Data Data Address Data Data Data Data Data Float Data Data Data Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM I2C SERIAL COMMUNICATION — SIO1 P89C668 Note that in both the P89C668 and the 8XC552 the I2C pins are alternate functions to port pins P1.6 and P1.7. Because of this, P1.6 and P1.7 on these parts do not have a pull-up structure as found on the 80C51. Therefore P1.6 and P1.7 have open drain outputs on the P89C668. The I2C serial port is identical to the I2C serial port on the 8XC552, 8XC654, and 8XC652 devices. The operation of this subsystem is described in detail in the 8XC552 section of this manual. Serial Control Register (S1CON) – See Table 3 S1CON (D8H) CR2 ENS1 STA STO SI AA CR1 CR0 Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation. Table 3. Serial Clock Rates BIT FREQUENCY (kHz) AT fOSC CR2 CR1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 3 MHz 23 27 31 37 6.25 50 100 0.24 < 62.5 0 < 255 6 MHz 47 54 63 75 12.5 100 200 0.49 < 62.5 0 < 254 8 MHz 62.5 71 83.3 100 17 1331 2671 0.65 < 55.6 0 < 253 12 MHz2 15 MHz2 fOSC DIVIDED BY 94 1071 1251 1501 25 2001 4001 0.98 < 50.0 0 < 251 1171 128 112 96 80 480 60 30 48 × (256 – (reload value Timer 1)) Reload value Timer 1 in Mode 2. 1341 1561 1881 31 2501 5001 1.22 < 52.1 0 < 250 NOTES: 1. These frequencies exceed the upper limit of 100 kHz of the I2C-bus specification and cannot be used in an I2C-bus application. 2. At fOSC = 12 MHz/15 MHz the maximum I2C bus rate of 100 kHz cannot be realized due to the fixed divider rates. 2001 Jul 27 10 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 Figure 3). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. TIMER 2 OPERATION Timer 2 Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2* in the special function register T2CON (see Figure 1). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 4. Figure 4 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. Capture Mode In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure 2 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 pulses.). If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. Auto-Reload Mode (Up or Down Counter) The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation. In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter [C/T2* in T2CON]) then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see (MSB) TF2 (LSB) EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Symbol Position Name and Significance TF2 T2CON.7 EXF2 T2CON.6 RCLK T2CON.5 TCLK T2CON.4 EXEN2 T2CON.3 TR2 C/T2 T2CON.2 T2CON.1 CP/RL2 T2CON.0 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. A logic 1 starts the timer. Timer or counter select. (Timer 2) 0 = Internal timer (OSC/6) 1 = External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. SU01209 Figure 1. Timer/Counter 2 (T2CON) Control Register 2001 Jul 27 11 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 Table 4. Timer 2 Operating Modes RCLK + TCLK CP/RL2 TR2 0 0 1 16-bit Auto-reload 0 1 1 16-bit Capture 1 X 1 Baud rate generator X X 0 (off) OSC ÷6 MODE C/T2 = 0 TL2 (8-bits) TH2 (8-bits) TF2 C/T2 = 1 T2 Pin Control TR2 Capture Transition Detector Timer 2 Interrupt RCAP2L RCAP2H T2EX Pin EXF2 Control EXEN2 SU01210 Figure 2. Timer 2 in Capture Mode T2MOD Address = 0C9H Reset Value = XXXX XX00B Not Bit Addressable Bit * — — — — — — T2OE DCEN 7 6 5 4 3 2 1 0 Symbol Function — Not implemented, reserved for future use.* T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU00729 Figure 3. Timer 2 Mode (T2MOD) Control Register 2001 Jul 27 12 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM ÷6 OSC P89C668 C/T2 = 0 TL2 (8-BITS) TH2 (8-BITS) C/T2 = 1 T2 PIN CONTROL TR2 RELOAD TRANSITION DETECTOR RCAP2L RCAP2H TF2 TIMER 2 INTERRUPT T2EX PIN EXF2 CONTROL SU01211 EXEN2 Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0) (DOWN COUNTING RELOAD VALUE) FFH FFH TOGGLE EXF2 OSC ÷6 C/T2 = 0 OVERFLOW TL2 T2 PIN TH2 TF2 INTERRUPT C/T2 = 1 CONTROL TR2 COUNT DIRECTION 1 = UP 0 = DOWN RCAP2L RCAP2H (UP COUNTING RELOAD VALUE) Figure 5. Timer 2 Auto Reload Mode (DCEN = 1) 2001 Jul 27 13 T2EX PIN SU01212 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 Timer 1 Overflow ÷2 “0” “1” OSC C/T2 = 0 SMOD TL2 (8-bits) “1” TH2 (8-bits) “0” RCLK C/T2 = 1 T2 Pin Control ÷ 16 “1” TR2 Reload Transition Detector RCAP2L T2EX Pin EXF2 RCAP2H RX Clock “0” TCLK ÷ 16 TX Clock Timer 2 Interrupt Control EXEN2 Note availability of additional external interrupt. SU01213 Figure 6. Timer 2 in Baud Rate Generator Mode Table 5. Timer 2 Generated Commonly Used Baud Rates Modes 1 and 3 Baud Rates + Timer 2 Overflow Rate 16 The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T2*=0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Timer 2 Ba d Rate Baud Osc Freq 750 k 19.2 k 5.6 k 4.8 k 2.4 k 600 220 600 220 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 6 MHz 6 MHz RCAP2H RCAP2L FF FF FF FF FE FB F2 FD F9 FF D9 B2 64 C8 1E AF 8F 57 Usually, as a timer it would increment every machine cycle (i.e., the oscillator frequency). As a baud rate generator, it increments at the oscillator frequency. Thus the baud rate formula is as follows: 1/ 6 Modes 1 and 3 Baud Rates = Oscillator Frequency [16 [65536 * (RCAP2H, RCAP2L)]] Where: (RCAP2H, RCAP2L)= The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode shown in Figure 6, is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. Baud Rate Generator Mode Bits TCLK and/or RCLK in T2CON (Table 5) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates – one generated by Timer 1, the other by Timer 2. Figure 6 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode,in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be The baud rates in modes 1 and 3 are determined by Timer 2’s overflow rate given below: 2001 Jul 27 14 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 Where fOSC= Oscillator Frequency written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as: Table 5 shows commonly used baud rates and how they can be obtained from Timer 2. RCAP2H, RCAP2L + 65536 * ǒ 32 Ǔ f OSC Baud Rate Summary Of Baud Rate Equations Timer/Counter 2 Set-up Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is: Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. see Table 6 for set-up of Timer 2 as a timer. Also see Table 7 for set-up of Timer 2 as a counter. Baud Rate + Timer 2 Overflow Rate 16 If Timer 2 is being clocked internally , the baud rate is: Baud Rate + Table 6. [16 f OSC [65536 * (RCAP2H, RCAP2L)]] Timer 2 as a Timer T2CON MODE INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2) 16-bit Auto-Reload 00H 08H 16-bit Capture 01H 09H Baud rate generator receive and transmit same baud rate 34H 36H Receive only 24H 26H Transmit only 14H 16H Table 7. Timer 2 as a Counter TMOD MODE INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2) 16-bit 02H 0AH Auto-Reload 03H 0BH NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode. 2001 Jul 27 15 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM Slave 1 Enhanced UART The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. Slave 0 SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 Slave 1 SADDR = SADEN = Given = 1110 0000 1111 1010 1110 0X0X Slave 2 SADDR = SADEN = Given = 1110 0000 1111 1100 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: 2001 Jul 27 1100 0000 1111 1110 1100 000X In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in S0CON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 9. SADDR = SADEN = Given = SADDR = SADEN = Given = In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the S0CON register. The FE bit shares the S0CON.7 bit with SM0 and the function of S0CON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then S0CON.7 functions as FE. S0CON.7 functions as SM0 when SMOD0 is cleared. When used as FE S0CON.7 can only be cleared by software. Refer to Figure 8. Slave 0 P89C668 Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. 1100 0000 1111 1101 1100 00X0 16 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 S0CON Address = 98H Reset Value = 0000 0000B Bit Addressable SM0/FE Bit: SM1 7 6 (SMOD0 = 0/1)* SM2 REN TB8 RB8 Tl Rl 5 4 3 2 1 0 Symbol Function FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. SM0 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) SM1 Serial Port Mode Bit 1 SM0 SM1 Mode 0 0 1 1 0 1 0 1 0 1 2 3 Description Baud Rate** shift register 8-bit UART 9-bit UART 9-bit UART fOSC/6 variable fOSC/32 or fOSC/16 variable SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Tl Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. NOTE: *SMOD0 is located at PCON6. **fOSC = oscillator frequency SU01457 Figure 7. S0CON: Serial Port Control Register 2001 Jul 27 17 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM D0 D1 D2 D3 P89C668 D4 D5 D6 D7 D8 DATA BYTE START BIT ONLY IN MODE 2, 3 STOP BIT SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL SM0 / FE SM1 SM2 REN TB8 RB8 TI RI S0CON (98H) SMOD1 SMOD0 – POF LVF GF0 GF1 IDL PCON (87H) 0 : S0CON.7 = SM0 1 : S0CON.7 = FE SU01458 Figure 8. UART Framing Error Detection D0 D1 D2 D3 D4 SM0 SM1 1 1 1 0 D5 SM2 1 D6 D7 D8 REN TB8 RB8 1 X TI RI S0CON (98H) RECEIVED ADDRESS D0 TO D7 COMPARATOR PROGRAMMED ADDRESS IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS” – WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. SU01459 Figure 9. UART Multiprocessor Communication, Automatic Address Recognition 2001 Jul 27 18 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt levels rather than two as on the 80C51. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. Interrupt Priority Structure The P89C668 has an 8 source four-level interrupt structure (see Table 8). There are 4 SFRs associated with the four-level interrupt. They are the IE, IEN1, IP, and IPH. (See Figures 10, 11, 12, and 13.) The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible. The IPH is located at SFR address B7H. The structure of the IPH register and a description of its bits is shown in Figure 12. The function of the IPH SFR is simple and when combined with the IP SFR determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table: PRIORITY BITS INTERRUPT PRIORITY LEVEL IPH.x IP.x 0 0 Level 0 (lowest priority) 0 1 Level 1 1 0 Level 2 1 1 Level 3 (highest priority) Table 8. Interrupt Table SOURCE POLLING PRIORITY REQUEST BITS X0 1 IE0 SI01 (I2C) HARDWARE CLEAR? N (L)1 Y (T)2 VECTOR ADDRESS 03H 2 — N 2BH T0 3 TP0 Y 0BH X1 4 IE1 N (L) Y (T) 13H T1 5 TF1 Y 1BH SP 6 RI, TI N 23H T2 7 TF2, EXF2 N 3BH PCA 8 CF, CCFn n = 0–4 N 33H NOTES: 1. L = Level activated 2. T = Transition activated IEN0 (0A8H) 7 6 5 4 3 2 1 0 EA EC ES1 ES0 ET1 EX1 ET0 EX0 Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables it. BIT IEN0.7 SYMBOL EA IEN0.6 IEN0.5 IEN0.4 IEN0.3 IEN0.2 IEN0.1 IEN0.0 EC ES1 ES0 ET1 EX1 ET0 EX0 FUNCTION Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. PCA interrupt enable bit I2C interrupt enable bit. Serial Port interrupt enable bit. Timer 1 interrupt enable bit. External interrupt 1 enable bit. Timer 0 interrupt enable bit. External interrupt 0 enable bit. SU01460 Figure 10. IE Registers 2001 Jul 27 19 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM IP (0B8H) P89C668 7 6 5 4 3 2 1 0 PT2 PPC PS1 PS0 PT1 PX1 PT0 PX0 Priority Bit = 1 assigns high priority Priority Bit = 0 assigns low priority BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 SYMBOL PT2 PPC PS1 PS0 PT1 PX1 PT0 PX0 FUNCTION Timer 2 interrupt priority bit. PCA interrupt priority bit Serial I/O1 (I2C) interrupt priority bit. Serial Port interrupt priority bit. Timer 1 interrupt priority bit. External interrupt 1 priority bit. Timer 0 interrupt priority bit. External interrupt 0 priority bit. SU01461 Figure 11. IP Registers IPH (B7H) 7 6 5 4 3 2 1 0 PT2H PPCH PS1H PS0H PT1H PX1H PT0H PX0H Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT IPH.7 IPH.6 IPH.5 IPH.4 IPH.3 IPH.2 IPH.1 IPH.0 SYMBOL PT2H PPCH PS1H PS0H PT1H PX1H PT0H PX0H FUNCTION Timer 2 interrupt priority bit high. PCA interrupt priority bit Serial I/O (I2C) interrupt priority bit high. Serial Port interrupt priority bit high. Timer 1 interrupt priority bit high. External interrupt 1 priority bit high. Timer 0 interrupt priority bit high. External interrupt 0 priority bit high. SU01462 Figure 12. IPH Registers IEN1 (E8H) 7 6 5 4 3 2 1 0 — — — — — — — ET2 Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT IEN1.7 IEN1.6 IEN1.5 IEN1.4 IEN1.3 IEN1.2 IEN1.1 IEN1.0 SYMBOL — — — — — — — ET2 FUNCTION Timer 2 interrupt enable bit. SU01095 Figure 13. IEN1 Registers 2001 Jul 27 20 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit. Reduced EMI Mode The AO bit (AUXR.0) in the AUXR register when set disables the ALE output. The ENBOOT bit determines whether the BOOTROM is enabled or disabled. This bit will automatically be set if the status byte is non zero during reset or PSEN is pulled low, ALE floats high, and EA > VIH on the falling edge of reset. Otherwise, this bit will be cleared during reset. Reduced EMI Mode AUXR (8EH) 7 6 5 4 3 2 1 0 – – – – – – EXTRAM AO AUXR.1 AUXR.0 EXTRAM AO P89C668 DPS Turns off ALE output. BIT0 AUXR1 DPTR0 Dual DPTR DPH (83H) The dual DPTR structure (see Figure 14) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them. DPL (82H) EXTERNAL DATA MEMORY SU00745A Figure 14. • New Register Name: AUXR1# • SFR Address: A2H • Reset Value: xxxxxxx0B DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: AUXR1 (A2H) 7 6 5 4 3 2 1 0 – – ENBOOT – GF2 0 – DPS Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPS DPTR0 0 DPTR1 1 The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. INC DPTR Increments the data pointer by 1 MOV DPTR, #data16 Loads the DPTR with a 16-bit constant MOV A, @ A+DPTR Move code byte relative to DPTR to ACC MOVX A, @ DPTR Move external RAM (16-bit address) to ACC MOVX @ DPTR , A Move ACC to external RAM (16-bit address) JMP @ A + DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details. The GF2 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to 2001 Jul 27 DPTR1 21 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 ECF bit in the CMOD register is set, The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. The PCA interrupt system shown in Figure 17. Programmable Counter Array (PCA) The Programmable Counter Array available on the and P89C668 is a special 16-bit Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3(CEX0), module 1 to P1.4(CEX1), etc. The basic PCA configuration is shown in Figure 15. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Figure 20). The registers contain the bits that control the mode that each module will operate in. The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register. The PCA timer is a common time base for all five modules and can be programmed to run at: 1/6 the oscillator frequency, 1/2 the oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P1.2). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR as follows (see Figure 18): CPS1 CPS0 PCA Timer Count Source 0 0 1/6 oscillator frequency 0 1 1/2 oscillator frequency 1 0 Timer 0 overflow 1 1 External Input at ECI pin In the CMOD SFR are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during idle mode, WDTE which enables or disables the watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. These functions are shown in Figure 16. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Figure 21 shows the CCAPMn settings for the various PCA functions. The watchdog timer function is implemented in module 4 (see Figure 25). There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output. The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (refer to Figure 19). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the 16 BITS MODULE 0 P1.3/CEX0 MODULE 1 P1.4/CEX1 MODULE 2 P1.5/CEX2 MODULE 3 P3.4/CEX3 MODULE 4 P3.5/CEX4 16 BITS PCA TIMER/COUNTER TIME BASE FOR PCA MODULES MODULE FUNCTIONS: 16-BIT CAPTURE 16-BIT TIMER 16-BIT HIGH SPEED OUTPUT 8-BIT PWM WATCHDOG TIMER (MODULE 4 ONLY) SU01416 Figure 15. Programmable Counter Array (PCA) 2001 Jul 27 22 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 TO PCA MODULES OSC/6 OVERFLOW OSC/2 CH INTERRUPT CL 16–BIT UP COUNTER TIMER 0 OVERFLOW EXTERNAL INPUT (P1.2/ECI) 00 01 10 11 DECODE IDLE CIDL CF WDTE –– –– –– CPS1 CPS0 ECF CMOD (C1H) CR –– CCF4 CCF3 CCF2 CCF1 CCF0 CCON (C0H) SU01096 Figure 16. PCA Timer/Counter CF CR –– CCF4 CCF3 CCF2 CCF1 CCF0 CCON (C0H) PCA TIMER/COUNTER MODULE 0 IE.6 EC IE.7 EA TO INTERRUPT PRIORITY DECODER MODULE 1 MODULE 2 MODULE 3 MODULE 4 CMOD.0 ECF CCAPMn.0 ECCFn SU01097 Figure 17. PCA Interrupt System 2001 Jul 27 23 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 CMOD Address = C1H Reset Value = 00XX X000B CIDL WDTE – – – CPS1 7 6 5 4 3 2 Bit: CPS0 1 ECF 0 Symbol Function CIDL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. – Not implemented, reserved for future use.* CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. CPS1 CPS0 Selected PCA Input** 0 0 1 1 ECF 0 1 0 1 Internal clock, fOSC ÷ 6 Internal clock, fOSC ÷ 2 Timer 0 overflow External clock at ECI/P1.2 pin (max. rate = fOSC ÷ 4) 0 1 2 3 PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. ** fOSC = oscillator frequency SU01098 Figure 18. CMOD: PCA Counter Mode Register CCON Address = 0C0H Reset Value = 00X0 0000B Bit Addressable Bit: CF CR – CCF4 CCF3 CCF2 CCF1 CCF0 7 6 5 4 3 2 1 0 Symbol Function CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. – Not implemented, reserved for future use*. CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU01099 Figure 19. CCON: PCA Counter Control Register 2001 Jul 27 24 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM CCAPMn Address CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 P89C668 0C2H 0C3H 0C4H 0C5H 0C6H Reset Value = X000 0000B Not Bit Addressable Bit: – ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 7 6 5 4 3 2 1 0 Symbol Function – ECOMn CAPPn CAPNn MATn Not implemented, reserved for future use*. Enable Comparator. ECOMn = 1 enables the comparator function. Capture Positive, CAPPn = 1 enables positive edge capture. Capture Negative, CAPNn = 1 enables negative edge capture. Match. When MATn = 1, a match of the PCA counter with this module’s compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle. When TOGn = 1, a match of the PCA counter with this module’s compare/capture register causes the CEXn pin to toggle. Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. TOGn PWMn ECCFn NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU01100 Figure 20. CCAPMn: PCA Modules Compare/Capture Registers – ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn X 0 0 0 0 0 0 0 No operation MODULE FUNCTION X X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X X 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn X X 1 1 0 0 0 X 16-bit capture by a transition on CEXn X 1 0 0 1 0 0 X 16-bit Software Timer X 1 0 0 1 1 0 X 16-bit High Speed Output X 1 0 0 0 0 1 0 8-bit PWM X 1 0 0 1 X 0 X Watchdog Timer Figure 21. PCA Module Modes (CCAPMn Register) PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. Refer to Figure 22. counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set (see Figure 24). Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 25 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module’s capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module’s CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows updating the PWM without glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode. 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 23). High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA 2001 Jul 27 25 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM CF CR –– CCF4 P89C668 CCF3 CCF2 CCF1 CCF0 CCON (0C0H) PCA INTERRUPT (TO CCFn) PCA TIMER/COUNTER CH CL CCAPnH CCAPnL CAPTURE CEXn –– ECOMn CAPPn CAPNn MATn TOGn PWMn 0 0 0 0 ECCFn CCAPMn, n= 0 to 4 (C2H – C6H) SU01101 Figure 22. PCA Capture Mode CF WRITE TO CCAPnH –– CCF4 CCF3 CCF2 CCF1 CCF0 CCON (C0H) RESET CCAPnH WRITE TO CCAPnL 0 CR PCA INTERRUPT CCAPnL (TO CCFn) 1 ENABLE MATCH 16–BIT COMPARATOR CH CL PCA TIMER/COUNTER –– ECOMn CAPPn CAPNn 0 0 MATn TOGn PWMn 0 0 ECCFn CCAPMn, n= 0 to 4 (C2H – C6H) SU01102 Figure 23. PCA Compare Mode 2001 Jul 27 26 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM CF WRITE TO CCAPnH CR CCF4 CCF3 CCF2 CCF1 CCON (C0H) CCF0 RESET CCAPnH WRITE TO CCAPnL 0 –– P89C668 PCA INTERRUPT CCAPnL (TO CCFn) 1 MATCH ENABLE 16–BIT COMPARATOR TOGGLE CH CEXn CL PCA TIMER/COUNTER –– ECOMn CAPPn CAPNn 0 0 MATn TOGn PWMn 1 CCAPMn, n: 0..4 (C2H – C6H) ECCFn 0 SU01103 Figure 24. PCA High Speed Output Mode CCAPnH CCAPnL 0 CL < CCAPnL ENABLE 8–BIT COMPARATOR CEXn CL >= CCAPnL 1 CL OVERFLOW PCA TIMER/COUNTER –– ECOMn CAPPn CAPNn MATn TOGn 0 0 0 0 PWMn ECCFn CCAPMn, n: 0..4 (C2H – C6H) 0 SU01104 Figure 25. PCA PWM Mode 2001 Jul 27 27 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM CIDL WRITE TO CCAP4L –– –– –– CPS1 CPS0 ECF CMOD (C1H) RESET CCAP4H WRITE TO CCAP4H 1 WDTE P89C668 CCAP4L MODULE 4 0 ENABLE MATCH 16–BIT COMPARATOR CH RESET CL PCA TIMER/COUNTER –– ECOMn CAPPn CAPNn MATn 0 0 1 TOGn X PWMn ECCFn 0 X CCAPM4 (C6H) SU01105 Figure 26. PCA Watchdog Timer m(Module 4 only) The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 26 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. Figure 27 shows the code for initializing the watchdog timer. Module 4 can be configured in either compare mode, and the WDTE bit in CMOD must also be set. The user’s software then must periodically change (CCAP4H,CCAP4L) to keep a match from occurring with the PCA timer (CH,CL). This code is given in the WATCHDOG routine in Figure 27. In order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the PCA timer, This routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program within 216 count of the PCA timer. 2. periodically change the PCA timer value so it will never match the compare values, or 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. 2001 Jul 27 28 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM INIT_WATCHDOG: MOV CCAPM4, #4CH MOV CCAP4L, #0FFH MOV CCAP4H, #0FFH ORL CMOD, #40H ; ; ; ; ; ; ; ; Module 4 in compare mode Write to low byte first Before PCA timer counts up to FFFF Hex, these compare values must be changed Set the WDTE bit to enable the watchdog timer without changing the other bits in CMOD ; ;******************************************************************** ; ; Main program goes here, but CALL WATCHDOG periodically. ; ;******************************************************************** ; WATCHDOG: CLR EA ; Hold off interrupts MOV CCAP4L, #00 ; Next compare value is within MOV CCAP4H, CH ; 255 counts of the current PCA SETB EA ; timer value RET Figure 27. PCA Watchdog Timer Initialization Code 2001 Jul 27 29 P89C668 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 For example: Expanded Data RAM Addressing The P89C668 has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 7936 bytes expanded RAM (ERAM). where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). The four segments are: 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. The ERAM can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory is physically located on-chip, logically occupies the first 7936-bytes of external data memory. MOV @R0,#data 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not affect ports P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during external addressing. For example, with EXTRAM = 0, 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. 4. The 7936-bytes expanded RAM (ERAM, 00H – 1EFFH) are indirectly accessed by move external instruction, MOVX, and with the EXTRAM bit cleared, see Figure 28. MOVX @R0,#data where R0 contains 0A0H, access the ERAM at address 0A0H rather than external memory. An access to external data memory locations higher than 7936 (i.e., 1F00H to FFFFH) will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. Refer to Figure 29. The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a 16-bit address. Port 2 outputs the high-order eight address bits (the contents of DPH) while Port 0 multiplexes the low-order eight address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD). When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example: MOV 0A0H,#data accesses the SFR at location 0A0H (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM. The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM. AUXR Address = 8EH Reset Value = xxxx xx10B Not Bit Addressable — — — — — — EXTRAM AO 7 6 5 4 3 2 1 0 Bit: Symbol Function AO Disable/Enable ALE AO Operating Mode 0 ALE is emitted at a constant rate of 1/3 the oscillator frequency. 1 ALE is active only during a MOVX or MOVC instruction. EXTRAM Internal/External RAM (00H – 1EFFH) access using MOVX @Ri/@DPTR EXTRAM Operating Mode 0 Internal ERAM (00H–1EFFH) access using MOVX @Ri/@DPTR 1 External data memory access. — Not implemented, reserved for future use*. NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU01106 Figure 28. AUXR: Auxiliary Register 2001 Jul 27 30 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM 1FFF FF FF UPPER 128 BYTES INTERNAL RAM ERAM 7936 BYTES P89C668 80 FFFF SPECIAL FUNCTION REGISTER EXTERNAL DATA MEMORY 80 1F00 1EFF LOWER 128 BYTES INTERNAL RAM 100 00 00 0000 SU01107 Figure 29. Internal and External Data Memory Address Space with EXTRAM = 0 HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR P89C668) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output reset HIGH pulse at the RST-pin (see the note below). Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the reset pin (see note below). The RESET pulse duration is 98 × TOSC, where TOSC = 1/fOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. 2001 Jul 27 31 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin RATING UNIT 0 to +70 or –40 to +85 °C –65 to +150 °C 0 to +13.0 V –0.5 to +6.5 V 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 2001 Jul 27 32 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 DC ELECTRICAL CHARACTERISTICS Tamb = 0 °C to +70 °C, 5 V ± 10% or –40 °C to +85 °C; 5 V ±5%; VSS = 0 V SYMBOL VIL PARAMETER Input low voltage MIN 4.5 V < VCC < 5.5 V –0.5 P1.7/SDA11 VIL2 Input low voltage to P1.6/SCL, VIH Input high voltage (ports 0, 1, 2, 3, EA) VIH1 VIH2 VOL Output low voltage, ports 1, 2, 38 VOL1 VOL2 TYP1 MAX UNIT 0.2 VCC–0.1 V –0.5 0.3VDD V 0.2VCC+0. 9 VCC+0.5 V Input high voltage, XTAL1, RST 0.7VCC VCC+0.5 V Input high voltage, P1.6/SCL, P1.7/SDA11 0.7VDD 6.0 V VCC = 4.5 V IOL = 1.6 mA2 0.4 V Output low voltage, port 0, ALE, PSEN 7, 8 VCC = 4.5 V IOL = 3.2 mA2 0.45 V Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0 mA 0.4 V VCC = 4.5 V IOH = –30 µA VCC – 0.7 V VCC = 4.5 V IOH = –3.2 mA VCC – 0.7 V –1 3 VOH Output high voltage, ports 1, 2, 3 VOH1 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V ITL Logical 1-to-0 transition current, ports 1, 2, 36 ILI Input leakage current, port 0 IL2 Input leakage current, P1.6/SCL, P1.7/SDA ICC Power supply current (see Figure 37): Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Fi Figure 44 ffor conditions) diti ) Programming and erase mode RRST LIMITS TEST CONDITIONS –75 µA VIN = 2.0 V See Note 4 –650 µA 0.45 < VIN < VCC – 0.3 ±10 µA 0 V < VI < 6 V 0 V < VDD < 5.5 V 10 µA 100 125 µA µA mA 225 kΩ See Note 5 Tamb = 0 °C to 70 °C Tamb = –40 °C to +85 °C fosc = 20 MHz Internal reset pull-down resistor 20 60 40 CIO Pin capacitance10 (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 41 through 44 for ICC test conditions and Figure 37 for ICC vs Freq. Active mode: ICC(MAX) = (2.8 × FREQ. + 8.0)mA for all devices, in 6 clock mode; (1.4 × FREQ. + 8.0)mA in 12 clock mode. Idle mode: ICC(MAX) = (1.2 × FREQ. +1.0)mA in 6 clock mode; (0.6 × FREQ. +1.0)mA in 12 clock mode. 6. This value applies to Tamb = 0 °C to +70 °C. 7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15 mA (*NOTE: This is 85 °C specification.) Maximum IOL per port pin: Maximum IOL per 8-bit port: 26 mA 71 mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 11. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5 V will be recognized as a logic 0 while an input voltage above 3.0 V will be recognized as a logic 1. 2001 Jul 27 33 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 AC ELECTRICAL CHARACTERISTICS (6 CLOCK MODE) Tamb = 0 °C to +70 °C, VCC = 5 V ± 10% or –40 °C to +85 °C, VCC = 5 V ±5%, VSS = 0 V1, 2, 3 VARIABLE CLOCK4 SYMBOL FIGURE PARAMETER 1/tCLCL 30 Oscillator frequency tLHLL 30 ALE pulse width tAVLL 30 tLLAX tLLIV 20 MHz CLOCK4 MIN MAX MIN MAX UNIT 0 20 0 20 MHz tCLCL–40 10 ns Address valid to ALE low 0.5tCLCL–20 5 ns 30 Address hold after ALE low 0.5tCLCL–20 30 ALE low to valid instruction in tLLPL 30 ALE low to PSEN low 0.5tCLCL–20 tPLPH 30 PSEN pulse width 1.5tCLCL–45 tPLIV 30 PSEN low to valid instruction in tPXIX 30 Input instruction hold after PSEN tPXIZ 30 Input instruction float after PSEN 0.5tCLCL–20 5 ns tAVIV 30 Address to valid instruction in 2.5tCLCL–80 45 ns tPLAZ 30 PSEN low to address float 10 10 ns 5 2tCLCL–65 ns 35 5 ns 30 1.5tCLCL–60 0 ns ns 15 0 ns ns Data Memory tRLRH 31, 32 RD pulse width 3tCLCL–100 50 tWLWH 31, 32 WR pulse width 3tCLCL–100 50 tRLDV 31, 32 RD low to valid data in tRHDX 31, 32 Data hold after RD tRHDZ 31, 32 Data float after RD tLLDV 31, 32 ALE low to valid data in tAVDV 31, 32 Address to valid data in tLLWL 31, 32 ALE low to RD or WR low tAVWL 31, 32 Address valid to WR low or RD low tQVWX 31, 32 Data valid to WR transition tWHQX 31, 32 Data hold after WR tQVWH 32 Data valid to WR high tRLAZ 31, 32 RD low to address float tWHLH 31, 32 RD or WR high to ALE high 2.5tCLCL–90 0 ns 35 0 ns ns tCLCL–20 5 ns 4tCLCL–150 50 ns 60 ns 125 ns 4.5tCLCL–165 1.5tCLCL–50 ns 1.5tCLCL+50 25 2tCLCL–75 25 ns 0.5tCLCL–25 0 ns 0.5tCLCL–20 5 ns 3.5tCLCL–130 45 0 0.5tCLCL–20 0.5tCLCL+20 5 ns 0 ns 45 ns External Clock tCHCX 34 High time 20 tCLCL–tCLCX ns tCLCX 34 Low time 20 tCLCL–tCHCX ns tCLCH 34 Rise time 5 ns tCHCL 34 Fall time 5 ns tXLXL 33 Serial port clock cycle time 6tCLCL 300 ns tQVXH 33 Output data setup to clock rising edge 5tCLCL–133 117 ns tXHQX 33 Output data hold after clock rising edge tCLCL–30 20 ns tXHDX 33 Input data hold after clock rising edge 0 0 ns Shift Register tXHDV 33 Clock rising edge to input data valid 5tCLCL–133 117 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. 2001 Jul 27 34 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 AC ELECTRICAL CHARACTERISTICS (6 CLOCK MODE) (Continued) Tamb = 0 °C to +70 °C, VCC = 5 V ± 10% or –40 °C to +85 °C, VCC = 5 V ± 5%, VSS = 0 V1, 2 SYMBOL PARAMETER INPUT OUTPUT I2C Interface tHD;STA START condition hold time ≥ 7 tCLCL > 4.0 µs 4 tLOW SCL low time ≥ 8 tCLCL > 4.7 µs 4 tHIGH SCL high time ≥ 7 tCLCL > 4.0 µs 4 tRC SCL rise time ≤ 1 µs –5 tFC SCL fall time ≤ 0.3 µs < 0.3 µs 6 tSU;DAT1 Data set-up time ≥ 250 ns > 10 tCLCL – tRD tSU;DAT2 SDA set-up time (before rep. START cond.) ≥ 250 ns > 1 µs 4 tSU;DAT3 SDA set-up time (before STOP cond.) ≥ 250 ns > 4 tCLCL tHD;DAT Data hold time ≥ 0 ns > 4 tCLCL – tFC tSU;STA Repeated START set-up time ≥ 7 tCLCL 4 > 4.7 µs 4 tSU;STO STOP condition set-up time ≥ 7 tCLCL 4 > 4.0 µs 4 tBUF Bus free time ≥ 7 tCLCL 4 > 4.7 µs 4 tRD ≤1 SDA rise time µs7 –5 tFD SDA fall time ≤ 300 ns7 < 0.3 µs 6 NOTES: 1. Parameters are valid over operating temperature range and voltage range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. These values are characterized but not 100% production tested. 4. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 5. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs. 6. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400 pF. 7. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. 2001 Jul 27 35 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM AC ELECTRICAL CHARACTERISTICS (12 CLOCK MODE) P89C668 Tamb = 0 °C to +70 °C, VCC = 5 V ± 10%, or –40 °C to +85 °C, VCC = 5 V ±5%, VSS = 0 V1, 2, 3 VARIABLE CLOCK4 33 MHz CLOCK4 SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 30 Oscillator frequency 0 33 0 33 MHz tLHLL 30 ALE pulse width 2tCLCL–40 21 ns tAVLL 30 Address valid to ALE low tCLCL–25 5 ns tLLAX 30 Address hold after ALE low tCLCL–25 5 ns tLLIV 30 ALE low to valid instruction in 4tCLCL–65 55 ns tLLPL 30 ALE low to PSEN low tCLCL–25 5 ns tPLPH 30 PSEN pulse width 3tCLCL–45 45 ns tPLIV 30 PSEN low to valid instruction in 3tCLCL–60 30 ns tPXIX 30 Input instruction hold after PSEN 0 0 ns tPXIZ 30 Input instruction float after PSEN tCLCL–25 5 ns tAVIV 30 Address to valid instruction in 5tCLCL–80 70 ns tPLAZ 30 PSEN low to address float 10 10 ns Data Memory tRLRH 31, 32 RD pulse width 6tCLCL–100 82 ns tWLWH 31, 32 WR pulse width 6tCLCL–100 82 ns tRLDV 31, 32 RD low to valid data in 5tCLCL–90 60 ns tRHDX 31, 32 Data hold after RD 0 0 ns tRHDZ 31, 32 Data float after RD 2tCLCL–28 32 ns tLLDV 31, 32 ALE low to valid data in 8tCLCL–150 90 ns tAVDV 31, 32 Address to valid data in 9tCLCL–165 105 ns tLLWL 31, 32 ALE low to RD or WR low 3tCLCL–50 3tCLCL+50 40 140 ns tAVWL 31, 32 Address valid to WR low or RD low 4tCLCL–75 45 ns tQVWX 31, 32 Data valid to WR transition tCLCL–30 0 ns tWHQX 31, 32 Data hold after WR tCLCL–25 5 ns tQVWH 32 Data valid to WR high 7tCLCL–130 80 ns tRLAZ 31, 32 RD low to address float 0 0 ns tWHLH 31, 32 RD or WR high to ALE high tCLCL–25 tCLCL+25 5 55 ns External Clock tCHCX 34 High time 17 tCLCL–tCLCX ns tCLCX 34 Low time 17 tCLCL–tCHCX ns tCLCH 34 Rise time 5 ns tCHCL 34 Fall time 5 ns Shift Register tXLXL 33 Serial port clock cycle time 12tCLCL 360 ns tQVXH 33 Output data setup to clock rising edge 10tCLCL–133 167 ns tXHQX 33 Output data hold after clock rising edge 2tCLCL–80 50 ns tXHDX 33 Input data hold after clock rising edge 0 0 ns tXHDV 33 Clock rising edge to input data valid 10tCLCL–133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz. 2001 Jul 27 36 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 AC ELECTRICAL CHARACTERISTICS (12 CLOCK MODE) (Continued) Tamb = 0 °C to +70 °C, VCC = 5 V ± 10%, or –40 °C to +85 °C, VCC = 5 V ± 5%, VSS = 0 V1, 2 SYMBOL PARAMETER INPUT OUTPUT I2C Interface tHD;STA START condition hold time ≥ 14 tCLCL > 4.0 µs 4 tLOW SCL low time ≥ 16 tCLCL > 4.7 µs 4 tHIGH SCL high time ≥ 14 tCLCL > 4.0 µs 4 tRC SCL rise time ≤ 1 µs –5 tFC SCL fall time ≤ 0.3 µs < 0.3 µs 6 tSU;DAT1 Data set-up time ≥ 250 ns > 20 tCLCL – tRD tSU;DAT2 SDA set-up time (before rep. START cond.) ≥ 250 ns > 1 µs 4 tSU;DAT3 SDA set-up time (before STOP cond.) ≥ 250 ns > 8 tCLCL tHD;DAT Data hold time ≥ 0 ns > 8 tCLCL – tFC tSU;STA Repeated START set-up time ≥ 14 tCLCL 4 > 4.7 µs 4 tSU;STO STOP condition set-up time ≥ 14 tCLCL 4 > 4.0 µs 4 tBUF Bus free time ≥ 14 tCLCL 4 > 4.7 µs 4 tRD ≤1 SDA rise time µs7 –5 tFD SDA fall time ≤ 300 ns7 < 0.3 µs 6 NOTES: 1. Parameters are valid over operating temperature range and voltage range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. These values are characterized but not 100% production tested. 4. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 5. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs. 6. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400 pF. 7. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 63 ns < tCLCL < 285 ns (16 MHz > fOSC > 3.5 MHz) the I2C interface meets the I2C-bus specification for bit-rates up to 100 kbit/s. 2001 Jul 27 37 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 EXPLANATION OF THE AC SYMBOLS P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE tLHLL ALE tAVLL tLLPL tPLPH tLLIV tPLIV PSEN tLLAX INSTR IN A0–A7 PORT 0 tPXIZ tPLAZ tPXIX A0–A7 tAVIV PORT 2 A0–A15 A8–A15 SU00006 Figure 30. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tAVLL tLLAX tRLAZ PORT 0 tRHDZ tRLDV tRHDX A0–A7 FROM RI OR DPL DATA IN A0–A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00025 Figure 31. External Data Memory Read Cycle 2001 Jul 27 38 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 ALE tWHLH PSEN tWLWH tLLWL WR tLLAX tAVLL tWHQX tQVWX tQVWH A0–A7 FROM RI OR DPL PORT 0 DATA OUT A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00026 Figure 32. External Data Memory Write Cycle INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE tXLXL CLOCK tXHQX tQVXH OUTPUT DATA 0 1 2 WRITE TO SBUF 3 4 5 6 7 tXHDX tXHDV SET TI INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID CLEAR RI SET RI SU00027 Figure 33. Shift Register Mode Timing VCC–0.5 0.45V 0.7VCC 0.2VCC–0.1 tCHCL tCHCX tCLCH tCLCX tCLCL SU00009 Figure 34. External Clock Drive 2001 Jul 27 39 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM VCC–0.5 P89C668 VLOAD+0.1V 0.2VCC+0.9 0.2VCC–0.1 0.45V VOH–0.1V TIMING REFERENCE POINTS VLOAD VLOAD–0.1V VOL+0.1V NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA. NOTE: AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. SU00717 SU00718 Figure 35. AC Testing Input/Output Figure 36. Float Waveform 70 60 50 89C668 MAXIMUM ACTIVE ICC 40 ICC (mA) TYPICAL ACTIVE ICC 30 20 MAXIMUM IDLE 10 TYPICAL IDLE 2 4 6 8 10 12 14 16 18 20 Frequency at XTAL1 (MHz, 6 clock mode) SU01404 Figure 37. ICC vs. FREQ Valid only within frequency specifications of the device under test 2001 Jul 27 40 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 repeated START condition START or repeated START condition START condition tSU;STA STOP condition tRD 0.7 VCC SDA (INPUT/OUTPUT) 0.3 VCC tBUF tFD tRC tFC tSU;STO 0.7 VCC SCL (INPUT/OUTPUT) 0.3 VCC tSU;DAT3 tHD;STA tLOW tHIGH tSU;DAT1 tHD;DAT tSU;DAT2 SU00107A Figure 38. Timing SI01 (I2C) Interface VCC–0.5 0.45V 0.2VCC+0.9 0.2VCC–0.1 NOTE: AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. SU00010 Figure 39. AC Testing Input/Output VLOAD+0.1V VLOAD VLOAD–0.1V TIMING REFERENCE POINTS VOH–0.1V VOL+0.1V NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA. SU00011 Figure 40. Float Waveform 2001 Jul 27 41 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 VCC VCC ICC ICC VCC VCC 89C668 CLOCK SIGNAL XTAL2 RST VCC EA P0 RST (NC) VCC VCC EA P0 89C668 P1.6 * P1.7 * XTAL1 (NC) CLOCK SIGNAL VSS XTAL2 P1.6 * P1.7 * XTAL1 VSS SU01109 SU01110 Figure 41. ICC Test Condition, Active Mode All other pins are disconnected Figure 42. ICC Test Condition, Idle Mode All other pins are disconnected VCC–0.5 0.5V tCHCL tCHCX tCLCH tCLCX tCLCL SU00266 Figure 43. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCL = tCHCL = 10 ns VCC ICC VCC VCC RST EA P0 89C668 (NC) P1.6 XTAL2 P1.7 XTAL1 * * VSS SU01111 Figure 44. ICC Test Condition, Power Down Mode All other pins are disconnected VCC = 2 V to 5.5 V NOTE: * Ports 1.6 and 1.7 should be connected to VCC through resistors of sufficiently high value such that the sink current into these pins does not exceed the IOL1 specification. 2001 Jul 27 42 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM FLASH EPROM MEMORY CAPABILITIES OF THE PHILIPS 89C51 FLASH-BASED MICROCONTROLLERS GENERAL DESCRIPTION Flash organization The P89C668 Flash memory augments EPROM functionality with in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Chip Erase operation will erase the entire program memory. The Block Erase function can erase any Flash byte block. In-system programming and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user friendly programming interface. The P89C668 contains 64 kbytes of Flash program memory. This memory is organized as 5 separate blocks. The first two blocks are 8 kbytes in size, filling the program memory space from address 0 through 3FFF hex. The final three blocks are 16 kbytes in size and occupy addresses from 4000 through FFFF hex. Figure 45 depicts the Flash memory configurations. The P89C668 Flash reliably stores memory contents even after 1000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The P89C668 uses a +5 V VPP supply to perform the Program/Erase algorithms. Flash Programming and Erasure There are three methods of erasing or programming of the Flash memory that may be used. First, the Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point in the Boot ROM. The end-user application, though, must be executing code from a different block than the block that is being erased or programmed. Second, the on-chip ISP boot loader may be invoked. This ISP boot loader will, in turn, call low-level routines through the same common entry point in the Boot ROM that can be used by the end-user application. Third, the Flash may be programmed or erased using the parallel method by using a commercially available EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51, but it is not identical, and the commercially available programmer will need to have support for these devices. FEATURES – IN-SYSTEM PROGRAMMING (ISP) AND IN-APPLICATION PROGRAMMING (IAP) • Flash EPROM internal program memory with Block Erase. • Internal 1 kbyte fixed boot ROM, containing low-level in-system programming routines and a default serial loader. User program can call these routines to perform In-Application Programming (IAP). The Boot ROM can be turned off to provide access to the full 64 kbyte Flash memory. Boot ROM When the microcontroller programs its own Flash memory, all of the low level details are handled by code that is permanently contained in a 1 kbyte “Boot ROM” that is separate from the Flash memory. A user program simply calls the common entry point with appropriate parameters in the Boot ROM to accomplish the desired operation. Boot ROM operations include things like: erase block, program byte, verify byte, program security lock bit, etc. The Boot ROM overlays the program memory space at the top of the address space from FC00 to FFFF hex, when it is enabled. The Boot ROM may be turned off so that the upper 1 kbytes of Flash program memory are accessible for execution. • Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space. This configuration provides flexibility to the user. • Default loader in Boot ROM allows programming via the serial port without the need for a user provided loader. • Up to 64 kbyte external program memory if the internal program memory is disabled (EA = 0). • Programming and erase voltage +5 V or +12 V. • Read/Programming/Erase using ISP/IAP: – Byte Programming (20 ms). – Typical quick erase times (including preprogramming time): Block Erase (8 kbytes or 16 kbytes) in 10 seconds. Full Erase (64 kbytes) in 20 seconds. • Parallel programming with 87C51 compatible hardware interface to programmer. • In-system programming. • Programmable security for the code in the Flash. • 1000 minimum erase/program cycles for each byte. • 10 year minimum data retention. 2001 Jul 27 P89C668 43 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 FFFF FFFF BOOT ROM FC00 (1k BYTES) BLOCK 4 16k BYTES C000 BLOCK 3 16k BYTES PROGRAM ADDRESS 8000 BLOCK 2 16k BYTES 4000 BLOCK 1 8k BYTES 2000 BLOCK 0 8k BYTES 0000 SU01112 Figure 45. Flash Memory Configurations Power-On Reset Code Execution Hardware Activation of the Boot Loader The P89C668 contains two special Flash registers: the BOOT VECTOR and the STATUS BYTE. At the falling edge of reset, the P89C668 examines the contents of the Status Byte. If the Status Byte is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code. When the Status Byte is set to a value other than zero, the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to 00H. The factory default setting is 0FCH, corresponds to the address 0FC00H for the factory masked-ROM ISP boot loader. A custom boot loader can be written with the Boot Vector set to the custom boot loader. The boot loader can also be executed by holding PSEN LOW, P2.7 high, EA greater than VIH (such as +5 V), and ALE HIGH (or not connected) at the falling edge of RESET. This is the same effect as having a non-zero status byte. This allows an application to be built that will normally execute the end user’s code but can be manually forced into ISP operation. If the factory default setting for the Boot Vector (0FCH) is changed, it will no longer point to the ISP masked-ROM boot loader code. If this happens, the only way it is possible to change the contents of the Boot Vector is through the parallel programming method, provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and Status Byte. NOTE: When erasing the Status Byte or Boot Vector, both bytes are erased at the same time. It is necessary to reprogram the Boot Vector after erasing and updating the Status Byte. 2001 Jul 27 After programming the Flash, the status byte should be programmed to zero in order to allow execution of the user’s application code beginning at address 0000H. 44 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 VCC VPP +12V OR + 5V VCC +5V TxD TxD RxD RxD RST XTAL2 VSS 89C668 XTAL1 P2.7 “1” VSS SU01113 Figure 46. In-System Programming with a Minimum of Pins the record. If there are zero bytes in the record, this field is often set to 0000. The “RR” string indicates the record type. A record type of “00” is a data record. A record type of “01” indicates the end-of-file mark. In this application, additional record types will be added to indicate either commands or data for the ISP facility. The maximum number of data bytes in a record is limited to 16 (decimal). ISP commands are summarized in Table 9. In-System Programming (ISP) The In-System Programming (ISP) is performed without removing the microcontroller from the system. The In-System Programming (ISP) facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89C668 through the serial port. This firmware is provided by Philips and embedded within each P89C668 device. As a record is received by the P89C668, the information in the record is stored internally and a checksum calculation is performed. The operation indicated by the record type is not performed until the entire record has been received. Should an error occur in the checksum, the P89C668 will send an “X” out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record, then the command will be executed. In most cases, successful reception of the record will be indicated by transmitting a “.” character out the serial port (displaying the contents of the internal program memory is an exception). The Philips In-System Programming (ISP) facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins: TxD, RxD, VSS, VCC, and VPP (see Figure 46). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature. The VPP supply should be adequately decoupled and VPP not allowed to exceed datasheet limits. Using the In-System Programming (ISP) In the case of a Data Record (record type 00), an additional check is made. A “.” character will NOT be sent unless the record checksum matched the calculated checksum and all of the bytes in the record were successfully programmed. For a data record, an “X” indicates that the checksum failed to match, and an “R” character indicates that one of the bytes did not properly program. It is necessary to send a type 02 record (specify oscillator frequency) to the P89C668 before programming data. The ISP feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the P89C668 to establish the baud rate. The ISP firmware provides auto-echo of received characters. The ISP facility was designed to that specific crystal frequencies were not required in order to generate baud rates or time the programming pulses. The user thus needs to provide the P89C668 with information required to generate the proper timing. Record type 02 is provided for this purpose. Once baud rate initialization has been performed, the ISP firmware will only accept Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below: WinISP, a software utility to implement ISP programming with a PC, is available on Philips Semiconductors’ web site. In addition, at the web site is a listing of third party commercially available serial and parallel programmers. :NNAAAARRDD..DDCC<crlf> In the Intel Hex record, the “NN” represents the number of data bytes in the record. The P89C668 will accept up to 16 (10H) data bytes. The “AAAA” string represents the address of the first byte in 2001 Jul 27 45 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM Table 9. Intel-Hex Records Used by In-System Programming RECORD TYPE COMMAND/DATA FUNCTION 00 Program Data :nnaaaa00dd....ddcc Where: Nn = number of bytes (hex) in record Aaaa = memory address of first byte in record dd....dd = data bytes cc = checksum Example: :10008000AF5F67F0602703E0322CFA92007780C361 01 End of File (EOF), no operation :xxxxxx01cc Where: xxxxxx = required field, but value is a “don’t care” cc = checksum Example: :00000001FF 02 Specify Oscillator Frequency :01xxxx02ddcc Where: xxxx = required field, but value is a “don’t care” dd = integer oscillator frequency rounded down to nearest MHz cc = checksum Example: :0100000210ED (dd = 10h = 16, used for 16.0–16.9 MHz) 2001 Jul 27 46 P89C668 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM RECORD TYPE 03 P89C668 COMMAND/DATA FUNCTION Miscellaneous Write Functions :nnxxxx03ffssddcc Where: nn = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 03 = Write Function ff = subfunction code ss = selection code dd = data input (as needed) cc = checksum Subfunction Code = 01 (Erase Blocks) ff = 01 ss = block code as shown below: block 0, 0k to 8k, 00H block 1, 8k to 16k, 20H block 2, 16k to 32k, 40H block 3, 32k to 48k, 80H block 4, 48k to 64k, C0H Example: :0200000301C03C erase block 4 Subfunction Code = 04 (Erase Boot Vector and Status Byte) ff = 04 ss = don’t care dd = don’t care Example: :020000030400F7 erase boot vector and status byte Subfunction Code = 05 (Program Security Bits) ff = 05 ss = 00 program security bit 1 (inhibit writing to Flash) 01 program security bit 2 (inhibit Flash verify) 02 program security bit 3 (disable eternal memory) Example: :020000030501F5 program security bit 2 Subfunction Code = 06 (Program Status Byte or Boot Vector) ff = 06 ss = 00 program status byte 01 program boot vector Example: :020000030601F4 program boot vector Subfunction Code = 07 (Full Chip Erase) Erases all blocks, security bits, and sets status and boot vector to default values ff = 07 ss = don’t care dd = don’t care Example: :0100000307F5 full chip erase 04 Display Device Data or Blank Check – Record type 04 causes the contents of the entire Flash array to be sent out the serial port in a formatted display. This display consists of an address and the contents of 16 bytes starting with that address. No display of the device contents will occur if security bit 2 has been programmed. The dumping of the device data to the serial port is terminated by the reception of any character. General Format of Function 04 :05xxxx04sssseeeeffcc Where: 05 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 04 = “Display Device Data or Blank Check” function code ssss = starting address eeee = ending address ff = subfunction 00 = display data 01 = blank check cc = checksum Example: :0500000440004FFF0069 display 4000–4FFF 2001 Jul 27 47 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM RECORD TYPE 05 COMMAND/DATA FUNCTION Miscellaneous Read Functions General Format of Function 05 :02xxxx05ffsscc Where: 02 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 05 = “Miscellaneous Read” function code ffss = subfunction and selection code 0000 = read signature byte – manufacturer id (15H) 0001 = read signature byte – device id # 1 (C2H) 0002 = read signature byte – device id # 2 (P89C668 = 81H) 0700 = read security bits 0701 = read status byte 0702 = read boot vector = checksum cc Example: :020000050001F8 06 read signature byte – device id # 1 Direct Load of Baud Rate General Format of Function 06 :02xxxx06hhllcc Where: 02 = number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 06 = ”Direct Load of Baud Rate” function code hh = high byte of Timer 2 ll = low byte of Timer 2 cc = checksum Example: :02000006F50003 2001 Jul 27 48 P89C668 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 Using the Watchdog Timer (WDT) The P89C668 supports the use of the WDT in IAP. The user specifies that the WDT is to be fed by setting the most significant bit of the function passed in R1 prior to calling PCM_MTP. The WDT function is only supported for Block Erase when using the Quick Block Erase. The Quick Block Erase is specified by performing a Block Erase with register R0 = 0. Requesting a WDT feed during IAP should only be performed in applications that use the WDT since the process of feeding the WDT will start the WDT if the WDT was not running. In Application Programming Method Several In Application Programming (IAP) calls are available for use by an application program to permit selective erasing and programming of Flash sectors. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FFF0H. The oscillator frequency is an integer number rounded down to the nearest megahertz. For example, set R0 to 11 for 11.0592 MHz. Results are returned in the registers. The API calls are shown in Table 10. Table 10. IAP calls IAP CALL PARAMETER PROGRAM DATA BYTE Input Parameters: R0 = osc freq (integer) R1 = 02h R1 = 82h (WDT feed) DPTR = address of byte to program ACC = byte to program Return Parameter ACC = 00 if pass, !00 if fail ERASE BLOCK Input Parameters: R0 = osc freq (integer) R0 = 0 (Quick Erase) R1 = 01h R1 = 81h (WDT feed) DPH = block code as shown below: block 0, 0k to 8k, 00H block 1, 8k to 16k, 20H block 2, 16k to 32k, 40H block 3, 32k to 48k, 80H block 4, 48k to 64k, C0H DPL = 00h Return Parameter none ERASE BOOT VECTOR Input Parameters: R0 = osc freq (integer) R1 = 04h R1 = 84h (WDT feed) DPH = 00h DPL = don’t care Return Parameter none PROGRAM SECURITY BIT Input Parameters: R0 = osc freq (integer) R1 = 05h R1 = 85h (WDT feed) DPH = 00h DPL = 00h – security bit # 1 (inhibit writing to Flash) 01h – security bit # 2 (inhibit Flash verify) 02h – security bit # 3 (disable external memory) Return Parameter none PROGRAM STATUS BYTE Input Parameters: R0 = osc freq (integer) R1 = 06h R1 = 86h (WDT feed) DPH = 00h DPL = 00h – program status byte ACC = status byte Return Parameter ACC = status byte 2001 Jul 27 49 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM IAP CALL P89C668 PARAMETER PROGRAM BOOT VECTOR Input Parameters: R0 = osc freq (integer) R1 = 06h R1 = 86h (WDT feed) DPH = 00h DPL = 01h – program boot vector ACC = boot vector Return Parameter ACC = boot vector READ DEVICE DATA Input Parameters: R1 = 03h R1 = 83h (WDT feed) DPTR = address of byte to read Return Parameter ACC = value of byte read READ MANUFACTURER ID Input Parameters: R0 = osc freq (integer) R1 = 00h R1 = 80h (WDT feed) DPH = 00h DPL = 00h (manufacturer ID) Return Parameter ACC = value of byte read READ DEVICE ID # 1 Input Parameters: R0 = osc freq (integer) R1 = 00h R1 = 80h (WDT feed) DPH = 00h DPL = 01h (device ID # 1) Return Parameter ACC = value of byte read READ DEVICE ID # 2 Input Parameters: R0 = osc freq (integer) R1 = 00h R1 = 80h (WDT feed) DPH = 00h DPL = 02h (device ID # 2) Return Parameter ACC = value of byte read READ SECURITY BITS Input Parameters: R0 = osc freq (integer) R1 = 07h R1 = 87h (WDT feed) DPH = 00h DPL = 00h (security bits) Return Parameter ACC = value of byte read READ STATUS BYTE Input Parameters: R0 = osc freq (integer) R1 = 07h R1 = 87h (WDT feed) DPH = 00h DPL = 01h (status byte) Return Parameter ACC = value of byte read READ BOOT VECTOR Input Parameters: R0 = osc freq (integer) R1 = 07h R1 = 87h (WDT feed) DPH = 00h DPL = 02h (boot vector) Return Parameter ACC = value of byte read 2001 Jul 27 50 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 Security The security feature protects against software piracy and prevents the contents of the Flash from being read. The Security Lock bits are located in Flash. The P89C668 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 11). Table 11. SECURITY LOCK BITS1 PROTECTION DESCRIPTION Level LB1 LB2 LB3 1 0 0 0 MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. 2 1 0 0 Same as level 1, plus block erase is disabled. Erase or programming of the status byte or boot vector is disabled. 3 1 1 0 Same as level 2, plus verify of code memory is disabled. 4 1 1 1 Same as level 3, plus external execution is disabled. NOTE: 1. Security bits are independent of each other. Full-chip erase may be performed regardless of the state of the security bits. 2. All other combination of lockbits is undefined. 3. Setting LBx doesn’t prevent programming of unprogrammed bits. 2001 Jul 27 51 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM PLCC44: plastic leaded chip carrier; 44 leads 2001 Jul 27 P89C668 SOT187-2 52 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm 2001 Jul 27 53 P89C668 SOT389-1 Philips Semiconductors Preliminary data 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM P89C668 Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued datasheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 07-01 Document order number: 2001 Jul 27 54 9397 750 08651