CY62187EV30 MoBL® 64-Mbit (4 M × 16) Static RAM 64-Mbit (4 M × 16) Static RAM Features Functional Description ■ Very high speed ❐ 55 ns ■ Wide voltage range ❐ 2.2 V to 3.7 V ■ Ultra low standby power ❐ Typical standby current: 8 A ❐ Maximum standby current: 48 A ■ Ultra low active power ❐ Typical active current: 7.5 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2, and OE features ■ Automatic power down when deselected The CY62187EV30 is a high performance CMOS static RAM organized as 4 M words by 16-bits. This device features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99 percent when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). ■ CMOS for optimum speed and power ■ Available in Pb-free 48-ball FBGA package To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A21). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A21). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 9 for a complete description of read and write modes. For a complete list of related documentation, click here. Cypress Semiconductor Corporation Document Number: 001-48998 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 27, 2015 CY62187EV30 MoBL® Logic Block Diagram 4096K × 16 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA-IN DRIVERS I/O0–I/O7 I/O8–I/O15 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 COLUMN DECODER BHE WE OE CE2 CE1 BLE Power down Circuit Document Number: 001-48998 Rev. *K Page 2 of 19 CY62187EV30 MoBL® Contents Pin Configuration ............................................................. 4 Product Portfolio .............................................................. 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Data Retention Characteristics ....................................... 7 Data Retention Waveform ................................................ 7 Switching Characteristics ................................................ 8 Switching Waveforms ...................................................... 9 Truth Table ...................................................................... 12 Document Number: 001-48998 Rev. *K Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagram ............................................................ 14 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC® Solutions ...................................................... 19 Cypress Developer Community ................................. 19 Technical Support ..................................................... 19 Page 3 of 19 CY62187EV30 MoBL® Pin Configuration Figure 1. 48-ball FBGA pinout 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 A21 A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 A20 H Product Portfolio Power Dissipation Product Speed (ns) VCC Range (V) Operating ICC (mA) f = 1 MHz CY62187EV30LL Min Typ[1] Max 2.2 3.0 3.7 55 Standby ISB2 (A) f = fMax Typ[1] Max Typ[1] Max Typ[1] Max 7.5 9 45 55 8 48 Note 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document Number: 001-48998 Rev. *K Page 4 of 19 CY62187EV30 MoBL® DC Input Voltage [2, 3] ................. –0.3 V to VCC (max) + 0.3 V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) ......................... > 2001 V Latch Up Current .................................................... > 200 mA Operating Range Supply Voltage to Ground Potential ....................................... –0.3 V to VCC(max) + 0.3 V Device DC Voltage Applied to Outputs in High Z State [2, 3] ...................... –0.3 V to VCC(max) + 0.3 V CY62187EV30LL Range Ambient Temperature VCC[4] Industrial –40 °C to +85 °C 2.2 V to 3.7 V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 55 ns Unit Min Typ [5] Max – V VOH Output HIGH voltage 2.2 V < VCC < 2.7 V IOH = –0.1 mA 2.0 – 2.7 V < VCC < 3.7 V IOH = –1.0 mA 2.4 – – V VOL Output LOW voltage 2.2 V < VCC < 2.7 V IOL = 0.1 mA – – 0.4 V 2.7 V < VCC < 3.7 V IOL = 2.1 mA – – 0.4 V 1.8 – VCC + 0.3 V V VIH Input HIGH voltage VIL Input LOW voltage 2.2 V < VCC < 2.7 V 2.7 V < VCC < 3.7 V 2.2 – VCC + 0.3 V V 2.2 V< VCC < 2.7 V –0.3 – 0.6 V –0.3 – 0.8[6] V –1 – +1 A 2.7 V < VCC < 3.7 V IIX Input leakage current GND < VI < VCC IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 A ICC VCC operating supply current f = fMax = 1/tRC VCC = VCC(max) IOUT = 0 mA CMOS levels – 45 55 mA – 7.5 9 mA CE1 > VCC – 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.7 V – 8 48 A f = 1 MHz ISB2 [7] Automatic CE power down current — CMOS inputs Notes 2. VIL(min) = –2.0V for pulse durations less than 20 ns. 3. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 4. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 6. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions input LOW Voltage applied to the device must not be higher than 0.7 V. 7. Chip enables (CE1 and CE2), Address Pins A20, A21 and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 001-48998 Rev. *K Page 5 of 19 CY62187EV30 MoBL® Capacitance Parameter [8] Description CIN Input capacitance COUT Output capacitance Test Conditions Max Unit 25 pF 35 pF Test Conditions FBGA Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 42.35 C/W 6.25 C/W TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance Parameter [8] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE Figure 2. AC Test Loads and Waveforms ALL INPUT PULSES VCC 90% 90% 10% 10% GND Fall Time = 1 V/ns R2 Rise Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT OUTPUT RTH V Table 1. AC Test Loads Parameter 2.5 V 3.3 V Unit R1 16667 1103 R2 15385 1554 RTH 8000 645 VTH 1.20 1.75 V Note 8. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-48998 Rev. *K Page 6 of 19 CY62187EV30 MoBL® Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for data retention ICCDR [10] Data retention current tCDR[11] tR[12] Conditions Min Typ [9] Max Unit 1.5 – – V – – 48 A Chip deselect to data retention time 0 – – ns Operation recovery time 55 – – ns VCC = 1.5 V, CE1 > VCC – 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Data Retention Waveform VCC Figure 3. Data Retention Waveform [13] DATA RETENTION MODE VCC(min) VDR > 1.5 V tCDR VCC(min) tR CE1 or BHE.BLE or CE2 Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 10. Chip enables (CE1 and CE2), Address Pins A20, A21 and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 13. BHE.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document Number: 001-48998 Rev. *K Page 7 of 19 CY62187EV30 MoBL® Switching Characteristics Over the Operating Range Parameter [14, 15] Description 55 ns Min Max Unit Read Cycle tRC Read cycle time 55 – ns tAA Address to data valid – 55 ns tOHA Data hold from address change 6 – ns tACE CE1 LOW and CE2 HIGH to data valid – 55 ns tDOE OE LOW to data valid – 25 ns tLZOE OE LOW to LOW Z[16] 5 – ns – 20 ns tHZOE OE HIGH to high Z[16, 17] Z[16] tLZCE CE1 LOW and CE2 HIGH to low 10 – ns tHZCE CE1 HIGH and CE2 LOW to high Z[16, 17] – 20 ns tPU CE1 LOW and CE2 HIGH to power up 0 – ns tPD CE1 HIGH and CE2 LOW to power down – 55 ns tDBE BLE/BHE LOW to data valid – 55 ns tLZBE BLE/BHE LOW to low Z [16] 10 – ns tHZBE BLE/BHE HIGH to high Z [16, 17] – 20 ns Write Cycle [18, 19] tWC Write cycle time 55 – ns tSCE CE1 LOW and CE2 HIGH to write end 45 – ns tAW Address setup to write end 45 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 40 – ns tBW BLE/BHE LOW to write end 45 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns tHZWE WE LOW to high Z[16, 17] – 20 ns tLZWE WE HIGH to low Z[16] 10 – ns Notes 14. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable signals as described in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer applicable. It is available for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production. 15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of VTH, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 2 on page 6. 16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 18. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 19. The minimum write cycle pulse width for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of tSD and tHZWE. Document Number: 001-48998 Rev. *K Page 8 of 19 CY62187EV30 MoBL® Switching Waveforms Figure 4. Read Cycle 1 (Address Transition Controlled) [20, 21] tRC ADDRESS tOHA DATA I/O tAA PREVIOUS DATA VALID DATA OUT VALID Figure 5. Read Cycle 2 (OE Controlled) [21, 22] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tLZBE tDBE tHZBE OE tHZOE tDOE DATA I/O tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT VALID tLZCE VCC SUPPLY CURRENT tPU ICC 50% 50% ISB Notes 20. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 21. WE is HIGH for read cycle. 22. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document Number: 001-48998 Rev. *K Page 9 of 19 CY62187EV30 MoBL® Switching Waveforms (continued) Figure 6. Write Cycle 1 (WE Controlled) [23, 24, 25, 26] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATA IN VALID NOTE 26 tHZOE Figure 7. Write Cycle 2 (CE1 or CE2 Controlled) [23, 24, 25, 26] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATA IN VALID NOTE 26 tHZOE Notes 23. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 24. Data I/O is high impedance if OE = VIH. 25. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 26. During this period the I/Os are in output state and input signals should not be applied. Document Number: 001-48998 Rev. *K Page 10 of 19 CY62187EV30 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle 3 (WE Controlled, OE LOW) [27, 28, 29] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tHA tSA WE tPWE tSD DATA I/O NOTE 28 tHD DATA IN VALID tLZWE tHZWE Figure 9. Write Cycle 4 (BHE/BLE Controlled, OE LOW) [27, 28] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O NOTE 28 tHD DATA IN VALID Notes 27. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 28. During this period the I/Os are in output state and input signals should not be applied. 29. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. Document Number: 001-48998 Rev. *K Page 11 of 19 CY62187EV30 MoBL® Truth Table CE1 H CE2 [30] X X[30] WE X OE X BHE BLE [30] [30] [30] X [30] Power High Z Deselect/Power Down Standby (ISB) High Z Deselect/Power Down Standby (ISB) Deselect/Power Down Standby (ISB) L X X X X H H High Z L H H L L L Data Out (I/O0–I/O15) Read Active (ICC) L H H L H L High Z (I/O8–I/O15); Data Out (I/O0–I/O7) Read Active (ICC) L H H L L H Data Out (I/O8–I/O15); High Z (I/O0–I/O7) Read Active (ICC) L H L X L L Data In (I/O0–I/O15) Write Active (ICC) L H L X H L High Z (I/O8–I/O15); Data In (I/O0–I/O7) Write Active (ICC) L H L X L H Data In (I/O8–I/O15); High Z (I/O0–I/O7) Write Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L L High Z Output Disabled Active (ICC) X X X Mode [30] [30] X X Inputs Outputs Note 30. The ‘X’ (Don’t care) state for the chip enables and byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document Number: 001-48998 Rev. *K Page 12 of 19 CY62187EV30 MoBL® Ordering Information Speed (ns) 55 Ordering Code CY62187EV30LL-55BAXI Package Diagram Package Type 001-50044 48-ball FBGA (8 × 9.5 × 1.4 mm) Pb-free Operating Range Industrial Ordering Code Definitions CY 621 8 7 E V30 LL - 55 BA X I Temperature Grade: I = Industrial X = Pb-free Package Type: BA = 48-ball FBGA Speed Grade: 55 ns Low Power Voltage Range: V30 = 3 V (typical) Process Technology: E = 90 nm Bus Width = × 16 Density = 64-Mbit Family Code: 621 = MoBL SRAM family Company ID: CY = Cypress Document Number: 001-48998 Rev. *K Page 13 of 19 CY62187EV30 MoBL® Package Diagram Figure 10. 48-ball FBGA (8 × 9.5 × 1.4 mm) BK48L Package Outline, 001-50044 001-50044 *D Document Number: 001-48998 Rev. *K Page 14 of 19 CY62187EV30 MoBL® Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable CMOS Complementary Metal Oxide Semiconductor CE Chip Enable FBGA Fine-Pitch Ball Grid Array mA milliampere I/O Input/Output ms millisecond OE Output Enable ns nanosecond SRAM Static Random Access Memory ohms WE Write Enable % percent pF picofarad V volt W watt Document Number: 001-48998 Rev. *K Symbol Unit of Measure °C degree Celsius MHz megahertz µA microampere Page 15 of 19 CY62187EV30 MoBL® Document History Page Document Title: CY62187EV30 MoBL®, 64-Mbit (4 M × 16) Static RAM Document Number: 001-48998 Revision ECN Orig. of Change Submission Date ** 2595932 VKN / PYRS 10/24/08 New data sheet. *A 2644442 VKN / PYRS 01/23/09 Updated Package Diagram. *B 2672650 VKN / PYRS 03/12/09 Added 55 ns speed bin related information in all instances across the document. Updated Product Portfolio: Changed maximum value in VCC range from 3.6 V to 3.7 V. Changed typical value of “Operating ICC” from 2.5 mA to 3.5 mA at f = 1 MHz corresponding to 70 ns speed bin. Changed maximum value of “Operating ICC” from 4 mA to 6 mA at f = 1 MHz corresponding to 70 ns speed bin. Changed typical value of “Operating ICC” form 33 mA to 28 mA at f = fMAX corresponding to 70 ns speed bin. Changed maximum value of “Operating ICC” from 40 mA to 45 mA at f = fMAX corresponding to 70 ns speed bin. Updated Electrical Characteristics: Changed typical value of ICC parameter from 33 mA to 28 mA at f = fMAX corresponding to 70 ns speed bin. Changed maximum value of ICC parameter from 40 mA to 45 mA at f = fMAX corresponding to 70 ns speed bin. Changed typical value of ICC parameter from 2.5 mA to 3.5 mA at f = 1 MHz corresponding to 70 ns speed bin. Changed maximum value of ICC parameter from 4 mA to 6 mA at f = 1 MHz corresponding to 70 ns speed bin. Updated Note 7. Updated Switching Characteristics: Changed minimum value of tPWE parameter from 45 ns to 50 ns corresponding to 70 ns speed bin. Changed minimum value of tSD parameter from 30 ns to 35 ns corresponding to 70 ns speed bin. Updated Package Diagram: Changed 48-ball FBGA package dimensions from “8 × 9.5 × 1.6 mm” to “8 × 9.5 × 1.4 mm”. spec 001-50044 – Changed revision from ** to *A. *C 2737164 VKN / AESA 07/13/09 Changed status from Preliminary to Final. Updated Product Portfolio: Changed typical value of “Operating ICC” from 3.5 mA to 4 mA at f = 1 MHz corresponding to 55 ns and 70 ns speed bins. Changed typical value of “Operating ICC” from 35 mA to 45 mA at f = fmax corresponding to 55 ns speed bin. Changed typical value of “Operating ICC” from 28 mA to 35 mA at f = fmax corresponding to 70 ns speed bin. Document Number: 001-48998 Rev. *K Description of Change Page 16 of 19 CY62187EV30 MoBL® Document History Page (continued) Document Title: CY62187EV30 MoBL®, 64-Mbit (4 M × 16) Static RAM Document Number: 001-48998 Revision ECN Orig. of Change Submission Date Description of Change *C (cont.) 2737164 VKN / AESA 07/13/09 Updated Electrical Characteristics: Updated details in “Test Conditions” column of VOH, VOL, VIH, VIL parameters (Included VCC range). Changed maximum value of VIL parameter from 0.8 V to 0.7 V corresponding to Test Condition “VCC = 2.7 V to 3.7 V”. Changed typical value of ICC parameter from 35 mA to 45 mA at f = fmax corresponding to 55 ns speed bin. Changed typical value of ICC parameter from 28 mA to 35 mA at f = fmax corresponding to 70 ns speed bin. Changed typical value of ICC parameter from 3.5 mA to 4 mA at f = 1 MHz corresponding to 55 ns and 70 ns speed bins. Updated Capacitance: Changed maximum value of CIN parameter from 20 pF to 25 pF. Changed maximum value of COUT parameter from 20 pF to 35 pF. Updated Thermal Resistance: Replaced TBD with values for 48-ball FBGA package. Updated AC Test Loads and Waveforms: Updated Table 1: Included VCC range for VTH parameter. Updated Switching Characteristics: Changed minimum value of tLZBE parameter from 5 ns to 10 ns. Updated Truth Table: Added Note 30 and referred the same note in “X” in “CE1” and “CE2” columns. *D 2765892 VKN 09/18/09 Removed 70 ns speed bin related information in all instances across the document. Updated Product Portfolio: Changed maximum value of “Operating ICC” from 6 mA to 9 mA at f = 1 MHz corresponding to 55 ns speed bin. Updated Electrical Characteristics: Changed typical value of ICC parameter from 4 mA to 7.5 mA at f = 1 MHz corresponding to 55 ns speed bin. Changed maximum value of ICC parameter from 6 mA to 9 mA at f = 1 MHz corresponding to 55 ns speed bin. *E 3177000 AJU 02/18/2011 Updated Features: Changed value of “Typical Active Current” from 4 mA to 7.5 mA. Updated Pin Configuration: Fixed typo in Figure 1 (Renamed “48-Ball VFBGA” as “48-ball FBGA”). Updated Product Portfolio: Changed typical value of “Operating ICC” from 4 mA to 7.5 mA at f = 1 MHz corresponding to 55 ns speed bin. Updated Electrical Characteristics: Updated details in “Test Conditions” column of ISB2 parameter (Included BHE and BLE to reflect Byte power down feature). Updated AC Test Loads and Waveforms: Updated Table 1. Updated Data Retention Characteristics: Updated details in “Test Conditions” column of ICCDR parameter (Included BHE and BLE to reflect Byte power down feature). Changed minimum value of tR parameter from tRC to 55 ns. Added Ordering Code Definitions under Ordering Information. Updated Package Diagram. Added Acronyms and Units of Measure. Changed all instances of IO to I/O. Updated to new template. Document Number: 001-48998 Rev. *K Page 17 of 19 CY62187EV30 MoBL® Document History Page (continued) Document Title: CY62187EV30 MoBL®, 64-Mbit (4 M × 16) Static RAM Document Number: 001-48998 Revision ECN Orig. of Change Submission Date Description of Change *F 3282088 RAME 06/14/2011 Updated Functional Description: Removed the note “For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com website” and its reference. Updated Electrical Characteristics: Changed maximum value of VIL parameter corresponding to Test Condition “2.7 V < VCC < 3.7 V” from 0.7 V to 0.8 V. Added Note 6 and referred the same note in maximum value of VIL parameter. Updated to new template. *G 3785005 TAVA 10/18/2012 Minor text edits. Updated Package Diagram: spec 001-50044 – Changed revision from *C to *D. *H 4101127 VINI 08/21/2013 Updated Switching Characteristics: Added Note 14 and referred the same note in “Parameter” column. Updated to new template. Completing Sunset Review. *I 4114808 NILE 09/12/2013 Updated Electrical Characteristics: Updated Note 7. Updated Data Retention Characteristics: Updated Note 10. *J 4576478 NILE 11/21/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Switching Characteristics: Added Note 19 and referred the same note in “Write Cycle”. Updated Switching Waveforms: Added Note 29 and referred the same note in Figure 8. *K 4990839 VINI 10/27/2015 Updated Thermal Resistance: Replaced “2-layer” with “four-layer” in “Test Conditions” column. Changed value of JA parameter corresponding to FBGA package from 59.06 C/W to 42.35 C/W. Changed value of JC parameter corresponding to FBGA package from 14.08 C/W to 6.25 C/W. Updated to new template. Completing Sunset Review. Document Number: 001-48998 Rev. *K Page 18 of 19 CY62187EV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2015. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-48998 Rev. *K Revised October 27, 2015 Page 19 of 19 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.