CY7C1019D 1-Mbit (128 K × 8) Static RAM 1-Mbit (128 K × 8) Static RAM Features Functional Description The CY7C1019D [1] is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. The eight input and output pins (IO0 through IO7) are placed in a high-impedance state when: ■ Pin- and function-compatible with CY7C1019B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA @ 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA ■ 2.0 V Data retention ■ Automatic power-down when deselected ■ CMOS for optimum speed/power ■ Center power/ground pinout ■ Easy memory expansion with CE and OE options ■ Functionally equivalent to CY7C1019B ■ Available in Pb-free 32-pin 400-Mil wide Molded SOJ and 32-pin TSOP II packages ■ Deselected (CE HIGH) ■ Outputs are disabled (OE HIGH) ■ When the write operation is active (CE LOW, and WE LOW). Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A16). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the IO pins. The CY7C1019D device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. For a complete list of related documentation, click here. Logic Block Diagram IO0 INPUT BUFFER ROW DECODER SENSE AMPS IO1 A0 A1 A2 A3 A4 A5 A6 A7 A8 128K x 8 ARRAY IO2 IO3 IO4 IO5 IO6 CE COLUMN DECODER WE IO7 A9 A10 A11 A12 A13 A14 A15 A16 OE POWER DOWN Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document Number: 38-05464 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 26, 2014 CY7C1019D Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05464 Rev. *J Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY7C1019D Pin Configuration Figure 1. 32-pin SOJ / TSOP II pinout (Top View) A0 A1 A2 A3 CE IO 0 IO 1 VCC V SS IO 2 IO 3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE IO 7 IO 6 VSS VCC IO 5 IO 4 A12 A11 A10 A9 A8 Selection Guide Description -10 (Industrial) Unit Maximum Access Time 10 ns Maximum Operating Current 80 mA Maximum Standby Current 3 mA Document Number: 38-05464 Rev. *J Page 3 of 16 CY7C1019D DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Storage Temperature ............................... –65 C to +150 C Latch-up Current .................................................... > 200 mA Ambient Temperature with Power Applied ......................................... –55 C to +125 C Operating Range Supply Voltage on VCC to Relative GND [2] ...............................–0.5 V to +6.0 V DC Voltage Applied to Outputs in High Z State [2] ................................ –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Speed Industrial –40 C to +85 C 5 V 0.5 V 10 ns Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage -10 (Industrial) Test Conditions IOH = –4.0 mA IOH = –0.1 mA Min Max 2.4 – – IOL = 8.0 mA 3.4 Unit V [3] VOL Output LOW Voltage – 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.5 V VIL Input LOW Voltage [2] –0.5 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 A IOZ Output Leakage Current GND < VI < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC –1 +1 A 100 MHz – 80 mA 83 MHz – 72 mA 66 MHz – 58 mA 40 MHz – 37 mA ISB1 Automatic CE Power-Down Current – TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax – 10 mA ISB2 Automatic CE Power-Down Current – CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 3 mA Note 2. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. 3. Please note that the maximum VOH limit doesnot exceed minimum CMOS VIH of 3.5V. If you are interfacing this SRAM with 5 V legacy processors that require a minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider. Document Number: 38-05464 Rev. *J Page 4 of 16 CY7C1019D Capacitance Parameter [4] Description CIN Input capacitance COUT Output capacitance Test Conditions Max Unit 6 pF 8 pF 400-Mil Wide SOJ TSOP II Unit 56.29 62.22 C/W 38.14 21.43 C/W TA = 25 C, f = 1 MHz, VCC = 5.0 V Thermal Resistance Parameter [4] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [5] ALL INPUT PULSES 3.0 V Z = 50 90% OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* 90% 10% 10% GND 1.5V Rise Time: 3 ns (a) (b) Fall Time: 3 ns High Z characteristics: R1 480 5V OUTPUT INCLUDING JIG AND SCOPE R2 255 5 pF (c) Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 2 (c). Document Number: 38-05464 Rev. *J Page 5 of 16 CY7C1019D Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [6] Chip Deselect to Data Retention Time tR [7] Operation Recovery Time VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Min Max Unit 2.0 – V – 3 mA 0 – ns tRC – ns Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 4.5 V VDR > 2 V tCDR 4.5 V tR CE Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. Document Number: 38-05464 Rev. *J Page 6 of 16 CY7C1019D Switching Characteristics Over the Operating Range Parameter [8] Description -10 (Industrial) Min Max Unit Read Cycle tpower [9] VCC(typical) to the first access 100 – s tRC Read Cycle Time 10 – ns tAA Address to Data Valid – 10 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 10 ns tDOE OE LOW to Data Valid – 5 ns tLZOE OE LOW to Low Z 0 – ns – 5 ns 3 – ns – 5 ns [10, 11] tHZOE OE HIGH to High Z tLZCE CE LOW to Low Z [11] tHZCE CE HIGH to High Z [10, 11] tPU [12] CE LOW to Power-Up 0 – ns tPD [12] CE HIGH to Power-Down – 10 ns Write Cycle [13, 14] tWC Write Cycle Time 10 – ns tSCE CE LOW to Write End 7 – ns tAW Address Set-Up to Write End 7 – ns tHA Address Hold from Write End 0 – ns tSA Address Set-Up to Write Start 0 – ns tPWE WE Pulse Width 7 – ns tSD Data Set-Up to Write End 6 – ns tHD Data Hold from Write End 0 – ns WE HIGH to Low Z [11] 3 – ns WE LOW to High Z [10, 11] – 5 ns tLZWE tHZWE Notes 8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 9. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 10. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of Figure 2 on page 5. Transition is measured when the outputs enter a high impedance state. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. This parameter is guaranteed by design and is not tested. 13. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 14. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05464 Rev. *J Page 7 of 16 CY7C1019D Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [15, 16] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [16, 17] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes 15. Device is continuously selected. OE, CE = VIL. 16. WE is HIGH for Read cycle. 17. Address valid prior to or coincident with CE transition LOW.. Document Number: 38-05464 Rev. *J Page 8 of 16 CY7C1019D Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled) [18, 19] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA IO tHD DATA VALID Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [18, 19] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA IO tHD DATAIN VALID NOTE 20 tHZOE Notes 18. Data IO is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 20. During this period the IOs are in the output state and input signals should not be applied. Document Number: 38-05464 Rev. *J Page 9 of 16 CY7C1019D Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [21, 22] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA IO NOTE 23 tHD DATA VALID tHZWE tLZWE Notes 21. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 22. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 23. During this period the IOs are in the output state and input signals should not be applied. Document Number: 38-05464 Rev. *J Page 10 of 16 CY7C1019D Truth Table CE OE WE IO0–IO7 Mode Power H X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Package Diagram Ordering Code Package Type CY7C1019D-10VXI 51-85033 32-pin SOJ (400 Mils) Pb-free CY7C1019D-10ZSXI 51-85095 32-pin TSOP (Type II) Pb-free Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 01 9 D - 10 XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = V or ZS V = 32-pin Molded SOJ ZS = 32-pin TSOP Type II Speed: 10 ns Process Technology: D = C9, 90 nm Technology Data Width: 9 = × 8-bits Density: 01 = 1-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05464 Rev. *J Page 11 of 16 CY7C1019D Package Diagrams Figure 9. 32-pin SOJ (400 Mils) V32.4 (Molded SOJ V33) Package Outline, 51-85033 51-85033 *E Document Number: 38-05464 Rev. *J Page 12 of 16 CY7C1019D Package Diagrams (continued) Figure 10. 32-pin TSOP Type II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095 51-85095 *B Document Number: 38-05464 Rev. *J Page 13 of 16 CY7C1019D Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SOJ Small Outline J-lead µs microsecond SRAM Static Random Access Memory mA milliampere TSOP Thin Small Outline Package ms millisecond TTL Transistor-Transistor Logic mm millimeter WE Write Enable ns nanosecond ohm % percent pF picofarad V volt W watt Document Number: 38-05464 Rev. *J Symbol Unit of Measure Page 14 of 16 CY7C1019D Document History Page Document Title: CY7C1019D, 1-Mbit (128 K × 8) Static RAM Document Number: 38-05464 Rev. ECN No. Issue Date Orig. of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233715 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165) Pb-free offering in the Ordering Information *B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table Added Data Retention Characteristics table and waveforms Shaded Ordering Information *C 307598 See ECN RKF Reduced Speed bins to -10 and -12 ns *D 520647 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2 *E 802877 See ECN VKN Changed ICC spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz *F 3110052 12/14/2010 AJU Added Ordering Code Definitions. Updated Package Diagrams. *G 3245896 05/02/2011 PRAS Updated Package Diagrams. Added Acronyms and Units of Measure. Updated in new template. *H 4038234 06/24/2013 MEMJ Updated Functional Description. Updated Electrical Characteristics: Added one more Test Condition “IOH = –0.1 mA” for VOH parameter and added maximum value corresponding to that Test Condition. Added Note 3 and referred the same note in maximum value for VOH parameter corresponding to Test Condition “IOH = –0.1 mA”. Updated in new template. *I 4385827 05/21/2014 MEMJ Updated Package Diagrams: spec 51-85033 – Changed revision from *D to *E. Completing Sunset Review. *J 4579569 11/26/2014 MEMJ Added related documentation hyperlink in page 1. Document Number: 38-05464 Rev. *J Description of Change Page 15 of 16 CY7C1019D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05464 Rev. *J Revised November 26, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16