CY7C1020CV33 512 K (32 K × 16) Static RAM 512 K (32 K × 16) Static RAM Features Functional Description ■ Pin- and function-compatible with CY7C1020CV33 ■ Temperature Ranges ❐ Commercial: 0 °C to 70 °C ❐ Industrial: –40 °C to 85 °C ❐ Automotive: –40 °C to 125 °C The CY7C1020CV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). ■ High speed ❐ tAA = 10 ns ■ CMOS for optimum speed/power ■ Low active power ❐ 325 mW (max) ■ Automatic power-down when deselected ■ Independent control of upper and lower bits ■ Available in Pb-free and non Pb-free 44-pin TSOP II package Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020CV33 is available in standard 44-pin TSOP Type II package. For a complete list of related resources, click here. Logic Block Diagram 32K × 16 RAM Array SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O1–I/O8 I/O9–I/O16 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 BHE WE CE OE BLE Cypress Semiconductor Corporation Document Number: 38-05133 Rev. *L • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 5, 2015 CY7C1020CV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Document Number: 38-05133 Rev. *L Package Diagrams .......................................................... 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC® Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17 Page 2 of 17 CY7C1020CV33 Selection Guide Description -10 -12 -15 Unit 10 12 15 ns Commercial/Industrial 90 85 80 mA Automotive – – 85 mA Commercial/Industrial 5 5 5 mA Automotive – – 10 mA Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Pin Configuration Figure 1. 44-pin TSOP Type II pinout (Top View) [1] TSOP II Top View NC A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A4 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC Note 1. NC pins are not connected on the die. Document Number: 38-05133 Rev. *L Page 3 of 17 CY7C1020CV33 Pin Definitions Pin Name Pin Number I/O Type A0–A14 5, 4, 3, 2, 18, 44, 43, 42, 27, 26, 25, 24, 21, 20, 19 Input I/O1–I/O16 7–10, 13–16, 29–32, 35–38 Description Address Inputs used to select one of the address locations. Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation. NC 1, 22, 23, 28 WE 17 Input/Control Write Enable Input, active LOW. When selected LOW, a Write is conducted. When deselected HIGH, a Read is conducted. CE 6 Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. BHE, BLE 40, 39 Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O16–I/O9, BLE controls I/O8–I/O1. OE 41 VSS 12, 34 VCC 11, 33 Document Number: 38-05133 Rev. *L No Connect No Connects. Not connected to the die. Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system. Power Supply Power Supply inputs to the device. Page 4 of 17 CY7C1020CV33 Maximum Ratings Current into outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied .......................................... –55 C to +125 C Static discharge voltage (per MIL-STD-883, method 3015) .......................... > 2001 V Latch-up current .................................................... > 200 mA Operating Range Range Supply voltage on VCC to relative GND [2] ................................–0.5 V to +4.6 V Ambient Temperature VCC 0 C to +70 C 3.3 V 10% Industrial –40 C to +85 C 3.3 V 10% Automotive –40 C to +125 C 3.3 V 10% Commercial DC voltage applied to outputs in high Z State [2] ................................ –0.5 V to VCC + 0.5 V DC input voltage [2] ............................. –0.5 V to VCC + 0.5 V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA VOL Output LOW voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH voltage -10 -12 Max Min Max Min Max 2.4 – 2.4 – 2.4 – V – 0.4 – 0.4 – 0.4 V 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 [2] 0.3 Input LOW voltage IIX Input leakage current GND < VI < VCC – – IOZ Output leakage current GND < VI < VCC, Commercial 1 Output Disabled / Industrial +1 ICC VCC operating supply current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC ISB1 Automatic CE power-down Max VCC, current – TTL Inputs CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Commercial 1 / Industrial Automotive Unit Min VIL ISB2 -15 V 0.8 –0.3 0.8 –0.3 0.8 V +1 –1 +1 –1 +1 A – – –20 +20 A –1 +1 –1 +1 A Automotive – – – – –20 +20 A Commercial / Industrial – 90 – 85 – 80 mA Automotive – – – – – 85 mA Commercial / Industrial – 15 – 15 – 15 mA Automotive – – – – – 20 mA – 5 – 5 – 5 mA – – – – – 10 mA Commercial Automatic CE power-down Max VCC, current – CMOS inputs CE > VCC – 0.3 V, / Industrial VIN > VCC – 0.3 V, Automotive or VIN < 0.3 V, f=0 Note 2. VIL(min) = –2.0 V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns. Document Number: 38-05133 Rev. *L Page 5 of 17 CY7C1020CV33 Capacitance Parameter [3] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max Unit 8 pF 8 pF Thermal Resistance Parameter [3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 44-pin TSOP-II Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 76.92 C/W 15.86 C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [4] ALL INPUT PULSES R 317 3.3 V 3.0 V OUTPUT R2 351 30 pF (a) GND 90% 90% 10% 10% High Z characteristics: R 317 3.3 V OUTPUT 5 pF Rise Time: 1 V/ns (b) Fall Time: 1 V/ns R2 351 (c) Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. Document Number: 38-05133 Rev. *L Page 6 of 17 CY7C1020CV33 Switching Characteristics Over the Operating Range Parameter [5] Description -10 -12 -15 Min Max Min Max Min Max Unit Read Cycle tRC Read cycle time 10 – 12 – 15 – ns tAA Address to data valid – 10 – 12 – 15 ns tOHA Data hold from address change 3 – 3 – 3 – ns tACE CE LOW to data valid – 10 – 12 – 15 ns tDOE OE LOW to data valid – 5 – 6 – 7 ns 0 – 0 – 0 – ns – 5 – 6 – 7 ns tLZOE tHZOE OE LOW to low Z [6] OE HIGH to high Z [6, 7] [6] tLZCE CE LOW to low Z 3 – 3 – 3 – ns tHZCE CE HIGH to high Z [6, 7] – 5 – 6 – 7 ns tPU[8] tPD[8] CE LOW to power-up 0 – 0 – 0 – ns CE HIGH to power-down – 10 – 12 – 15 ns tDBE Byte enable to data valid – 5 – 6 – 7 ns tLZBE Byte enable to low Z 0 – 0 – 0 – ns Byte disable to high Z – 5 – 6 – 7 ns tHZBE Write Cycle [9, 10] tWC Write cycle time 10 – 12 – 15 – ns tSCE CE LOW to write end 8 – 9 – 10 – ns tAW Address set-up to write end 7 – 8 – 10 – ns tHA Address hold from write end 0 – 0 – 0 – ns tSA Address set-up to write start 0 – 0 – 0 – ns tPWE WE pulse width 7 – 8 – 10 – ns tSD Data set-up to write end 5 – 6 – 8 – ns tHD Data hold from write end 0 – 0 – 0 – ns [6] tLZWE WE HIGH to low Z 3 – 3 – 3 – ns tHZWE WE LOW to high Z [6, 7] – 5 – 6 – 7 ns tBW Byte enable to end of write 7 – 8 – 9 – ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. This parameter is guaranteed by design and is not tested. 9. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tSD and tHZWE. Document Number: 38-05133 Rev. *L Page 7 of 17 CY7C1020CV33 Switching Waveforms Figure 3. Read Cycle No. 1 [11, 12] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% IICC CC IISB SB Notes 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for Read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05133 Rev. *L Page 8 of 17 CY7C1020CV33 Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (CE Controlled) [14, 15] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Figure 6. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes 14. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 38-05133 Rev. *L Page 9 of 17 CY7C1020CV33 Switching Waveforms (continued) Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [16] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Note 16. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tSD and tHZWE. Document Number: 38-05133 Rev. *L Page 10 of 17 CY7C1020CV33 Truth Table CE OE H X X X X High Z High Z Power-down Standby (ISB) L L H L L Data out Data out Read – All bits Active (ICC) L H Data out High Z Read – Lower bits only Active (ICC) H L High Z Data out Read – Upper bits only Active (ICC) L L Data in Data in Write – All bits Active (ICC) L H Data in High Z Write – Lower bits only Active (ICC) H L High Z Data in Write – Upper bits only Active (ICC) L X WE BLE BHE L I/O1–I/O8 I/O9–I/O16 Mode Power L H H X X High Z High Z Selected, outputs disabled Active (ICC) L X X H H High Z High Z Selected, outputs disabled Active (ICC) Document Number: 38-05133 Rev. *L Page 11 of 17 CY7C1020CV33 Ordering Information Speed (ns) 15 Package Diagram Ordering Code Package Type Operating Range CY7C1020CV33-15ZSXE 51-85087 44-pin TSOP Type II (Pb-free) Automotive CY7C1020CV33-15ZSXET 51-85087 44-pin TSOP Type II (Pb-free) Automotive Ordering Code Definitions CY 7 C 1020 C V33 - 15 ZS X E X X = T or Blank T = Tape and Reel; Blank = Tube Temperature Range: E = Automotive Pb-free Package Type: ZS = 44-pin TSOP Type II Speed Grade: 15 ns V33 = 3.3 V Process Technology: C = 0.16 µm Part Identifier Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05133 Rev. *L Page 12 of 17 CY7C1020CV33 Package Diagrams Figure 8. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 38-05133 Rev. *L Page 13 of 17 CY7C1020CV33 Acronyms Acronym Document Conventions Description Units of Measure CMOS Complementary Metal Oxide Semiconductor CE Chip Enable °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static Random Access Memory mA milliampere TSOP Thin Small-Outline Package mW milliwatt TTL Transistor-Transistor Logic ns nanosecond Write Enable % percent WE Document Number: 38-05133 Rev. *L Symbol Unit of Measure pF picofarad V volt W watt Page 14 of 17 CY7C1020CV33 Document History Page Document Title: CY7C1020CV33, 512 K (32 K × 16) Static RAM Document Number: 38-05133 Rev. ECN No. Issue Date Orig. of Change ** 109428 12/16/01 HGK New data sheet. *A 115045 05/30/02 HGK Added 8 ns speed bin related information in all instances across the document. Updated Selection Guide: Changed value of “Maximum Operating Current” corresponding to 10 ns speed bin from 100 mA to 90 mA. Changed value of “Maximum Operating Current” corresponding to 12 ns speed bin from 100 mA to 85 mA. Changed value of “Maximum Operating Current” corresponding to 15 ns speed bin from 100 mA to 80 mA. Updated Electrical Characteristics: Changed maximum value of ICC parameter corresponding to 10 ns speed bin from 100 mA to 90 mA. Changed maximum value of ICC parameter corresponding to 12 ns speed bin from 100 mA to 85 mA. Changed maximum value of ICC parameter corresponding to 15 ns speed bin from 100 mA to 80 mA. Changed maximum value of ISB1 parameter corresponding to 10 ns, 12 ns and 15 ns speed bins from 40 mA to 15 mA. Updated Ordering Information: Updated part numbers. *B 117615 08/14/02 DFP Removed SOJ package related information in all instances across the document. Removed 8 ns speed bin related information in all instances across the document. Updated Pin Configuration: Updated Figure 1 (Replaced “A4” with “NC” for pin 1 and replaced “NC” with “A4” for pin 18). Updated Ordering Information: Updated part numbers. *C 262949 See ECN RKF Added Automotive Temperature Range related information in all instances across the document. Updated Ordering Information: Updated part numbers. *D 334398 See ECN SYT Updated Ordering Information: Updated part numbers (Added Lead-Free Product Information). *E 493543 See ECN NXR Updated Pin Configuration: Added Note 1 and referred the same note in Figure 1. Updated Electrical Characteristics: Changed the description of IIX parameter from “Input Load Current” to “Input Leakage Current”. Removed IOS parameter and its details. Updated Ordering Information: Updated part numbers. *F 2897691 03/23/2010 RAME Updated Ordering Information: Updated part numbers. Updated Package Diagrams. *G 3057593 10/13/2010 PRAS Updated Ordering Information: Updated part numbers. Added Ordering Code Definitions. Document Number: 38-05133 Rev. *L Description of Change Page 15 of 17 CY7C1020CV33 Document History Page (continued) Document Title: CY7C1020CV33, 512 K (32 K × 16) Static RAM Document Number: 38-05133 Rev. ECN No. Issue Date Orig. of Change *H 3100106 12/02/2010 PRAS *I 4146968 10/04/2013 VINI Updated Package Diagrams: spec 51-85087 – Changed revision from *C to *E. Updated to new template. Completing Sunset Review. *J 4567799 11/12/2014 VINI Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated Switching Characteristics: Added Note 10 and referred the same note in “Write Cycle”. Updated Switching Waveforms: Added Note 16 and referred the same note in Figure 7. Completing Sunset Review. Description of Change Minor edits across the document. Added Acronyms and Units of Measure. Updated to new template. *K 4573200 11/18/2014 VINI No technical updates. *L 5004033 11/05/2015 VINI Updated to new template. Completing Sunset Review. Document Number: 38-05133 Rev. *L Page 16 of 17 CY7C1020CV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05133 Rev. *L Revised November 5, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 17 of 17