CY62167DV30:16-Mbit (1M x 16) Static RAM Datasheet.pdf

CY62167DV30 MoBL®
16-Mbit (1 M × 16) Static RAM
16-Mbit (1 M × 16) Static RAM
Features
automatic power-down feature that significantly reduces power
consumption by 99% when addresses are not toggling. The
device can also be put into standby mode when deselected (CE1
HIGH or CE2 LOW or both BHE and BLE are HIGH). The
input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when: deselected (CE1 HIGH or CE2
LOW), outputs are disabled (OE HIGH), both Byte High Enable
and Byte Low Enable are disabled (BHE, BLE HIGH), or during
a Write operation (CE1 LOW, CE2 HIGH and WE LOW).
■
Thin small outline package (TSOP-I) configurable as
1 M × 16 or as 2 M × 8 SRAM
■
Wide voltage range: 2.2 V–3.6 V
■
Ultra-low active power:
Typical active current: 2 mA at f = 1 MHz
■
Ultra-low standby power
■
Easy memory expansion with CE1, CE2 and OE features
■
Automatic power-down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed / power
■
Available in Pb-free and non Pb-free 48-ball very fine-pitch ball
grid array (VFBGA) and 48-pin TSOP I package
Functional Description
The CY62167DV30 is a high-performance CMOS static RAM
organized as 1M words by 16-bits. This device features
advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL) in portable
applications such as cellular telephones. The device also has an
Writing to the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If
Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the address
pins (A0 through A19). If Byte High Enable (BHE) is LOW, then
data from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A19).
Reading from the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins appear on I/O0 to I/O7. If Byte High Enable (BHE)
is LOW, then data from memory appear on I/O8 to I/O15. See the
truth table at the back of this data sheet for a complete
description of Read and Write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
1M × 16 / 2M x 8
RAM Array
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BYTE
A11
A12
A13
A14
A15
A16
A17
A18
A19
BHE
WE
CE2
CE1
OE
BLE
Power-Down
Circuit
Cypress Semiconductor Corporation
Document Number: 38-05328 Rev. *M
•
CE2
CE1
BHE
BLE
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 19, 2014
CY62167DV30 MoBL®
Contents
Product Portfolio .............................................................. 3
Pin Configurations ........................................................... 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 12
Document Number: 38-05328 Rev. *M
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Page 2 of 18
CY62167DV30 MoBL®
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62167DV30LL
Operating ICC(mA)
Speed
(ns)
Min
Typ [1]
Max
2.2
3.0
3.6
f = 1 MHz
Standby ISB2(A)
f = fMax
Typ [1]
Max
Typ [1]
Max
Typ [1]
Max
2
4
15
30
2.5
22
12
25
55
70
Pin Configurations
Figure 1. 48-ball VFBGA pinout (Top View) [2, 3]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
Vcc
D
VCC
I/O12 DNU
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
DNU
H
Figure 2. 48-pin TSOP I pinout (Top View) [4]
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
2. NC pins are not connected on the die.
3. DNU pins have to be left floating.
4. The BYTE pin in the 48-TSOP I package has to be tied to VCC to use the device as a 1M X 16 SRAM. The 48-TSOP I package can also be used as a 2 M × 8 SRAM
by tying the BYTE signal to VSS. In the 2 M × 8 configuration, Pin 45 is A20, while BHE, BLE and I/O8 to I/O14 pins are not used (DNU).
Document Number: 38-05328 Rev. *M
Page 3 of 18
CY62167DV30 MoBL®
Maximum Ratings
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Latch-up current .................................................... > 200 mA
Storage temperature ................................ –65 °C to +150 °C
Operating Range
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage to ground potential ..... –0.2 V to VCC + 0.3 V
DC voltage applied to outputs
in High-Z state [5, 6] ............................. –0.2 V to VCC + 0.3 V
Device
Range
Ambient
Temperature
VCC[7]
CY62167DV30LL Industrial –40 °C to +85 °C
2.20 V to
3.60 V
DC input voltage [5, 6] .......................... –0.2 V to VCC + 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Electrical Characteristics
Over the Operating Range
Parameter
VOH
Description
Output HIGH voltage
Test Conditions
CY62167DV30-55
Min
Typ
IOH = –0.1 mA VCC = 2.20 V
2.0
–
IOH = –1.0 mA VCC = 2.70 V
2.4
VOL
Output LOW voltage
IOL = 0.1 mA
VCC = 2.20 V
IOL = 2.1 mA
VCC = 2.70 V
VIH
Input HIGH voltage
[8]
CY62167DV30-70
Unit
Max
Min
Typ [8]
Max
–
2.0
–
–
V
–
0.4
V
–
VCC + 0.3
V
–0.3
–
0.6
V
2.4
–
–
0.4
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3
VCC = 2.7 V to 3.6 V
2.2
–0.3
–
–1
–
+1
–1
–
+1
A
1.8
2.2
VIL
Input LOW voltage
VCC = 2.2 V to 2.7 V
IIX
Input leakage current
GND  VI  VCC
IOZ
Output leakage current GND  VO  VCC, output
disabled
–1
–
+1
–1
–
+1
A
ICC
VCC operating supply
current
VCC = VCC(max) f = fMax = 1/tRC
IOUT = 0 mA
f = 1 MHz
CMOS levels
–
15
30
–
12
25
mA
2
4
2
4
Automatic power-down CE1  VCC 0.2 V or CE2  0.2 V,
current – CMOS inputs VIN  VCC – 0.2 V, VIN  0.2 V,
f = fMax (address and data only),
–
2.5
22
–
2.5
22
A
–
2.5
22
–
2.5
22
A
VCC= 2.7 V to 3.6 V
ISB1
0.6
0.8
0.8
f = 0 (OE, WE), VCC = 3.60 V
ISB2
Automatic power-down CE1  VCC – 0.2 V or
current – CMOS Inputs CE2  0.2 V
VIN  VCC – 0.2 V or VIN  0.2V,
f = 0, VCC = 3.60 V
Notes
5. VIL(min.) = –2.0 V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
7. Full Device AC operation requires linear VCC ramp from 0 to VCC(min.) and VCC must be stable at VCC(min) for 500s.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 38-05328 Rev. *M
Page 4 of 18
CY62167DV30 MoBL®
Capacitance
Parameter [10]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
8
pF
10
pF
Thermal Resistance
Parameter [10]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
VFBGA
TSOP I
Unit
Still air, soldered on a 3 × 4.5 inch, 2-layer
printed circuit board
55
60
C/W
16
4.3
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
VCC
OUTPUT
R1
ALL INPUT PULSES
VCC
10%
50 pF[12]
R2
90%
GND
Rise Time = 1 V/ns
90%
10%
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.5 V
3.0 V
Unit
R1
16667
1103

R2
15385
1554

RTH
8000
645

VTH
1.20
1.75
V
Document Number: 38-05328 Rev. *M
Page 5 of 18
CY62167DV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Min
Typ [9]
Max
Unit
1.5
–
–
V
–
–
10
A
0
–
–
ns
CY62167DV30LL-55
55
–
–
ns
CY62167DV30LL-70
70
Conditions
VDR
VCC for data retention
ICCDR
Data retention current
tCDR[10]
Chip deselect to data retention
time
tR[11]
Operation recovery time
VCC = 1.5 V,
CE1  VCC – 0.2 V or CE2  0.2 V,
VIN  VCC – 0.2 V or VIN  0.2 V
Data Retention Waveform
Figure 4. Data Retention Waveform [12]
VCC
CE1 or
VCC, min.
tCDR
DATA RETENTION MODE
VDR  1.5 V
VCC, min.
tR
BHE,BLE
or
CE2
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device operation requires linear VCC ramp from VDR to VCC(min.)  100 s or stable at VCC(min.)  100 s.
12. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 38-05328 Rev. *M
Page 6 of 18
CY62167DV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter [13]
Description
55 ns
70 ns
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
55
–
70
–
ns
tAA
Address to data valid
–
55
–
70
ns
tOHA
Data hold from address change
10
–
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
55
–
70
ns
tDOE
OE LOW to data valid
–
25
–
35
ns
5
–
5
–
ns
–
20
–
25
ns
tLZOE
OE LOW to low Z
tHZOE
[14]
OE HIGH to high Z
[14, 15]
[14]
tLZCE
CE1 LOW and CE2 HIGH to low Z
10
–
10
–
ns
tHZCE
CE1 HIGH and CE2 LOW to high Z [14, 15]
–
20
–
25
ns
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down
–
55
–
70
ns
tDBE
BLE/BHE LOW to data valid
–
55
–
70
ns
tLZBE
BLE/BHE LOW to low Z [14]
10
–
10
–
ns
–
20
–
25
ns
tHZBE
Write Cycle
BLE/BHE HIGH to high Z
[14, 15]
[16]
tWC
Write cycle time
55
–
70
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
40
–
60
–
ns
tAW
Address setup to write end
40
–
60
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
40
–
45
–
ns
tBW
BLE/BHE LOW to write end
40
–
60
–
ns
tSD
Data setup to write end
25
–
30
–
ns
tHD
Data hold from write end
0
–
0
–
ns
tHZWE
WE LOW to high-Z [14, 15]
–
20
–
25
ns
10
–
10
–
ns
tLZWE
WE HIGH to low-Z
[14]
Notes
13. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of
0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
15. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
16. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the Write.
Document Number: 38-05328 Rev. *M
Page 7 of 18
CY62167DV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle 1 (Address Transition Controlled) [17, 18]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle 2 (OE Controlled) [18, 19]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tLZBE
OE
tDBE
tHZBE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
17. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
18. WE is HIGH for read cycle.
19. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 38-05328 Rev. *M
Page 8 of 18
CY62167DV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle 1 (WE Controlled) [20, 21, 22]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
See Note 23
tHZOE
Notes
20. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the Write.
21. Data I/O is high-impedance if OE = VIH.
22. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
23. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 38-05328 Rev. *M
Page 9 of 18
CY62167DV30 MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle 2 (CE1 or CE2 Controlled) [24, 25, 26]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
Note 27
tHZOE
Figure 9. Write Cycle 3 (WE Controlled, OE LOW) [26]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
WE
tSA
tHA
tPWE
tSD
DATA I/O
Note 27
tHD
VALID DATA
tHZWE
tLZWE
Notes
24. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the Write.
25. Data I/O is high-impedance if OE = VIH.
26. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
27. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 38-05328 Rev. *M
Page 10 of 18
CY62167DV30 MoBL®
Switching Waveforms (continued)
Figure 10. Write Cycle 4 (BHE/BLE Controlled, OE LOW) [28]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
Note 29
tHD
VALID DATA
Notes
28. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
29. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 38-05328 Rev. *M
Page 11 of 18
CY62167DV30 MoBL®
Truth Table
CE1
CE2
WE
OE
BHE
BLE
H
X
X
X
X
X
High Z
Deselect/Power-down
Standby (ISB)
X
L
X
X
X
X
High Z
Deselect/Power-down
Standby (ISB)
X
X
X
X
H
H
High Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
High Z (I/O8–I/O15);
Data out (I/O0–I/O7)
Read
Active (ICC)
L
H
H
L
L
H
Data out (I/O8–I/O15);
High Z (I/O0–I/O7)
Read
Active (ICC)
L
H
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
High Z (I/O8–I/O15);
Data in (I/O0–I/O7)
Write
Active (ICC)
L
H
L
X
L
H
Data in (I/O8–I/O15);
High Z (I/O0–I/O7)
Write
Active (ICC)
L
H
H
H
L
H
High Z
Output disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output disabled
Active (ICC)
Document Number: 38-05328 Rev. *M
Inputs/Outputs
Mode
Power
Page 12 of 18
CY62167DV30 MoBL®
Ordering Information
Speed
(ns)
55
Ordering Code
CY62167DV30LL-55BVI
Package
Diagram
Package Type
51-85178 48-ball FBGA (8 × 9.5 × 1 mm)
CY62167DV30LL-55BVXI
70
Operating
Range
Industrial
48-ball FBGA (8 × 9.5 × 1 mm) Pb-free
CY62167DV30LL-55ZXI
51-85183 48-pin TSOP I (12 × 18.4 × 1 mm) Pb-free
CY62167DV30LL-70BVI
51-85178 48-ball FBGA (8 × 9.5 × 1 mm)
Please contact your local Cypress sales representative for availability of these parts
Ordering Code Definitions
CY 621 6
7
D
V30 LL - XX XX
X
I
Temperature Range: I = Industrial
Pb-free
Package Type: XX = BV or Z
BV = 48-ball FBGA; Z = 48-pin TSOP I
Speed Grade: XX = 55 ns or 70 ns
Low Power
Voltage Range: 3 V Typical
Process Technology: 130 nm Technology
Bus Width: 7 = × 16
Density: 6 = 16-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05328 Rev. *M
Page 13 of 18
CY62167DV30 MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (8 × 9.5 × 1 mm) BV48B Package Outline, 51-85178
51-85178 *C
Document Number: 38-05328 Rev. *M
Page 14 of 18
CY62167DV30 MoBL®
Package Diagrams (continued)
Figure 12. 48-pin TSOP I (12 × 18.4 × 1 mm) Z48A Package Outline, 51-85183
51-85183 *C
Document Number: 38-05328 Rev. *M
Page 15 of 18
CY62167DV30 MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
I/O
Input/Output
°C
degrees Celsius
SRAM
Static Random Access Memory
MHz
megahertz
TSOP
Thin Small Outline Package
A
microampere
VFBGA
Very Fine-Pitch Ball Grid Array
mA
milliampere
ns
nanosecond

ohm
pF
picofarad
V
volt
W
watt
Document Number: 38-05328 Rev. *M
Symbol
Unit of Measure
Page 16 of 18
CY62167DV30 MoBL®
Document History Page
Document Title: CY62167DV30 MoBL®, 16-Mbit (1 M × 16) Static RAM
Document Number: 38-05328
Revision
ECN
Orig. of
Change
Submission
Date
**
118408
GUG
09/30/02
New data sheet.
*A
123692
DPM
02/11/03
Changed status from Advanced to Preliminary.
Added package diagram
*B
126555
DPM
04/25/03
Minor change: Changed Sunset Owner from DPM to HRT
*C
127841
XRJ
09/10/03
Added 48 TSOP I package
*D
205701
AJU
See ECN
Changed BYTE pin usage description for 48 TSOPI package
*E
238050
KKV/AJU
See ECN
Replaced 48-ball VFBGA package diagram; Modified Package Name in
Ordering Information table from BV48A to BV48B
*F
304054
PCI
See ECN
Added 45-ns Speed Bin in AC, DC and Ordering Information tables
Added Footnote #12 on page #4
Added Pb-free packages on page # 10
*G
492895
VKN
See ECN
Modified datasheet to explain x8 configurability.
Removed L power bin from the product offering
Updated Ordering Information Table
*H
2896036
AJU
03/19/10
Removed 45-ns. Removed inactive parts from Ordering Information.
Updated Packaging Information
Updated links in Sales, Solutions, and Legal Information.
*I
3067267
RAME
11/08/10
Updated datasheet as per new template
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated all table notes to footnote.
Package diagram updated 51-85178 from ** to *A
*J
3329789
RAME
07/27/11
Removed references to AN1064 SRAM system guidelines.
Updated template according to current CY standards.
*K
4108382
AJU
08/29/2013
Updated Pin Configurations:
Removed the note “Ball H6 for the FBGA package can be used to upgrade to
a 32M density” and its reference in Figure 1.
Updated Package Diagrams:
spec 51-85178 – Changed revision from *A to *C.
Updated in new template.
*L
4192919
VINI
11/15/2013
No technical updates.
Completing Sunset Review.
*M
4574377
VINI
11/19/2014
Added related documentation hyperlink in page 1.
Document Number: 38-05328 Rev. *M
Description of Change
Page 17 of 18
CY62167DV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
cypress.com/go/plc
Memory
cypress.com/go/memory
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cypress.com/go/support
cypress.com/go/touch
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Technical Support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2002-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05328 Rev. *M
Revised November 19, 2014
Page 18 of 18
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of
their respective holders.