CY7C1041D 4-Mbit (256 K × 16) Static RAM 4-Mbit (256 K × 16) Static RAM Features specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). ■ Pin-and function-compatible with CY7C1041B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 90 mA at 10 ns (Industrial) ■ Low CMOS standby power ❐ ISB2 = 10 mA ■ 2.0 V data retention ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 44-pin (400-Mil) Molded SOJ and 44-pin TSOP II packages Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Functional Description The CY7C1041D [1] is a high-performance CMOS static RAM organized as 256K words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location The CY7C1041D is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. The CY7C1041D is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. For a complete list of related documentation, click here. Logic Block Diagram 256K x 16 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER I/O0–I/O7 I/O8–I/O15 A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 COLUMN DECODER BHE WE CE OE BLE Note 1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document Number: 38-05472 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 24, 2014 CY7C1041D Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05472 Rev. *I Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY7C1041D Pin Configuration Figure 1. 44-pin SOJ / TSOP II pinout (Top View) A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Selection Guide -10 (Industrial) -12 (Automotive) [2] Maximum Access Time 10 12 ns Maximum Operating Current 90 95 mA Maximum CMOS Standby Current 10 15 mA Description Unit Note 2. Automotive product information is Preliminary. Document Number: 38-05472 Rev. *I Page 3 of 16 CY7C1041D Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... >2001 V Storage Temperature ............................... –65 C to +150 C Latch-up Current ..................................................... >200 mA Ambient Temperature with Power Applied ......................................... –55 C to +125 C Operating Range Ambient Temperature VCC Speed Industrial –40 C to +85 C 5 V 0.5 10 ns Automotive –40 C to +125 C 5 V 0.5 12 ns Supply Voltage on VCC to Relative GND [3] ...............................–0.5 V to +6.0 V DC Voltage Applied to Outputs in High Z State [3] ................................. –0.5 V to VCC +0.5 V Range DC Input Voltage [3] ............................. –0.5 V to VCC +0.5 V Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage Test Conditions VCC = Min IOH = –4.0 mA -10 (Industrial) -12 (Automotive) Min Max Min Max 2.4 – 2.4 – – 3.4 V [4] VCC = Max IOH = –0.1mA – VCC = Min IOL = 8.0 mA – 0.4 – 0.4 V 2.0 VCC + 0.5 2.0 VCC + 0.5 V –0.5 0.8 –0.5 0.8 V [3] 3.4 [4] Unit VIL Input LOW Voltage IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 A IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 –1 +1 A ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC 100 MHz – 90 – – mA 83 MHz – 80 – 95 mA 66 MHz – 70 – 85 mA 40 MHz – 60 – 75 mA ISB1 Automatic CE Power-Down Current – TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 20 – 25 mA ISB2 Automatic CE Power-Down Current – CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 – 10 – 15 mA Notes 3. VIL (Min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 4. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5V legacy processors that require a minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider. Document Number: 38-05472 Rev. *I Page 4 of 16 CY7C1041D Capacitance Parameter [5] Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0 V Max Unit 8 pF 8 pF Thermal Resistance Parameter [5] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) 44-pin SOJ Package Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 44-pin TSOP II Unit Package 57.91 50.66 C/W 36.73 17.17 C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [6] 10 ns device Z = 50 ALL INPUT PULSES OUTPUT 3.0 V 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 90% 30 pF* GND 1.5 V 90% 10% 10% 3 ns (a) (b) 3 ns High-Z Characteristics: R1 481 5V OUTPUT THÉVENIN EQUIVALENT 167 1.73 V OUTPUT Equivalent to: R2 255 5 pF INCLUDING JIG AND SCOPE (c) Notes 5. Tested initially and after any design or process changes that may affect these parameters. 6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure 2 (a). High-Z characteristics are tested for all speeds using the test load shown in Figure 2 (c) Document Number: 38-05472 Rev. *I Page 5 of 16 CY7C1041D Data Retention Characteristics Over the Operating Range Parameter Conditions[7] Description Min Max Unit 2.0 – V VDR VCC for Data Retention ICCDR Data Retention Current VCC = VDR = 2.0 V, Industrial – 10 mA ICCDR Data Retention Current CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Automotive – 15 mA tCDR[8] Chip Deselect to Data Retention Time 0 – ns tR[9] Operation Recovery Time tRC – ns Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 4.5 V VDR > 2 V tCDR 4.5 V tR CE Notes 7. No input may exceed VCC + 0.5 V. 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device operation requires linear VCC ramp from VDR to VCC(Min) > 50 s or stable at VCC(Min) > 50 s. Document Number: 38-05472 Rev. *I Page 6 of 16 CY7C1041D Switching Characteristics Over the Operating Range Parameter [11] Description -10 (Industrial) -12 (Automotive) Min Max Min Max Unit Read Cycle tpower VCC(typical) to the First Access[12] 100 – 100 – s tRC Read Cycle Time 10 – 12 – ns tAA Address to Data Valid – 10 – 12 ns tOHA Data Hold from Address Change 3 – 3 – ns tACE CE LOW to Data Valid – 10 – 12 ns tDOE OE LOW to Data Valid – 5 – 6 ns tLZOE OE LOW to Low Z 0 – 0 – ns – 5 – 6 ns 3 – 3 – ns – 5 – 6 ns Z[13, 14] tHZOE OE HIGH to High tLZCE CE LOW to Low Z[14] Z[13, 14] tHZCE CE HIGH to High tPU CE LOW to Power-Up 0 – 0 – ns tPD CE HIGH to Power-Down – 10 – 12 ns tDBE Byte Enable to Data Valid – 5 – 6 ns tLZBE Byte Enable to Low Z 0 – 0 – ns Byte Disable to High Z – 5 – 6 ns tHZBE Write Cycle [15, 16] tWC Write Cycle Time 10 – 12 – ns tSCE CE LOW to Write End 7 – 10 – ns tAW Address Set-Up to Write End 7 – 10 – ns tHA Address Hold from Write End 0 – 0 – ns tSA Address Set-Up to Write Start 0 – 0 – ns tPWE WE Pulse Width 7 – 10 – ns tSD Data Set-Up to Write End 6 – 7 – ns tHD Data Hold from Write End 0 – 0 – ns tLZWE WE HIGH to Low Z[14] 3 – 3 – ns – 5 – 6 ns 7 – 10 – ns [13, 14] tHZWE WE LOW to High Z tBW Byte Enable to End of Write Notes 10. AC characteristics (except High-Z) are tested using the load conditions shown in Figure 2 (a). High-Z characteristics are tested for all speeds using the test load shown in Figure 2 (c) 11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 12. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 13. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 2. Transition is measured when the outputs enter a high impedance state. 14. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given device. 15. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 16. The minimum Write cycle time for Write Cycle No. 4 (WE Controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05472 Rev. *I Page 7 of 16 CY7C1041D Switching Waveforms Figure 4. Read Cycle No. 1 [17, 18] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [19, 20] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes 17. No input may exceed VCC + 0.5 V. 18. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL. 19. WE is HIGH for read cycle. 20. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05472 Rev. *I Page 8 of 16 CY7C1041D Switching Waveforms(continued) Figure 6. Write Cycle No. 1 (CE Controlled) [21, 22] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O Figure 7. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O Notes 21. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 22. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 38-05472 Rev. *I Page 9 of 16 CY7C1041D Switching Waveforms(continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE HIGH During Write) [23, 24] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE BHE, BLE t SD DATA I/O NOTE 25 tHD DATAIN VALID t HZOE Figure 9. Write Cycle No. 4 (WE Controlled, OE LOW) [26] tWC BHE, BLE ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE DATA I/O tSD tHD NOTE 25 tLZWE Notes 23. Address valid prior to or coincident with CE transition LOW. 24. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 25. During this period the I/Os are in the output state and input signals should not be applied. 26. The minimum Write cycle time for Write Cycle No. 4 (WE Controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05472 Rev. *I Page 10 of 16 CY7C1041D Truth Table I/O0–I/O7 I/O8–I/O15 Mode Power CE OE WE BLE BHE H X X X X High Z High Z Power Down Standby (ISB) L L H L L Data Out Data Out Read All bits Active (ICC) L L H L H Data Out High Z Read Lower bits only Active (ICC) L L H H L High Z Data Out Read Upper bits only Active (ICC) L X L L L Data In Data In Write All bits Active (ICC) L X L L H Data In High Z Write Lower bits only Active (ICC) L X L H L High Z Data In Write Upper bits only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) Ordering Information Table 1 lists the CY7C1041D key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 1. Key Features and Ordering Information Speed (ns) 10 Package Diagram Ordering Code Package Type CY7C1041D-10VXI 51-85082 44-pin SOJ (400 Mils) Pb-free CY7C1041D-10ZSXI 51-85087 44-pin TSOP (Type II) Pb-free Operating Range Industrial Ordering Code Definitions CY 7 C 1 04 1 D - 10 XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = V or ZS V = 44-pin SOJ ZS = 44-pin TSOP Type II Speed: 10 ns Process Technology: D = C9, 90 nm Technology Data width: 1 = × 16-bits Density: 04 = 4-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05472 Rev. *I Page 11 of 16 CY7C1041D Package Diagrams Figure 10. 44-pin SOJ (400 Mils) V44.4 Package Outline, 51-85082 51-85082 *E Figure 11. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 38-05472 Rev. *I Page 12 of 16 CY7C1041D Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static Random Access Memory mA milliampere SOJ Small Outline J-Lead mV millivolt mW milliwatt ns nanosecond pF picofarad V volt W watt TSOP Thin Small Outline Package VFBGA Very Fine-Pitch Ball Grid Array Document Number: 38-05472 Rev. *I Symbol Unit of Measure Page 13 of 16 CY7C1041D Document History Page Document Title: CY7C1041D, 4-Mbit (256 K × 16) Static RAM Document Number: 38-05472 Revision ECN Orig. of Change Submission Date ** 201560 SWI See ECN Advance Datasheet for C9 IPP *A 233729 RKF See ECN 1.AC, DC parameters are modified as per EROS (Spec #01-2165) 2.Pb-free offering in the ‘ordering information’ *B 351117 PCI See ECN Changed from Advance to Preliminary Removed 17 and 20 ns Speed bin Added footnote # 4 Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 67 and 54 mA to 75 and 70 mA for 12 and 15 ns speed bins respectively ICC (Ind’l): Changed from 80, 67 and 54 mA to 90, 85 and 80 mA for 10, 12 and 15 ns speed bins respectively Changed footnote # 10 on tR Changed tSCE from 8 to 7 ns for 10 ns speed bin Added Static Discharge Voltage and latch-up current spec Added VIH(max) spec in footnote # 2 Changed reference voltage level for measurement of Hi-Z parameters from 500 mV to 200 mV Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram Changed part names from Z to ZS in the Ordering Information Table Removed L-Version Added 10 ns parts in the Ordering Information Table Added Lead-Free Ordering Information Shaded Ordering Information Table *C 446328 NXR See ECN Converted Preliminary to Final Removed -15 speed bin Removed Commercial Operating Range product information Added Automotive Operating Range product information Changed Maximum Rating for supply voltage from 7 V to 6 V Updated Thermal Resistance table Changed tHZWE from 6 ns to 5 ns Updated footnote #8 on High-Z parameter measurement Updated the Ordering Information and replaced Package Name column with Package Diagram in the Ordering Information table *D 2897049 VKN 03/22/10 Removed inactive parts from the ordering information table. *E 3109184 AJU 12/13/2010 Added Ordering Code Definitions. *F 3236731 PRAS 04/21/2011 Template updates. Added acronyms and units tables. *G 4040855 MEMJ 06/27/2013 Updated Functional Description. Updated Electrical Characteristics: Added one more Test Condition “VCC = Max, IOH = –0.1mA” for VOH parameter and added maximum value corresponding to that Test Condition. Added Note 4 and referred the same note in maximum value for VOH parameter corresponding to Test Condition “VCC = Max, IOH = –0.1mA”. Updated Package Diagrams: spec 51-85082 – Changed revision from *C to *E. spec 51-85087 – Changed revision from *C to *E. Updated in new template. Document Number: 38-05472 Rev. *I Description of Change Page 14 of 16 CY7C1041D Document History Page(continued) Document Title: CY7C1041D, 4-Mbit (256 K × 16) Static RAM Document Number: 38-05472 Revision ECN Orig. of Change *H 4390998 MEMJ 05/27/2014 Updated Switching Characteristics: Updated Note 16 (Replaced “Write Cycle No. 3” with “Write Cycle No. 4”). Updated Switching Waveforms: Added Note 26 and referred the same note in Figure 9. Completing Sunset Review. *I 4578500 MEMJ 11/24/2014 Added related documentation hyperlink in page 1. Document Number: 38-05472 Rev. *I Submission Date Description of Change Page 15 of 16 CY7C1041D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF Technical Support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05472 Rev. *I Revised November 24, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16