CY7C1051DV33 8-Mbit (512 K × 16) Static RAM Datasheet.pdf

CY7C1051DV33
8-Mbit (512 K × 16) Static RAM
8-Mbit (512K x 16) Static RAM
Features
Functional Description
■
Temperature ranges
❐ –40 °C to 85 °C
The CY7C1051DV33 is a high performance CMOS Static RAM
organized as 512 K words by 16-bits.
■
High speed
❐ tAA = 10 ns
■
Low active power
❐ ICC = 110 mA at f = 100 MHz
■
Low CMOS standby power
❐ ISB2 = 20 mA
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data
from I/O pins (I/O0–I/O7), is written into the location specified on
the address pins (A0–A18). If Byte HIGH Enable (BHE) is LOW,
then data from I/O pins (I/O8–I/O15) is written into the location
specified on the address pins (A0–A18).
■
2.0-V data retention
■
Automatic power-down when deselected
■
Transistor-transistor logic (TTL)-compatible inputs and outputs
■
Easy memory expansion with CE and OE features
■
Available in Pb-free 48-ball fine ball grid array (FBGA) and
44-pin thin small outline package (TSOP) II packages
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte LOW Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0–I/O7. If
Byte HIGH Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 10 for a
complete description of read and write modes.
The input/output pins (I/O0–I/O15) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or a write operation (CE LOW, and
WE LOW) is in progress.
The CY7C1051DV33 is available in a 44-pin TSOP II package
with center power and ground (revolutionary) pinout and a
48-ball FBGA package.
Logic Block Diagram
512 K × 16
ARRAY
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
I/O0–I/O7
I/O8–I/O15
A9
A10
A 11
A 12
A 13
A14
A15
A16
A17
A18
COLUMN
DECODER
Cypress Semiconductor Corporation
Document Number: 001-00063 Rev. *I
•
198 Champion Court
BHE
WE
CE
OE
BLE
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 10, 2014
CY7C1051DV33
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 4
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 5
Data Retention Waveform ................................................ 5
AC Switching Characteristics ......................................... 6
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Document Number: 001-00063 Rev. *I
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC® Solutions ...................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Page 2 of 15
CY7C1051DV33
Pin Configurations
Figure 1. Pin Diagram - 48-ball FBGA (Top View)[1]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Figure 2. Pin Diagram - 44-Pin TSOP II (Top View)[1]
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
37
13
32
31
30
29
28
27
14
15
16
17
18
19
20
21
22
36
35
34
33
26
25
24
23
A17
A16
A15
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
A18
A14
A13
A12
A11
A10
Selection Guide
–10
–12
Unit
Maximum access time
Description
10
12
ns
Maximum operating current
110
100
mA
Maximum CMOS standby current
20
20
mA
\
Note
1. NC pins are not connected on the die.
Document Number: 001-00063 Rev. *I
Page 3 of 15
CY7C1051DV33
Maximum Ratings
Static discharge voltage............. ...............................>2001 V
Exceeding the maximum ratings may shorten the useful life of
the device. These user guidelines are not tested.
(per MIL-STD-883, Method 3015)
Storage temperature ................................ –65 C to +150 C
Latch-up current ...................................................... >200 mA
Operating Range
Ambient temperature with
power applied............................................ –55 C to +125 C
DC voltage applied to outputs
in high-Z state[2] ...................................–0.3 V to VCC + 0.3 V
DC input
voltage[2]
Ambient
Temperature
Range
Supply voltage on VCC to relative GND[2] .... –0.5 V to +4.6 V
VCC
Speed
Industrial
–40 C to +85 C 3.3 V  0.3 V
10 ns
Industrial
–40 C to +85 C 3.3 V  0.3 V
12 ns
...............................–0.3 V to VCC + 0.3 V
Current into outputs (LOW) ..........................................20 mA
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
–10
–12
Min
Max
Min
Max
2.4
–
2.4
–
Unit
VOH
Output HIGH voltage
Min VCC, IOH = –4.0 mA
V
VOL
Output LOW voltage
Min VCC, IOL = 8.0 mA
–
0.4
–
0.4
V
VIH[2]
Input HIGH voltage
2.0
VCC + 0.3
2.0
VCC + 0.3
V
VIL[2]
Input LOW voltage
–0.3
0.8
–0.3
0.8
V
IIX
Input leakage current
GND < VIN < VCC
–1
+1
–1
+1
A
IOZ
Output leakage current
GND < VOUT < VCC, Output
Disabled
–1
+1
–1
+1
A
ICC
VCC operating
supply current
f = fMAX = 1/tRC
–
110
–
100
mA
ISB1
Automatic CE power
down current —TTL
inputs
Max VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
–
40
–
35
mA
ISB2
Automatic CE Power
Down Current —CMOS
Inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V, f
=0
–
20
–
20
mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
TA = 25C, f = 1 MHz, VCC = 3.3 V
Max
Unit
12
pF
12
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
JA
Thermal resistance
(Junction to ambient)
JC
Thermal resistance
(Junction to case)
Test Conditions
FBGA
Package
TSOP II
Package
Unit
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
28.31
51.43
C/W
11.4
15.8
C/W
Note
2. VIL(min) = –2.0 V and VIH(max) = VCC + 2.0 V for pulse durations of less than 20 ns.
Document Number: 001-00063 Rev. *I
Page 4 of 15
CY7C1051DV33
AC Test Loads and Waveforms
AC characteristics (except High-Z) are tested using the load conditions shown in Figure 3 (a). High-Z characteristics are tested for
all speeds using the test load shown in Figure 3 (c).
Figure 3. AC Test Loads and Waveforms
Z = 50
3.0 V
OUTPUT
50 
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5 V
30 pF*
GND
ALL INPUT PULSES
90%
Rise Time: 1 V/ns
(a)
90%
10%
10%
Fall Time: 1 V/ns
(b)
High-Z Characteristics
R 317
3.3 V
OUTPUT
R2
351
5 pF
(c)
Data Retention Characteristics
Over the Operating Range
Parameter
Conditions[3]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[4]
Chip Deselect to Data
Retention Time
tR[4]
Operation Recovery Time
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
Min
Max
Unit
2.0
–
V
–
20
mA
0
–
ns
tRC
–
ns
Data Retention Waveform
DATA RETENTION MODE
3.0 V
VCC
VDR > 2 V
tCDR
3.0 V
tR
CE
Notes
3. No inputs may exceed VCC + 0.3 V
4. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
Document Number: 001-00063 Rev. *I
Page 5 of 15
CY7C1051DV33
AC Switching Characteristics
Over the Operating Range[5]
Parameter
Description
–10
–12
Min
Max
Min
Max
Unit
Read Cycle
tpower[6]
VCC(typical) to the First Access
100
–
100
–
s
tRC
Read Cycle Time
10
–
12
–
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
–
10
–
12
ns
2.5
–
2.5
–
ns
CE LOW to Data Valid
–
10
–
12
ns
tDOE
OE LOW to Data Valid
–
5
–
6
ns
tLZOE
OE LOW to Low-Z
0
–
0
–
ns
tHZOE
OE HIGH to High-Z[7, 8]
–
5
–
6
ns
CE LOW to
Low-Z[8]
3
–
3
–
ns
tHZCE
CE HIGH to
High-Z[7, 8]
–
5
–
6
ns
tLZCE
tPU
CE LOW to Power Up
0
–
0
–
ns
tPD
CE HIGH to Power Down
–
10
–
12
ns
tDBE
Byte Enable to Data Valid
–
5
–
6
ns
tLZBE
Byte Enable to Low-Z
0
–
0
–
ns
tHZBE
Byte Disable to High-Z
–
5
–
6
ns
Write Cycle[9, 10]
tWC
Write Cycle Time
10
–
12
–
ns
tSCE
CE LOW to Write End
7
–
8
–
ns
tAW
Address Setup to Write End
7
–
8
–
ns
tHA
Address Hold from Write End
0
–
0
–
ns
tSA
Address Setup to Write Start
0
–
0
–
ns
tPWE
WE Pulse Width
7
–
8
–
ns
tSD
Data Setup to Write End
5
–
6
–
ns
tHD
Data Hold from Write End
0
–
0
–
ns
[8]
3
–
3
–
ns
[7, 8]
–
5
6
ns
7
–
–
ns
tLZWE
WE HIGH to Low-Z
tHZWE
WE LOW to High-Z
tBW
Byte Enable to End of Write
8
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. tPOWER gives the minimum amount of time that the power supply must be at typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, tHZBE and tHZWE are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms” on page 5.Transition is measured
when the outputs enter a high impedance state.
8. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any device.
9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
either of these signals can terminate the write. The input data setup and hold timing must refer to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-00063 Rev. *I
Page 6 of 15
CY7C1051DV33
Switching Waveforms
Figure 4. Read Cycle No. 1[11, 12]
tRC
ADDRESS
tOHA
DATA I/O
tAA
PREVIOUS DATA VALID
DATA OUT VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [12, 13]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA I/O
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
DATA OUT VALID
HIGH
IMPEDANCE
tPD
tPU
50%
50%
IICC
CC
IISB
SB
Notes
11. Device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
12. WE is HIGH for Read cycle.
13. Address valid before or coincident with CE transition LOW.
Document Number: 001-00063 Rev. *I
Page 7 of 15
CY7C1051DV33
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (CE Controlled) [14, 15]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
DATA I/O
tHD
DATA IN VALID
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
DATA I/O
tHD
DATA IN VALID
Notes
14. Data I/O is high-impedance if OE, or BHE, BLE, or both = VIH.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document Number: 001-00063 Rev. *I
Page 8 of 15
CY7C1051DV33
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [16]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
DATA I/O
tSD
tHD
DATA IN VALID
tLZWE
Note
16. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
Document Number: 001-00063 Rev. *I
Page 9 of 15
CY7C1051DV33
Truth Table
CE
OE
WE
BLE
BHE
H
X
X
X
X
High-Z
I/O0–I/O7
High-Z
Power Down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read All Bits
Active (ICC)
L
L
H
L
H
Data Out
High-Z
Read Lower Bits Only
Active (ICC)
L
L
H
H
L
High-Z
Data Out
Read Upper Bits Only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write All Bits
Active (ICC)
L
X
L
L
H
Data In
High-Z
Write Lower Bits Only
Active (ICC)
L
X
L
H
L
High-Z
Data In
Write Upper Bits Only
Active (ICC)
L
H
H
X
X
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
Document Number: 001-00063 Rev. *I
I/O8–I/O15
Mode
Power
Page 10 of 15
CY7C1051DV33
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and
refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains
a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit
us at http://www.cypress.com/go/datasheet/offices.
Speed
(ns)
10
12
Ordering Code
Package
Diagram
Package Type
CY7C1051DV33-10BAXI
51-85193
48-ball FBGA (Pb-free)
CY7C1051DV33-10ZSXI
51-85087
44-pin TSOP II (Pb-free)
CY7C1051DV33-12BAXI
51-85193
48-ball FBGA (Pb-free)
CY7C1051DV33-12ZSXI
51-85087
44-pin TSOP II (Pb-free)
Operating
Range
Industrial
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 7 C 1 05 1
D V33 - XX XXX X
Temperature Range: x = I or E
I = Industrial
Package Type: XXX = BAX or ZSX
BAX = 48-ball FBGA (Pb-free)
ZSX = 44-pin TSOP II(Pb-free)
Speed: XX = 10 ns or 12 ns or 15 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
1 = Data width × 16-bits
05 = 8-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Document Number: 001-00063 Rev. *I
Page 11 of 15
CY7C1051DV33
Package Diagrams
Figure 9. 48-Ball FBGA (6 x 8 x 1.2 mm), 51-85193
51-85193 *C
Document Number: 001-00063 Rev. *I
Page 12 of 15
CY7C1051DV33
Package Diagrams (continued)
Figure 10. 44-Pin Thin Small Outline Package Type II, 51-85087
51-85087 *E
Acronyms
Document Conventions
Acronym
Description
CE
chip enable
CMOS
complementary metal oxide semiconductor
I/O
input/output
OE
output enable
SRAM
static random access memory
SOJ
small outline J-lead
TSOP
thin small outline package
VFBGA
very fine-pitch ball grid array
Document Number: 001-00063 Rev. *I
Units of Measure
Symbol
Unit of Measure
ns
nanosecond
V
volt
µA
microampere
mA
milliampere
mV
millivolt
mW
milliwatt
MHz
megahertz
pF
picofarad
°C
degree Celsius
W
watt
Page 13 of 15
CY7C1051DV33
Document History Page
Document Title: CY7C1051DV33, 8-Mbit (512 K × 16) Static RAM
Document Number: 001-00063
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
342195
PCI
See ECN
New Datasheet
*A
380574
SYT
See ECN
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8, 10
and 12 ns speed bins respectively
ICC (Ind’l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8, 10
and 12 ns speed bins respectively
Changed the Capacitance values from 8 pF to 10 pF on Page # 3
*B
485796
NXR
See ECN
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed -8 and -12 Speed bins from product offering,
Removed Commercial Operating Range option,
Modified Maximum Ratings for DC input voltage from -0.5 V to -0.3 V and
VCC + 0.5 V to VCC + 0.3 V
Changed the Description of IIX from Input Load Current to
Input Leakage Current.
Changed tHZBE from 5 ns to 6 ns
Updated footnote #7 on High-Z parameter measurement
Added footnote #11
Updated the Ordering Information table and Replaced Package Name column
with Package Diagram.
*C
866000
NXR
See ECN
Changed ball E3 from VSS to NC in FBGA pin configuration
*D
1513285
VKN/AESA
See ECN
Converted from preliminary to final
Changed tHZBE from 6 ns to 5 ns for 10 ns speed bin
Added 12 ns speed bin
Changed tOHA spec from 3 ns to 2.5 ns
Updated Ordering information table
*E
2911009
VKN
04/12/10
Replaced 48-Ball (7 x 8.5 x 1.2 mm) FBGA with 48-Ball (6 x 8 x 1.2mm) FBGA,
Updated Package diagrams, Updated ordering information.
*F
3086522
PRAS
11/15/2010
Included Auto-E information (preliminary) in Ordering Information.
*G
3112625
AJU
12/16/2010
Added Ordering Code Definitions.
*H
3369149
TAVA
09/12/2011
Removed all references to Automotive information.
*I
4530449
MEMJ
10/10/2014
Updated Switching Waveforms:
Added Note 16 and referred the same note in Figure 8.
Updated Package Diagrams:
spec 51-85087 – Changed revision from *D to *E.
Updated in new template.
Completing Sunset Review.
Document Number: 001-00063 Rev. *I
Page 14 of 15
CY7C1051DV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
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USB Controllers
Wireless/RF
psoc.cypress.com/solutions
cypress.com/go/USB
cypress.com/go/wireless
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-00063 Rev. *I
Revised October 10, 2014
All products and company names mentioned in this document may be the trademarks of their respective holders.
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