CY7C1399BN 256-Kbit (32 K × 8) Static RAM 256-Kbit (32 K × 8) Static RAM Features Functional Description ■ Temperature Ranges ❐ Industrial: –40 °C to 85 °C ❐ Commercial: 0 °C to 70 °C ❐ Automotive-A: –40 °C to 85 °C The CY7C1399BN is a high-performance 3.3 V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tristate drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. ■ Single 3.3 V power supply ■ Ideal for low-voltage cache memory applications ■ High speed: 12 ns ■ Low active power ❐ 180 mW (max) ■ Low-power alpha immune 6T cell ■ Available in pb-free and non pb-free plastic SOJ and TSOP- I packages An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399BN is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I packages. For a complete list of related documentation, click here. Logic Block Diagram g I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 32K x 8 ARRAY I/O3 I/O4 I/O5 CE WE POWER DOWN COLUMN DECODER I/O7 • A 14 A 12 A 13 A 11 A 10 OE Cypress Semiconductor Corporation Document Number: 001-06490 Rev. *H I/O6 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 24, 2015 CY7C1399BN Contents Pin Configurations ........................................................... 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform ................................................ 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Document Number: 001-06490 Rev. *H Package Diagrams .......................................................... 12 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY7C1399BN Pin Configurations Figure 1. 28-pin TSOP pinout (Top View) TSOP Top View OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 21 22 23 20 19 18 17 16 15 14 13 12 11 10 9 8 24 25 26 27 28 1 2 3 4 5 6 7 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 Figure 2. 28-pin SOJ pinout (Top View) SOJ Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 Selection Guide Description Condition Maximum access time (ns) Maximum operating current (mA) Maximum CMOS standby current (A) Commercial -15 12 15 55 50 500 – Commercial (L) 50 – Industrial 500 500 – 500 Automotive-A Document Number: 001-06490 Rev. *H -12 Page 3 of 16 CY7C1399BN Maximum Ratings Output current into outputs (LOW) ............................. 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied .......................................... –55 C to +125 C Supply voltage on VCC to relative GND [1] ................................–0.5 V to +4.6 V DC voltage applied to outputs in high Z State [1] ................................. –0.5 V to VCC + 0.5 V DC input voltage [1] ............................. –0.5 V to VCC + 0.5 V Static discharge voltage (per MIL-STD-883, Method 3015) .......................... >2001 V Latch-up current .................................................... >200 mA Operating Range Range Ambient Temperature VCC 0C to +70C 3.3 V 300 mV Commercial Industrial –40C to +85C Automotive-A –40C to +85C Electrical Characteristics Over the Operating Range Parameter [1] Description Test Conditions VOH Output HIGH voltage Min VCC, IOH = –2.0 mA Min VCC, IOL = 4.0 mA -12 -15 Unit Min Max Min Max 2.4 – 2.4 – V VOL Output LOW voltage – 0.4 – 0.4 V VIH Input HIGH voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V VIL[1] Input LOW voltage –0.3 0.8 –0.3 0.8 V IIX Input leakage current –1 +1 –1 +1 A IOZ Output leakage current GND VIN VCC, Output disabled –5 +5 –5 +5 A ICC VCC operating supply current Max VCC, IOUT = 0 mA, f = fMAX = 1/tRC – 55 – 50 mA ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE VIH, Commercial VIN VIH, or Commercial (L) VIN VIL, f = fMAX Industrial Automotive-A ISB2 Automatic CE Power-down current – CMOS inputs [2] – 5 – – mA – 4 – – mA – 5 – 5 mA – – – 5 mA Max VCC, Commercial – 500 – – A CE VCC – 0.3 V, Commercial (L) – 50 – – A – 500 – 500 A – – – 500 A Industrial VIN VCC – 0.3 V, or Automotive-A VIN 0.3 V, WE VCC – 0.3 V or WE 0.3 V, f = fMAX Notes 1. Minimum voltage is equal to – 2.0 V for pulse durations of less than 20 ns. 2. Device draws low standby current regardless of switching on the addresses. Document Number: 001-06490 Rev. *H Page 4 of 16 CY7C1399BN Capacitance Parameter [3] Description Test Conditions CIN: Addresses Input capacitance Max Unit 5 pF 6 pF 6 pF TA = 25C, f = 1 MHz, VCC = 3.3 V CIN: Controls Output capacitance COUT AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [4] R1 317 3.3 V ALL INPUT PULSES 3.0 V OUTPUT INCLUDING JIG AND SCOPE CL R2 351 10% GND 90% 90% 10% Equivalent to: THÉVENINEQUIVALENT 167 OUTPUT 1.73 V 3 ns 3 ns Data Retention Characteristics (Over the Operating Range - L version only) Parameter Description Conditions VDR VCC for data retention ICCDR Data retention current tCDR Chip deselect to data retention time tR Operation recovery time Min VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Max Unit 2.0 – V 0 20 A 0 – ns tRC – ns Data Retention Waveform Figure 4. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V tCDR VDR 2 V 3.0 V tR CE Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and capacitance CL = 30 pF. Document Number: 001-06490 Rev. *H Page 5 of 16 CY7C1399BN Switching Characteristics Over the Operating Range Parameter [5] Description -12 -15 Min Max Min Max Unit Read Cycle tRC Read cycle time 12 – 15 – ns tAA Address to data valid – 12 – 15 ns tOHA Data hold from address change 3 – 3 – ns tACE CE LOW to data valid – 12 – 15 ns tDOE OE LOW to data valid – 5 – 6 ns 0 – 0 – ns – 5 – 6 ns tLZOE tHZOE OE LOW to low Z [6] OE HIGH to high Z [6, 7] [6] tLZCE CE LOW to low Z 3 – 3 – ns tHZCE CE HIGH to high Z [6, 7] – 6 – 7 ns tPU CE LOW to power-up 0 – 0 – ns CE HIGH to power-down – 12 – 15 ns tPD Write Cycle [8, 9] tWC Write cycle time 12 – 15 – ns tSCE CE LOW to write end 8 – 10 – ns tAW Address setup to write end 8 – 10 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 8 – 10 – ns tSD Data setup to write end 7 – 8 – ns tHD Data hold from write end 0 – 0 – ns tHZWE WE low to high Z[8] – 7 – 7 ns tLZWE [6] 3 – 3 – ns WE high to low Z Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and capacitance CL = 30 pF. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE Controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-06490 Rev. *H Page 6 of 16 CY7C1399BN Switching Waveforms Figure 5. Read Cycle No. 1 [10, 11] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATA VALID DATA OUT VALID Figure 6. Read Cycle No. 2 [11, 12] tRC CE tACE OE tHZOE tHZCE tDOE DATA I/O tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE DATA OUT VALID tPD tPU ICC 50% 50% ISB Notes 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document Number: 001-06490 Rev. *H Page 7 of 16 CY7C1399BN Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (WE Controlled) [13, 14, 15] tWC ADDRESS CE tAW tHA tSA WE tPWE OE tSD DATA I/O NOTE 16 tHD DATA IN VALID tHZOE Figure 8. Write Cycle No. 2 (CE Controlled) [13, 14, 15] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATA IN VALID Notes 13. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 16. During this period, the I/Os are in the output state and input signals should not be applied. Document Number: 001-06490 Rev. *H Page 8 of 16 CY7C1399BN Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [17, 18] tWC ADDRESS CE tAW WE tHA tSA tSD DATA I/O tHD DATA IN VALID NOTE 19 tHZWE tLZWE Notes 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD. 19. During this period, the I/Os are in the output state and input signals should not be applied. Document Number: 001-06490 Rev. *H Page 9 of 16 CY7C1399BN Truth Table CE WE OE Input/Output H X X High Z Deselect/Power-down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Deselect, Output disabled Active (ICC) Document Number: 001-06490 Rev. *H Mode Power Page 10 of 16 CY7C1399BN Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 12 Ordering Code CY7C1399BN-12ZXC Package Diagram 51-85071 28-pin TSOP I (Pb-free) CY7C1399BNL-12ZXC CY7C1399BN-12VXI Package Type Operating Range Commercial 28-pin TSOP I (Pb-free) 51-85031 28-pin molded SOJ (Pb-free) Industrial Contact your local sales representative regarding availability of these parts. Ordering Code Definitions CY 7 C 1 399 BN L - XX X X C Temperature Range: X = C or I or A C = Commercial I = Industrial A = Automotive-A X = Pb-free Package Type: X = V or Z V = 28-pin Molded SOJ Z = 28-pin TSOP I Speed: XX = 12 ns or 15 ns L = Low power Process Technology: BN = 0.25 µm 399 = 256-Kb density with data width × 8 bits Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-06490 Rev. *H Page 11 of 16 CY7C1399BN Package Diagrams Figure 10. 28-pin SOJ (300 Mils) V28.3 (Molded SOJ V21) Package Outline, 51-85031 51-85031 *F Document Number: 001-06490 Rev. *H Page 12 of 16 CY7C1399BN Package Diagrams (continued) Figure 11. 28-pin TSOP I (8 × 13.4 × 1.2 mm) Z28 (Standard) Package Outline, 51-85071 51-85071 *J Document Number: 001-06490 Rev. *H Page 13 of 16 CY7C1399BN Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static Random Access Memory mA milliampere TSOP Thin Small Outline Package mV millivolt WE Write Enable mW milliwatt ns nanosecond pF picofarad V volt W watt Document Number: 001-06490 Rev. *H Symbol Unit of Measure Page 14 of 16 CY7C1399BN Document History Page Document Title: CY7C1399BN, 256-Kbit (32 K × 8) Static RAM Document Number: 001-06490 Revision ECN Orig. of Change Submission Date ** 423877 NXR See ECN New data sheet. *A 498575 NXR See ECN Added Automotive-A range related information in all instances across the document. Updated Electrical Characteristics: Removed IOS parameter and its details. Updated Ordering Information. *B 2896382 AJU 03/19/2010 Updated Ordering Information: Removed obsolete part numbers. Updated Package Diagrams. *C 3053362 PRAS 10/08/2010 Updated Ordering Information: Removed pruned part numbers CY7C1399BNL-15VXC and CY7C1399BNL-15VXCT. Added Ordering Code Definitions. *D 3383869 TAVA 09/26/2011 Rearranged sections for better clarity. Updated Features: Added Commercial Temperature Range related information. Updated Functional Description: Removed Note “For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com website.” and its reference. Updated Switching Waveforms: Modified the notes in figures under Read cycle and Write cycle sections. Updated Package Diagrams. Added Acronyms and Units of Measure. Updated to new template. *E 4121360 VINI 09/12/2013 Updated to new template. Completing Sunset Review. *F 4540416 VINI 10/16/2014 Updated Switching Waveforms: Updated Note 18. Updated Package Diagrams: spec 51-85071 – Changed revision from *I to *J. Completing Sunset Review. *G 4578447 VINI 01/16/2015 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Ordering Information: Removed the prune part numbers CY7C1399BN-12VXC and CY7C1399BN-15VXA. Updated Package Diagrams: spec 51-85031 – Changed revision from *E to *F. Updated to new template. *H 4985705 NILE 10/24/2015 No technical updates. Completing Sunset Review. Document Number: 001-06490 Rev. *H Description of Change Page 15 of 16 CY7C1399BN Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06490 Rev. *H Revised October 24, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16