CY7C1079DV33 32-Mbit (4 M × 8) Static RAM Datasheet.pdf

CY7C1079DV33
32-Mbit (4 M × 8) Static RAM
32-Mbit (4 M × 8) Static RAM
Features
■
High Speed
❐ tAA = 12 ns
■
Low Active Power
❐ ICC = 250 mA at 12 ns
■
Low CMOS Standby Power
❐ ISB2 = 50 mA
Functional Description
The CY7C1079DV33 is a high performance CMOS Static RAM
organized as 4,194,304 words by 8 bits.
To write to the device, take Chip Enable (CE [1]) and Write Enable
(WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A21).
■
Operating Voltages of 3.3 ± 0.3 V
■
2.0 V Data Retention
■
Automatic Power Down when Deselected
■
TTL Compatible Inputs and Outputs
■
Available in Pb-free 48-ball FBGA Package
To read from the device, take Chip Enable (CE [1]) LOW and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
See Truth Table (Single Chip Enable) on page 10 for a complete
description of Read and Write modes.
The input and output pins (I/O0 through I/O7) are placed in a high
impedance state when the device is deselected (CE [1] HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE [1] LOW and WE LOW).
The CY7C1079DV33 is available in a 48-ball FBGA package.
For a complete list of related documentation, click here.
Logic Block Diagram
4M x 8
ARRAY
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFER
IO0 – IO7
WE
COLUMN
DECODER
OE
A10
A11
A 12
A 13
A 14
A15
A16
A17
A18
A19
A20
A21
CE
[1]
Note
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and
CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
Cypress Semiconductor Corporation
Document Number: 001-50282 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 28, 2014
CY7C1079DV33
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
AC Switching Characteristics ......................................... 7
Switching Waveforms ...................................................... 8
Truth Table (Single Chip Enable) .................................. 10
Truth Table (Dual Chip Enable) ..................................... 10
Document Number: 001-50282 Rev. *F
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC® Solutions ...................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Page 2 of 15
CY7C1079DV33
Selection Guide
-12
Unit
Maximum Access Time
Description
12
ns
Maximum Operating Current
250
mA
Maximum CMOS Standby Current
50
mA
Pin Configuration
Figure 1. 48-ball FBGA (Single Chip Enable) pinout [2]
1
2
3
4
5
6
NC
OE
A0
A1
A2
NC
NC
NC
A3
A4
CE
IO0
NC
A5
A6
VSS
IO1
A17
VCC
IO2
IO3
Figure 2. 48-ball FBGA (Dual Chip Enable) pinout [2]
1
2
3
4
5
6
A
NC
OE
A0
A1
A2
CE2
A
NC
B
NC
NC
A3
A4
CE1
NC
B
NC
IO4
C
IO0
NC
A5
A6
NC
IO4
C
A7
IO5
VCC
D
VSS
IO1
A17
A7
IO5
VCC
D
A18
A16
IO6
VSS
E
VCC
IO2
A18
A16
IO6
VSS
E
NC
A14
A15
NC
IO7
F
IO3
NC
A14
A15
NC
IO7
F
NC
A21
A12
A13
WE
NC
G
NC
A21
A12
A13
WE
NC
G
A19
A8
A9
A10
A11
A20
H
A19
A8
A9
A10
A11
A20
H
Note
2. NC pins are not connected to the die.
Document Number: 001-50282 Rev. *F
Page 3 of 15
CY7C1079DV33
DC Input Voltage [3] ............................ –0.5 V to VCC + 0.5 V
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Storage Temperature ............................... –65 C to +150 C
Latch Up Current ................................................... > 200 mA
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Operating Range
Supply Voltage on
VCC Relative to GND [3] ...............................–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State [3] ................................ –0.5 V to VCC + 0.5 V
Range
Ambient Temperature
VCC
Industrial
–40 C to +85 C
3.3 V  0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min, IOL = 8.0 mA
-12
Unit
Min
Max
2.4
–
V
–
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
VIL
Input LOW Voltage [3]
–0.3
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
A
IOZ
Output Leakage Current
GND < VOUT < VCC, Output disabled
–1
+1
A
ICC
VCC Operating Supply Current
VCC = Max, f = fMAX = 1/tRC,
IOUT = 0 mA CMOS levels
–
250
mA
ISB1
Automatic CE Power Down
Current – TTL Inputs
Max VCC, CE [4] > VIH,
VIN > VIH or VIN < VIL, f = fMAX
–
60
mA
ISB2
Automatic CE Power Down
Current – CMOS Inputs
Max VCC, CE [4] > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
–
50
mA
Notes
3. VIL (min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
4. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and
CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
Document Number: 001-50282 Rev. *F
Page 4 of 15
CY7C1079DV33
Capacitance
Parameter [5]
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
48-ball FBGA
Unit
16
pF
20
pF
Test Conditions
48-ball FBGA
Unit
Still air, soldered on a 3 × 4.5 inch, four layer printed circuit
board
30.91
C/W
13.60
C/W
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Thermal Resistance
Parameter [5]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [6]
High-Z characteristics
3.3 V
50 
VTH = 1.5 V
OUTPUT
Z0 = 50 
R1 317 
OUTPUT
30 pF*
5 pF*
(a)
* Capacitive load consists
of all components of the
test environment
3.0 V
GND
Rise Time > 1 V/ns
ALL INPUT PULSES
90%
90%
10%
10%
(c)
R2
351
INCLUDING
JIG AND
SCOPE
(b)
Fall Time:
> 1 V/ns
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating
VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage.
Document Number: 001-50282 Rev. *F
Page 5 of 15
CY7C1079DV33
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
VCC for Data Retention
VDR
[7]
ICCDR
Data Retention Current
VCC = 2 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
tCDR [8]
Chip Deselect to Data Retention
Time
tR [9]
Operation Recovery Time
Min
Typ
Max
Unit
2
–
–
V
–
–
50
mA
0
–
–
ns
tRC
–
–
ns
Data Retention Waveform
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC
3.0 V
tCDR
VDR > 2 V
3.0 V
tR
CE [6]
Notes
7. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and
CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.
Document Number: 001-50282 Rev. *F
Page 6 of 15
CY7C1079DV33
AC Switching Characteristics
Over the Operating Range
Parameter [10]
Description
-12
Min
Max
Unit
Read Cycle
tpower
VCC(Typical) to the First Access [11]
100
–
s
tRC
Read Cycle Time
12
–
ns
tAA
Address to Data Valid
–
12
ns
tOHA
Data Hold from Address Change
3
–
ns
tACE
CE [12] LOW to Data Valid
–
12
ns
tDOE
OE LOW to Data Valid
–
7
ns
tLZOE
OE LOW to Low Z
1
–
ns
–
7
ns
3
–
ns
–
7
ns
0
–
ns
–
12
ns
[13]
tHZOE
OE HIGH to High Z
tLZCE
CE LOW to Low Z [12, 13]
tHZCE
tPU
tPD
CE HIGH LOW to High Z
[12, 13]
CE LOW HIGH to Power Up
[12, 14]
CE HIGH LOW to Power Down
[12, 14]
Write Cycle [15, 16]
tWC
Write Cycle Time
12
–
ns
tSCE
CE [12] LOW
9
–
ns
tAW
Address Setup to Write End
9
–
ns
tHA
Address Hold from Write End
0
–
ns
tSA
Address Setup to Write Start
0
–
ns
tPWE
WE Pulse Width
9
–
ns
tSD
Data Setup to Write End
7
–
ns
tHD
Data Hold from Write End
0
–
ns
WE HIGH to Low Z
[13]
3
–
ns
WE LOW to High Z
[13]
–
7
ns
tLZWE
tHZWE
HIGH to Write End
Notes
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading shown in part a) of Figure 3 on page 5, unless specified otherwise.
11. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
12. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and
CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
13. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 5. Transition is measured 200 mV from steady state voltage.
14. These parameters are guaranteed by design and are not tested.
15. The internal write time of the memory is defined by the overlap of WE, CE = VIL. CE and WE are LOW to initiate a write, and the transition of any of these signals can
terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
16. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-50282 Rev. *F
Page 7 of 15
CY7C1079DV33
Switching Waveforms
Figure 5. Read Cycle No. 1 [17, 18]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [18, 19, 20]
tRC
ADDRESS
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
50%
ICC
ISB
Notes
17. The device is continuously selected. CE = VIL.
18. WE is HIGH for read cycle.
19. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and
CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
20. Address valid before or similar to CE transition LOW.
Document Number: 001-50282 Rev. *F
Page 8 of 15
CY7C1079DV33
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (CE Controlled) [21, 22, 23]
tWC
ADDRESS
tSA
CE
tSCE
tAW
tHA
tPWE
WE
tSD
tHD
DATA I/O
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [21, 22, 23]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Notes
21. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and
CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
22. Data I/O is high impedance if OE = VIH.
23. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 001-50282 Rev. *F
Page 9 of 15
CY7C1079DV33
Truth Table (Single Chip Enable)
CE [1]
OE
WE
H
X
X
High Z
Power Down
Standby (ISB)
L
L
H
Data Out
Read All Bits
Active (ICC)
L
X
L
Data In
Write All Bits
Active (ICC)
L
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
I/O0–I/O7
Mode
Power
Truth Table (Dual Chip Enable)
CE1
CE2
OE
WE
I/O0–I/O7
H
X
X
X
High Z
Power Down
Standby (ISB)
X
L
X
X
High Z
Power Down
Standby (ISB)
L
H
L
H
Data Out
Read All Bits
Active (ICC)
L
H
X
L
Data In
Write All Bits
Active (ICC)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Document Number: 001-50282 Rev. *F
Mode
Power
Page 10 of 15
CY7C1079DV33
Ordering Information
Speed
(ns)
12
Ordering Code
CY7C1079DV33-12BAXI
Package
Diagram
Package Type
51-85191 48-ball FBGA (8 × 9.5 × 1.2 mm) (Pb-free) [24]
Operating
Range
Industrial
Contact sales for part availability.
Ordering Code Definitions
CY 7 C 1 07 9
D V33 - 12
XX X
I
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = BA or B2
BA = 48-ball FBGA – Single Chip Enable
B2 = 48-ball FBGA – Dual Chip Enable
Speed: 12 ns
Voltage Range: V33 = 3 V to 3.6 V
Process Technology: D = C9, 90 nm Technology
Data width: 9 = × 8-bits
Density: 07 = 32-Mbit density
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Notes
24. This BGA package is offered with single chip enable.
25. This BGA package is offered with dual chip enable.
Document Number: 001-50282 Rev. *F
Page 11 of 15
CY7C1079DV33
Package Diagrams
Figure 9. 48-ball FBGA (8 × 9.5 × 1.2 mm) BA48J Package Outline, 51-85191
51-85191 *C
Document Number: 001-50282 Rev. *F
Page 12 of 15
CY7C1079DV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
FPBGA
Fine-Pitch Ball Grid Array
MHz
megahertz
I/O
Input/Output
µA
microampere
OE
Output Enable
µs
microsecond
SRAM
Static Random Access Memory
mA
milliampere
mm
millimeter
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 001-50282 Rev. *F
Symbol
Unit of Measure
ms
millisecond
mV
millivolt
ns
nanosecond

ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 13 of 15
CY7C1079DV33
Document History Page
Document Title: CY7C1079DV33, 32-Mbit (4 M × 8) Static RAM
Document Number: 001-50282
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
2711136
05/29/2009
VKN /
PYRS
New data sheet.
*A
2759408
09/03/2009
VKN /
AESA
Removed 10 ns speed bin related information across the document.
Description of Change
Updated Thermal Resistance:
Marked thermal specs as “TBD”.
Updated AC Switching Characteristics:
Changed maximum value of tDOE, tHZOE, tHZCE, tHZWE parameters from 6 ns
to 7 ns.
Updated Ordering Information:
Added -12B2XI part (Dual CE option)
*B
2813370
11/23/2009
VKN
*C
3132969
01/11/2011
PRAS
Updated DC Electrical Characteristics:
Changed maximum value of ICC parameter from 225 mA to 250 mA.
Added Ordering Code Definitions under Ordering Information.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Changed all instances of IO to I/O.
Updated in new template.
*D
3232668
04/18/2011
PRAS
Changed status from Preliminary to Final.
Updated Pin Configuration (Figure 2).
Updated Thermal Resistance.
*E
4434923
07/09/2014
VINI
Updated Package Diagrams:
spec 51-85191 – Changed revision from *A to *C.
Updated in new template.
Completing Sunset Review.
*F
4582593
11/28/2014
Document Number: 001-50282 Rev. *F
VINI
Added related documentation hyperlink in page 1.
Removed missing part number CY7C1079DV33-12B2XI in Ordering
Information.
Page 14 of 15
CY7C1079DV33
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2009-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-50282 Rev. *F
Revised November 28, 2014
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 15 of 15