CY7C199CN 256-Kbit (32 K × 8) Static RAM 256-Kbit (32 K × 8) Static RAM Features General Description The CY7C199CN[1] is a high performance CMOS Asynchronous SRAM organized as 32K by 8 bits that supports an asynchronous memory interface. The device features an automatic power-down feature that reduces power consumption when deselected. ■ Fast access time: 15 ns ■ Wide voltage range: 5.0 V ± 10% (4.5 V to 5.5 V) ■ complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Transistor transistor logic (TTL) compatible inputs and outputs ■ 2.0 V data retention ■ Low CMOS standby power The CY7C199CN is available in 28-pin molded SOJ and 28-pin DIP package(s). ■ Automated power-down when deselected For a complete list of related documentation, click here. ■ Available in Pb-free 28-pin molded small outline J-lead (SOJ) and 28-pin DIP packages See the Truth Table on page 4 in this data sheet for a complete description of read and write modes. Logic Block Diagram RAM Array Sense Amps Row Decoder Input Buffer I/Ox CE Column Decoder WE Power Down Circuit OE X A X Product Portfolio Description -15 Unit Maximum access time 15 ns Maximum operating current 80 mA Maximum CMOS standby current (low power) 500 A Cypress Semiconductor Corporation Document Number: 001-06435 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 16, 2015 CY7C199CN Contents Pin Layout and Specifications ........................................ 3 Pin Description ................................................................. 3 Truth Table ........................................................................ 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 DC Electrical Characteristics .......................................... 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads .................................................................. 6 AC Test Conditions .......................................................... 6 Data Retention Characteristics ....................................... 7 Data Retention Waveform ................................................ 7 AC Electrical Characteristics .......................................... 8 Document Number: 001-06435 Rev. *J Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC® Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17 Page 2 of 17 CY7C199CN Pin Layout and Specifications 28-pin DIP 28-pin SOJ A5 1 28 VCC A5 1 28 VCC A6 2 27 WE A6 2 27 WE A7 3 26 A4 A7 3 26 A4 A3 A8 4 25 A3 A9 5 24 A2 A10 6 23 A1 A8 4 A9 25 5 24 A2 A10 6 23 A11 A1 7 22 OE A11 7 22 OE A12 8 21 A12 8 21 A0 A13 A0 9 20 CE A13 9 20 CE A14 10 19 A14 10 19 IO7 IO0 IO7 11 18 IO0 11 18 IO6 IO1 IO6 12 17 IO1 12 17 IO5 IO2 IO5 13 16 IO2 13 16 IO4 VSS IO4 14 15 IO3 VSS 14 15 IO3 Pin Description Pin Type Description AX Input Address inputs CE Control Chip Enable IOX Input or Output Data input outputs OE Control VCC DIP SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 21, 23, 24, 25, 26 20 20 11, 12, 13, 15, 16, 17, 18, 19 11, 12, 13, 15, 16, 17, 18, 19 Output enable 22 22 Supply Power (5.0 V) 28 28 VSS Supply Ground 14 14 WE Control Write Enable 27 27 Note 1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com. Document Number: 001-06435 Rev. *J Page 3 of 17 CY7C199CN Truth Table CE OE WE IOx Mode Power H X X High-Z Deselect/Power-down Stand by (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High-Z Selected, Outputs disabled Active (ICC) Document Number: 001-06435 Rev. *J Page 4 of 17 CY7C199CN Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Parameter [2] Description Value Unit TSTG Storage temperature –65 to +150 °C TAMB Ambient temperature with power applied (that is, case temperature) –55 to +125 °C VCC Core Supply voltage relative to VSS –0.5 to +7.0 V VIN, VOUT DC voltage applied to any pin relative to VSS –0.5 to VCC + 0.5 IOUT Output short-circuit current 20 VESD Static discharge voltage (in accordance with MIL-STD-883, Method 3015) > 2001 V ILU Latch-up current > 200 mA V mA Operating Range Range Ambient Temperature (TA) Commercial Industrial Voltage Range (VCC) 0 °C to 70 °C 5.0 V ± 10% –40 °C to 85 °C 5.0 V ± 10% DC Electrical Characteristics Over the Operating Range Parameter [2] Description -15 Condition Min Max Unit VIH Input HIGH voltage 2.2 VCC + 0.3 V VIL Input LOW voltage –0.5 0.8 V VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA 2.4 – V VOL Output LOW voltage VCC = Min, IOL = 8.0 mA – 0.4 V ICC VCC Operating supply current VCC = Max, IOUT = 0 mA, f = Fmax = 1/tRC – 80 mA ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE VIH, VIN VIH or VIN VIL, f = Fmax Automatic CE power-down current – CMOS Inputs Max VCC, CE VCC – 0.3 V, VIN VCC – 0.3 V, or VIN 0.3 V, f = 0 IOZ Output leakage current IIX Input leakage current ISB2 – 30 mA – 10 mA – 10 mA – 500 A GND VI VCC, output disabled –5 +5 A GND VI VCC –5 +5 A L L Note 2. VIL (min) = –2.0 V for pulse durations of less than 20 ns. Document Number: 001-06435 Rev. *J Page 5 of 17 CY7C199CN Capacitance Parameter [3] Description CIN Input capacitance COUT Output capacitance Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Max Unit 8 pF 8 Thermal Resistance Parameter [3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Conditions SOJ DIP Unit Still air, soldered on a 3 × 4.5 square inch, two–layer printed circuit board 79 69.33 °C/W 41.42 31.62 AC Test Loads Figure 1. AC Test Loads O u tp u t L o a d s O u tp u t L o a d s fo r t H Z O E , t H Z C E & t H Z W E R1 R3 VC C VC C O u tp u t C1 R2 C2 (A )* (B )* T h e v e n in E q u iv a le n t O u tp u t R th R4 A ll In p u t P u ls e s VC C VT VS S 90% 90% 10% 10% R is e T im e 1 V /n s F a ll T im e 1 V /n s * in c lu d in g s c o p e a n d jig c a p a c ita n c e AC Test Conditions Parameter C1 Description Capacitor 1 Nom Unit 30 pF C2 Capacitor 2 5 R1 Resistor 1 480 R2 Resistor 2 255 R3 Resistor 3 480 R4 Resistor 4 255 RTH Resistor Thevenin 167 VTH Voltage Thevenin 1.73 V Note 3. Tested initially and after any design or process change that may affect these parameters. Document Number: 001-06435 Rev. *J Page 6 of 17 CY7C199CN Data Retention Characteristics Parameter [4] Description VDR VCC for data retention Condition ICCDR Data retention current tCDR Chip deselect to data retention time tR Operation recovery time VCC = VDR = 2.0 V, CE VCC – 0.3 V, VIN VCC – 0.3 V or VIN 0.3 V Min Max Unit 2.0 – V – 150 A 0 – ns 200 – s Data Retention Waveform Figure 2. Data Retention Waveform VCC DATA RETENTION MODE tCDR tR CE Note 4. L-version only. Document Number: 001-06435 Rev. *J Page 7 of 17 CY7C199CN AC Electrical Characteristics Parameter [5, 6] Description –15 Min Max Unit tRC Read cycle time 15 – ns tAA Address to data valid – 15 ns tOHA Data hold from address change 3 – ns tACE CE to data valid – 15 ns tDOE OE to data valid – 7 ns OE to Low-Z [7] 0 – ns tHZOE OE to High-Z [7, 8] – 7 ns tLZCE CE to Low-Z [7] 3 – ns – 7 ns 0 – ns tLZOE [7, 8] tHZCE CE to High-Z tPU CE to Power-up tPD CE to Power-down – 15 ns tWC Write Cycle Time [9] 15 – ns tSCE CE to write end 10 – ns tAW Address setup to write end 10 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 9 – ns tSD Data setup to write end 9 – ns tHD Data hold from write end 0 – ns tHZWE WE LOW to High-Z [7, 8] – 7 ns 3 – ns tLZWE WE HIGH to Low-Z [7] Notes 5. Test Conditions are based on a transition time of 3 ns or less and timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. 6. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, tHZWE are specified as in part (b) of the Figure 1 on page 6. Transitions are measured ± 200 mV from steady state voltage. 9. The internal memory write time is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. Document Number: 001-06435 Rev. *J Page 8 of 17 CY7C199CN Timing Waveforms Figure 3. Read Cycle No. 1 [10, 11] tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Figure 4. Read Cycle No. 2 [12, 13] tRC Address CE tHZCE tACE OE tDOE tHZOE tLZOE High Z Data Out VCC Current ICC ISB High Z Data Valid tLZCE tPU tPD 50% 50% Notes 10. Device is continuously selected. OE = VIL = CE. 11. WE is HIGH for read cycle. 12. This cycle is OE controlled and WE is HIGH read cycle. 13. Address valid before or similar with CE transition LOW. Document Number: 001-06435 Rev. *J Page 9 of 17 CY7C199CN Timing Waveforms (continued) Figure 5. Write Cycle No. 1 (WE Controlled) [14, 15, 16] tWC Address tSCE CE tAW tHA tPWE tSA WE OE tHZOE Data In/Out tSD Undefined tHD Data-In Valid see footnotes Figure 6. Write Cycle No. 2 (CE Controlled) [15, 17, 18] tWC Address tSCE CE tSA tHA tAW WE tSD Data In/Out High Z Data-In Valid tHD High Z Notes 14. This cycle is WE controlled, OE is HIGH during write. 15. Data in and/or out is high impedance if OE = VIH. 16. During this period the IOs are in output state and input signals must not be applied. 17. This cycle is CE controlled. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 001-06435 Rev. *J Page 10 of 17 CY7C199CN Timing Waveforms (continued) Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [19] t WC Address tSCE CE tAW tHA t PWE tSA WE tSD Data In Out Undefined tHD Undefined See Footnotes Data In Valid see footnotes t HZWE t LZWE Note 19. The cycle is WE Controlled, OE LOW. The minimum write cycle time is the sum of tHZWE and tSD. Document Number: 001-06435 Rev. *J Page 11 of 17 CY7C199CN Ordering Information Contact local sales representative regarding availability of these parts. Speed (ns) 15 Package Diagram Ordering Code Package Type Power Option Operating Range CY7C199CN-15PXC 51-85014 28-pin DIP (6.9 × 35.6 × 3.5 mm), Pb-free Standard Commercial CY7C199CNL-15VXI 51-85031 28-pin (300-Mil) Molded SOJ, Pb-free Low Power Industrial Ordering Code Definitions CY 7 C 1 99 CN L - XX X X X Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: X = P or V P = 28-pin DIP V = 28-pin Molded SOJ Speed: 15 ns L = low power Process Technology: CN = 0.25 µm Technology 99 = 256 K bit density with data width × 8 bits Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company: CY = Cypress Document Number: 001-06435 Rev. *J Page 12 of 17 CY7C199CN Package Diagrams Figure 8. 28-pin SOJ (300 Mils) V28.3 Package Outline, 51-85031 51-85031 *F Document Number: 001-06435 Rev. *J Page 13 of 17 CY7C199CN Package Diagrams (continued) Figure 9. 28-pin PDIP (300 Mils) Package Outline, 51-85014 51-85014 *G Document Number: 001-06435 Rev. *J Page 14 of 17 CY7C199CN Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static Random Access Memory mA milliampere SOJ Small Outline J-lead mV millivolt VFBGA Very Fine-Pitch Ball Grid Array mW milliwatt Write Enable ns nanosecond WE Document Number: 001-06435 Rev. *J Symbol Unit of Measure pF picofarad V volt W watt Page 15 of 17 CY7C199CN Document History Page Document Title: CY7C199CN, 256-Kbit (32 K × 8) Static RAM Document Number: 001-06435 Revision ECN Submission Date Orig. of Change ** 430363 See ECN NXR New data sheet. *A 684342 See ECN VKN Added Automotive-A Information Updated Ordering Information Table Description of Change *B 839904 See ECN VKN Added tDOE spec for Automotive-A part in AC Electrical characteristics table *C 2896044 03/19/2010 NXR Updated Ordering Information Table Updated Package Diagram *D 3108898 12/13/2010 PRAS Added Ordering Code Definitions. *E 3198636 03/17/11 PRAS Dislodged Automotive device information to 001-67737 Updated template and styles. *F 3246329 05/04/2011 PRAS Additional information on ISB1, ISB2 with respect to L parts *G 3302830 08/02/2011 RAME Removed all information related to 28-pin TSOP 1. Removed all information related to 20 ns speed bin. Removed the following parts from ordering information table. CY7C199CN-15VXC CY7C199CN-20ZXI Removed spec 51-85071. *H 4318563 03/25/2014 VINI Updated Package Diagrams: spec 51-85014 – Changed revision from *F to *G. Updated to new template. Completing Sunset Review. *I 4546472 10/28/2014 VINI Updated Maximum Ratings: Referred Note 2 in “Parameter” column. Updated AC Electrical Characteristics: Added Note 6 and referred the same note in “Parameter” column. *J 4576406 01/16/2015 VINI Added related documentation hyperlink in page 1. Updated Figure 8 in Package Diagrams (spec 51-85031 *E to *F). Document Number: 001-06435 Rev. *J Page 16 of 17 CY7C199CN Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06435 Rev. *J Revised January 16, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 17 of 17