4. Incremental ADC
Incremental ADC Data Sheet
ADCINC
Copyright © 2008-2009 Cypress Semiconductor Corporation. All Rights Reserved.
PSoC® Blocks
Resources
CapSense
I2C/SPI
Timer
API Memory
Comparator
Flash
RAM
Pins (per
External IO)
CY8C20x96, CY8C20x66, CY8C20x46, CY8C20x36, CY7C643/4/5xx, CY7C60413, CY7C60424, CY7C6053x,
CYONS2010, CYONSTB2010, CYONS2011, CYONSTB2011, CYONSFN2051, CYONSFN2053, CYONSFN2061,
CYONSFN2151, CYONSFN2161, CYONSFN2162, CY8CTST200, CY8CTMG2xx
-
-
-
-
1000
100
1
For one or more fully configured, functional example projects that use this User Module go to
www.cypress.com/psocexampleprojects.
Features and Overview
• 8 to 10-bit resolution
• Sample rate up to 5.859 ksps (10-bit resolution)
• Sample rate up to 23.4375 ksps (8-bit resolution)
• Input range 0 to 1.2V
• Internal clock divider with frequencies of 6, 3, and 1 MHz
The ADCINC User Module implements an incremental analog to digital converter with a selectable range
of 8 to 10 bits and signed or unsigned data formats. The input voltage range is fixed at 0 to 1.2V. The
ADCINC programming interface allows the user to select between polling the SPC or checking a status bit
that is set with the SPC interrupt.
This ADC is actually part of the SPC. All access to control and recover the result is through two registers
used to interface the main M8C processor and the SPC. The ADC consist of a timer that determines the
conversion time and the resolution, a counter to accumulated the result, and an analog modulator.
16-Bit
Timer
PMUX
16-Bit
Counter
INP
agnd
INN
COMP
NMUX
Vin
agnd
agnd
Vrefp
Vrefn
ADCINC Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-45836 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 12, 2009
Incremental ADC
The ADCINC User Module contains an integrator block, one comparator with positive input set by the
PMUX and negative input set by the NMUX. The input to the integrator stage comes from the Analog
Global Input Mux with full scale input being 0V to 1.2V. The ADC is run for a number of cycles set by the
Timer depending upon the resolution of the ADC desired by the user. A counter counts the number of trips
by the comparator, which is proportional to the input voltage. The SPC clock speed is 36 MHz and is
divided down to 1 to 6 MHz for ADCINC operation.
Functional Description
The range of the ADCINC is set at 0 to 1.2V. The analog block is configured as a integrator that can be
reset. Depending on the output polarity, the reference control is configured so that the reference voltage is
either added or subtracted from the input and placed in the integrator. This reference control attempts to
pull the integrator output back towards AGND. If the integrator is operated 2Bits times and the output
voltage comparator is positive "n" of those times, the residual voltage (Vresid) at the output is:
V in n
Result = --------- ( 2 )
V ref
Equation 1
This equation states that the range of this ADC is 0 to Vref, the resolution (LSB) is Vref/2n, and the voltage
on the output at the end of the computation is defined as the residue. Since Vresid is always less than Vref,
Vresid/2Bits less than half a LSB and can be ignored.
The accumulated value is sampled at the start and finish of the integrate time. A single cycle is added to
reset the integrator and process the answer.
Timing for ADCINC
The PWM is set up to generate an interrupt every 2n counts. This causes the input to be sampled 64
times. This defines one integrate cycle. The decimator counter is set up to accumulate 2n/64 bits of these
integrate cycles. The accumulated value is sampled at the start and finish of the integrate time. A single
cycle is added to reset the integrator and process the answer.
Because the ACDINC control is interrupt based and the sample time is relatively long, it is unreasonable to
expect the processor to wait while a sample is being processed. The primary communication between the
ADC routine and the main program is a data-available flag that may be polled. APIs are available to check
the data flag and retrieve data.
The data handler was designed to be poll based. If an interrupt-based data handler is desired, applicationspecific data handler code can be added to the interrupt routine _ADCINC_ADConversion_ISR, located in
the assembly file adcincint.asm. The place to insert code is clearly marked.
The frequency domain magnitude plot below normalizes the frequency so the sample rate, Fnom = 1.0.
The -3 dB point occurs at 0.443 × Fnom and zeros of the function occur at each integer multiple of FS.
Since the ADCINC PWM is set for a resolution of 14 bits, it actually samples 16385 times faster than the
nominal output rate, the Nyquist limit is 8192 higher, 13 octaves above Fnom, which significantly reduces
the requirements for an anti-alias filter. The Nyquist limit is 12 octaves for 13 bits of resolution, 11 octaves
for 12 bits of resolution, and so on.
Document Number: 001-45836 Rev. *C
Page 2 of 7
Incremental ADC
DC and AC Electrical Specifications
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise,
the specifications are for the entire device voltage and temperature operating range: –40°C <= TA <=
85°C, 1.71V <= Vdd <= 5.5V.
Electrical Specification
Description
Min
Typ
Max
Units
VREFADC
V
5
pF
Conditions and Notes
Input
Input Voltage Range
0
Input Capacitance
Input Resistance
1/
1/
1/
(500fF*Data (400fF*Data (300fF*Data
-Clock)
-Clock)
-Clock)
Ω
1.2V ± 5%
Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution.
Reference
ADC Reference Voltage
1.14
1.26
V
2.25
6
MHz
Source is chip’s internal main
oscillator. See AC ChipLevel Specifications for
accuracy.
Conversion Rate
Data Clock
8-Bit Sample Rate
23.4375
ksps
Data Clock set to 6 MHz.
Sample Rate = 0.001/
(2^Resolution/Data Clock)
10-Bit Sample Rate
5.859
ksps
Data Clock set to 6 MHz.
Sample Rate = 0.001/
(2^Resolution/Data Clock)
Can be set to 8-, 9-, or 10-bit
DC Accuracy
Resolution
8
10
bits
Differential Nonlinearity
-1
+2
LSB
Integral Nonlinearity
-2
+2
LSB
Offset Error
0
76.8
LSB
Gain Error
-5
12.8
5
10-bit resolution
%FSR For any resolution
Power
Operating Current
2.1
2.6
mA
Power Supply Rejection
Ratio
24
dB
PSRR (Vdd>3.0V)
30
dB
PSRR (Vdd < 3.0V)
Placement
The ADCINC User Module is implemented in software and does not require placement.
Document Number: 001-45836 Rev. *C
Page 3 of 7
Incremental ADC
Parameters and Resources
After the ADCINC is placed, these parameters must be configured for proper operation: ADC Resolution,
and Clock Divider.
ADC Resolution
This selection determines the data format of the return result. Valid resolution options are from 8 to 10 bits.
Set by cap select (Cs Select) and Timer period.
Clock Divider
The Data Clock determines the sample rate. The maximum DataClock that can be used is 6 MHz. This is
due to limitations of the Switched Cap blocks. The maximum sample rate for each of the various bit rates
are listed in the following table. Operation at absolute maximum sample rate results in reduced accuracy
and does not meet the INL/DNL specs listed in the AC and DC electrical specifications.
Resolution
Max Counts
Recommended Maximum Sample Rate
8-bit
255
23.43 ksps
9-bit
511
11.71 ksps
10-bit
1023
5.85 ksps
The sample window determines the normal mode frequencies the ADC rejects. It is defined as:
Bits
2
SampleRate = ---------------------------DataClock
Equation 2
Application Programming Interface
The Application Programming Interface (API) routines are provided as part of the user module to allow the
designer to deal with the module at a higher level. This section specifies the interface to each function
together with related constants provided by the “include” files.
Each time a user module is placed, it is assigned an instance name. By default, PSoC Designer assigns
the ADCINC_1 to the first instance of this user module in a given project. It can be changed to any unique
value that follows the syntactic rules for identifiers. The assigned instance name becomes the prefix of
every global function name, variable and constant symbol. In the following descriptions the instance name
has been shortened to ADCINC for simplicity.
Note
In this, as in all user module APIs, the values of the A and X register may be altered by calling an
API function. It is the responsibility of the calling function to preserve the values of A and X before
the call if those values are required after the call. This “registers are volatile” policy was selected
for efficiency reasons and has been in force since version 1.0 of PSoC Designer. The C compiler
automatically takes care of this requirement. Assembly language programmers must ensure their
code observes the policy, too. Though some user module API function may leave A and X
unchanged, there is no guarantee they may do so in the future.
Document Number: 001-45836 Rev. *C
Page 4 of 7
Incremental ADC
ADCINC_Start
Description:
The ADCINC for this device is internally constructed to connect to only two sources:
1. Internal temp sensor
2. Analog mux bus
If the analog Mux bus is chosen, an external pin may also be connected to the same mux bus to provide an external sense point.
C Prototype:
void ADCINC_Start (BYTE bMux)
Assembly:
mov
A, bMux
lcall ADCINC_Start
Parameters:
bMux: One byte that specifies the connection chosen as described above. Symbolic names provided
in C and assembly, and their associated values, are listed in the following table:
Symbolic Name
Value
ADCINC_INPUT_ANALOG_BUS
0
ADCINC_INPUT_TEMP_SENSOR
1
Return Value:
None
Side Effects:
The A and X registers may be modified by this or future implementations of this function. The same is
true for all RAM page pointer registers in the Large Memory Model. When necessary, it is the calling
function's responsibility to preserve the values across calls to fastcall16 functions.
ADCINC_Stop
Description:
Disables the ADC in the SPC.
C Prototype:
void ADCINC_Stop (void)
Assembly:
lcall ADCINC_Stop
Parameters:
None
Return Value:
None
Side Effects:
The A and X registers may be modified by this or future implementations of this function. The same is
true for all RAM page pointer registers in the Large Memory Model. When necessary, it is the calling
function's responsibility to preserve the values across calls to fastcall16 functions.
Document Number: 001-45836 Rev. *C
Page 5 of 7
Incremental ADC
ADCINC_GetSample
Description:
Runs the ADC until one ADC sample is complete.
C Prototype:
WORD ADCINC_GetSamples (void)
Assembly:
lcall ADCINC_GetSample
Parameters:
None
Return Value:
WORD (ADC_reading)
Side Effects:
The A and X registers may be modified by this or future implementations of this function. The same is
true for all RAM page pointer registers in the Large Memory Model. When necessary, it is the calling
function's responsibility to preserve the values across calls to fastcall16 functions. Currently, only the
CUR_PP page pointer register is modified.
Sample Firmware Source Code
The following sample code polls the Flag register and sends the data to a routine that shifts the data out
one of the I/O pins:
include "m8c.inc"
include "PSoCAPI.inc"
; Part specific constants and macros
; PSoC API definitions for all User Modules
export _main
_main:
M8C_SetBank1
mov reg[MUX_CR1], 0x10
; //connect p1_4 to the mux bus
M8C_SetBank0
M8C_EnableGInt
; enable global interrupts
mov a,ADCINC_INPUT_ANALOG_BUS ; set ADC Mode
call ADCINC_Start
loop1:
call ADCINC_GetSample ;places WORD data in A and X
jmp loop1
Here is a similar project written in C:
//-----------------------------------------------------------------------// Sample C Code for the ADCINC
// Continuously Sample input voltage
//
//-----------------------------------------------------------------------#include <m8c.h>
// part specific constants and macros
#include "PSoCAPI.h"
// PSoC API definitions for all User Modules
INT val;
void main()
{
Document Number: 001-45836 Rev. *C
Page 6 of 7
Incremental ADC
// Insert your main routine code here.
val = 0xaa;
LCD_Start();
LCD_Position(1,0);
LCD_PrCString("value = ");
//connect the pins up
M8C_SetBank1;
MUX_CR1 = 0x10; //connect p1_4 to the mux bus
M8C_SetBank0;
ADCINC_Start(ADCINC_INPUT_ANALOG_BUS);
val = ADCINC_GetSample();
LCD_Position(1,8);
LCD_PrHexInt(val);
val = ADCINC_GetSample();
LCD_Position(1,8);
LCD_PrHexInt(val);
}
while(1)
{
val = ADCINC_GetSample();
LCD_Position(1,8);
LCD_PrHexInt(val);
}
Configuration Registers
This ADC has no user registers. Any settings must be performed through the API.
Document Number: 001-45836 Rev. *C
Revised October 12, 2009
Page 7 of 7
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems
where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.