CMPPRG User Module Example Project Name: CMPPRG_Example Programming Language: C Associated Part Families: CY8C24x23,CY8C27x43,CY8C29x66, CY8C24x94,CY8C21x34 ® TM Software Version: PSoC Designer 5.2 Related Hardware:CY3210 PSoCEval1 Board Project Objective This project demonstrates the usage of the CMPPRG user module with a DigBuf of PSoC® device. Overview In this project, a CMPPRG is used to compare the selected input against a programmable reference threshold, the measured voltage signal from potentiometer that has been input from a pin, the comparator output is routed to a pin through a DigBuf user module. The output reflects the comparison between the input and the threshold that has been set with the CMPPRG. User Module List and Placement This table lists the user modules used in this project and the hardware resources occupied by each user modules. User Module Placement CMPPRG ACB00 DigBuf DBB00 User Module Parameter Settings This tables show the user module parameter settings for each user module used in the project. CMPPRG Parameter Value Comments AnalogBus Disable Not used CompBus ComparatorBus_0 Output to DigBuf Input AnalogColumn_ InputMUX-0 Input from Pin_0_1 LowLimit AGND Set LowLimit to AGND RefValue 0.125 Refer to 0.125 DigBuf 1 CMPPRG Example Parameter Value Comments Default Load Status Enable Default Input1 ComparatorBus_0 Typically set input from CMPPRG Input 2 Disable Not used Input ClockSync Unsynchronized Not used Output 1 Row_0_Output_0 Row_0_Output_0 Output 2 None Not used InvertInput1 Normal Default Global Resources Important Global Resources Parameter Value Comments Power Setting 5.0 V/24 MHz Default, Vcc = 5.0 V, IMO = 24 MHz CPU_Clock SysClk/8 Divide SysClock by 8 = 3 MHz 32K_Select Internal Default, not used PLL_Mode Disable Default, not used Sleep_Timer 512_Hz Default, not used VC1= SysClk/N 16 Divide SysClock by 16 VC2= VC1/N 16 Divide VC1 by 16 VC3 Source VC2 Set source of VC3 as VC2 VC3 Divider 256 Divide VC2 by 256 to produce a clock of 36 KHz Sysclk Source Internal Sysclck using IMO Sysclk*2 Disable No Default, not used Analog Power SC On/Ref Low Set the maximum operating power of analog blocks to Ref Low Default, but here Ref High = 3.8 V Ref Low = 1.2 V AGND = 2.5 V Ref Mux (Vdd/2)+/-BandGap AGndBypass Disable Default, not used Op-Amp Bias Low Default, not used A_Buff_Power Low Default, not used SwitchModePump OFF Default, not used Trip Voltage[LVD (SMP)] 4.81 V (5.00 V) Default, Will reset if VCC below 4.81 V LVDThrottleBack Disable Default, not used Watchdog Enable Disable Default, not used Refer to AN2219 All the global resources are left at the default value in this project. 2 CMPPRG Example Pin Configuration Pin Out Pin Select Drive Direction Port 0_0 GlobalOutEven_0 Strong Output Port 0_1 Analog Input High Z Analog Input Hardware Connections The schematic of the project is shown here. 3 CMPPRG Example The project can be tested using CY3210 – PSoC Eval1 board. To test the project, make the following connections: Connect P0 [1] of J6 to VR of J5 Connect P0 [0] of J6 to LED1 of J5 Operation On program execution, all hardware settings from the device configuration are loaded into the device and main.c is executed. The following operations are performed inside main.c. 1. Start CMPPRG user module with CMPPRG_Start(CMPPRG_MEDPOWER); 2. Start DigBuf with DigBuf_Start(); Testing the Project To test the project using CY3210 PSoCEval1 board, follow these steps: Make the connections as shown in the Hardware Settings section. Change the position of potentiometer and observe the status of LED, The LED turns ON while the input voltage is higher than 2.8125 V. The threshold voltage is configurable by configuring the “LowLimit” and the “RefValue” of CMPPRG, equation for calculating the Vthreshold is given in CMPPRG user module datasheet as, 4 CMPPRG Example PSoC is a registered trademark of Cypress Semiconductor Corp. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. 5