Converting STK10C68 to STK12C68 Introduction This document provides guidance on converting a design that is currently using the STK10C68 to the Simtek recommended part STK12C68. STK10C68 Package Comparison no No, (yes but undocumented) No, (yes but undocumented) No Yes 68 STK12C68 Yes, but can be disabled Yes Yes Yes No r u ST si K1 ng 2 C C68 Y1 4E is i 25 n N 6L RN A D in S st ta ea tu d s. of ST K Autostore Software store Software recall Hardware store HSB based Hardware store NE based 12 C Function Category . Feature set and limitations of the STK10C68 The 600 mil dip package is available in the STK12C68 and the STK10C68. Other packages that take less PCB area also exist such as 300 mil CDIP/PDIP and the 350 mil SOIC. Package S STK10C68 Available STK12C68 Available W P C Not Available Available Not Available Not Available Not Available Not Available PKG Code 350 mil SOIC – 28 pin si de 600 mil pdip -- 28 pin 300 mil pdip -- 28 pin 300 mil cdip -- 28 pin Notes Surface mount – smallest PCB area Through hole Through hole Through hole on Issues to consider during the conversion C The key difference is that the STK10C68 has a different hardware store mechanism than the STK12C68. STK12C68 will normally autostore so powering via VCAP and having VCCx open will prevent autostore. Logic explained here creates a signal to activate /HSB(hardware store) by combining the /G, /NE, /E, and /W signals used with the STK10C68. This will activate the same feature as in the STK12C68 (NE based hardware store) by instead activating /HSB. It is essential that the logic output be glitch free. In many implementations, /NE and /E signal is usually a logic decode of uppermost addresses and any decode from multiple address lines can glitch. /W signal is usually falling later in the cycle glitch-free strobe from the MPU. Please check that there is sufficient time from address change to /W falling to gate out /E and /NE glitches. This will ensure glitch free leading edge. Also, be sure that /W rises before the address changes. (Delay in the /W signal can cause problems for the rising edge.) This is the normal situation for most MPUs (check your MPU datasheet). The /HSB signal should go low only when /G is high and /E, /NE, and /W are all low. This low going pulse will activate the /HSB input which initiates a hardware store when low just like the STK10C68 does in response to /G being high, /NE, /E, and /W being low. Hardware recall is not supported in this conversion. There is no external pin on the STK12C68 to support hardware recall. Recall is automatic on power up so is in most cases not needed or used. If needed, contact Simtek applications engineering for recommendations. Application Note Number MA0016 0.1 Improper Timing example The following timing diagram shows an unwanted situation just before the low going write pulse. /HSB output from the OR gate should not glitch by having /WRITE extend into the next cycle. This can occur if there are too much delay in the /WRITE signal. Normally, /WRITE output from an MPU will terminate well before any address change. Be sure to check the timing of address changes to /WRITE rising. This time should always be negative and any positive values risk activating /HSB inadvertently. decoding glitches /NVCE ( /NVCE: logical decode of high addresses ) /WRITE /HSB 12 C Schematic changes for conversion: 68 . Error: /WRITE delayed letting glitches through r u ST si K1 ng 2 C C68 Y1 4E is i 25 n N 6L RN A D in S st ta ea tu d s. of ST K The larger memory is used with identical function but with two high order address bits tied inactive. The choice of package is open with the “S” package being the most area efficient surface mount choice. U1 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 10 9 8 7 6 5 4 3 25 24 21 23 2 /READ /CE /WRITE 22 20 27 NE VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 G E W 28 from power plane +5v 11 12 13 15 16 17 18 19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 14 VSS C1-by pass 0.1 uF must use gnd plane de /NVCE si STK10C68 C on Before Conversion schematic Application Note Number MA0016 0.1 /NVCE /CE 10 9 8 7 6 5 4 3 25 24 21 23 2 /READ /CE /WRITE 26 22 20 27 U2 1 /WRITE 1 4 5 OR4 VCAP A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 HSB G E W VCCx DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS 28 11 12 13 15 16 17 18 19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 14 STK12C68-W45I NOT must use gnd plane r u ST si K1 ng 2 C C68 Y1 4E is i 25 n N 6L RN A D in S st ta ea tu d s. of ST K After Conversion schematic 68 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 12 C U3 /READ 2 3 U1 1 . from power plane +5v closest to pin Moved from VCC C1-by pass 0.1uF C on si de On the next page, pin by pin comparisons of the two show all pins are the same except for the two additional address lines. Application Note Number MA0016 0.1 Corresponding pin Connection Pin for pin comparison of the two parts is given in the table below: 68 . Hook VCAP to system VCC Unhook /NE and connect to OR gate input (see schematic) No change “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ Connect to OR gate input (See schematic) “ Connect to OR gate input (See schematic) No change No change “ Connect to OR gate output (see schematic above) Also connect to OR gate input 12C68 VCCx should be open r u ST si K1 ng 2 C C68 Y1 4E is i 25 n N 6L RN A D in S st ta ea tu d s. of ST K 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 de si on A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 E# A10 G# A11 A9 A8 HSB W# VCCX C A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 E# A10 G# NC A9 A8 HSB W# VCC Comments 12 C STK10C68 STK12C68 Pin NAME NAME /NE VCAP 1 Application Note Number MA0016 0.1