CY7C056V CY7C057V CY7C037V CY7C038V3.3 V 16 K / 32 K × 36 FLEx36™ Asynchronous Dual-Port Static RAM CY7C056V CY7C057V 3.3 V 16 K / 32 K × 36 FLEx36™ Asynchronous Dual-Port Static RAM 3.3 V 16 K / 32 K × 36 FLEx36™ Asynchronous Dual-Port Static RAM Features ■ ■ True dual-ported memory cells that allow simultaneous access of the same memory location ■ 16 K × 36 organization (CY7C056V) ■ 32 K × 36 organization (CY7C057V) ■ 0.25-micron Complimentary metal oxide semiconductor (CMOS) for optimum speed/power ■ High-speed access: 12/15 ns ■ Low operating power ❐ Active: ICC = 250 mA (typical) ❐ Standby: ISB3 = 10 A (typical) ■ Fully asynchronous operation ■ Automatic power-down ■ Expandable data bus to 72 bits or more using Master/Slave Chip Select when using more than one device ■ On-chip arbitration logic ■ Semaphores included to permit software handshaking between ports ■ INT flag for port-to-port communication ■ Byte select on left port ■ Bus matching on right port ■ Depth expansion via dual chip enables ■ Pin select for Master or Slave ■ Commercial and Industrial temperature ranges ■ Available in 144-pin Thin quad plastic flatpack (TQFP) or 172-ball ball grid array (BGA) ■ Pb-free packages available Compact packages: ❐ 144-pin TQFP (20 × 20 × 1.4 mm) ❐ 172-ball BGA (1.0-mm pitch) (15 × 15 × 0.51 mm) Functional Description The CY7C056V and CY7C057V are low-power CMOS 16K and 32K x 36 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 36-bit dual-port static RAMs or multiple devices can be combined in order to function as a 72-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 72-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE) , Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt Flag (INT) permits communication between ports or systems by means of a mailbox. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic Power-down feature is controlled independently on each port by Chip Select (CE0 and CE1) pins. The CY7C056V and CY7C057V are available in 144-pin Thin quad plastic flatpack (TQFP) and 172-ball ball grid array (BGA) packages. For a complete list of related resources, click here. Note 1. CE is LOW when CE0 VIL and CE1 VIH. Cypress Semiconductor Corporation Document Number: 38-06055 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 18, 2015 CY7C056V CY7C057V Logic Block Diagram R/WL B0–B3 CE0L CE1L R/WR Left Port Control Logic CEL OEL I/O0L–I/O8L I/O9L–I/O17L  9 9 9 I/O Control I/O Control 9 I/O27L–I/O35L A0L–A13/14L 9 9 I/O18L–I/O26L Right Port Control Logic 14/15 CER True Dual-Ported RAM Array 14/15 OER BA WA Bus Match 9 9 Address Decode CE0R CE1R 9/18/36 I/OR BM SIZE Address Decode 14/15  A0R–A13/14R 14/15 Interrupt Semaphore Arbitration SEML SEMR BUSYR INTR BUSYL INTL M/S Notes 2. A0–A13 for 16K; A0–A14 for 32K devices. 3. BUSY is an output in Master mode and an input in Slave mode. Document Number: 38-06055 Rev. *J Page 2 of 29 CY7C056V CY7C057V Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 6 Selection Guide ................................................................ 6 Architecture ...................................................................... 7 Functional Overview ........................................................ 7 Write Operation ........................................................... 7 Read Operation ........................................................... 7 Interrupts ..................................................................... 8 Busy ............................................................................ 8 Master/Slave ............................................................... 8 Semaphore Operation ................................................. 9 Bus Match Operation ................................................. 11 Maximum Ratings ........................................................... 12 Operating Range ............................................................. 12 Electrical Characteristics ............................................... 12 Capacitance .................................................................... 13 AC Test Loads and Waveforms ..................................... 13 Data Retention Mode ...................................................... 14 Timing .............................................................................. 14 Switching Characteristics .............................................. 15 Switching Waveforms .................................................... 17 Document Number: 38-06055 Rev. *J Ordering Information ...................................................... 23 16 K × 36 3.3 V Asynchronous Dual Port SRAM ...... 23 32 K × 36 3.3 V Asynchronous Dual Port SRAM ...... 23 Ordering Code Definitions ......................................... 23 Package Diagrams .......................................................... 24 Acronyms ........................................................................ 26 Document Conventions ................................................. 26 Units of Measure ....................................................... 26 Errata ............................................................................... 27 Part Numbers Affected .............................................. 27 Qualification Status ................................................... 27 Errata Summary ........................................................ 27 Document History Page ................................................. 28 Sales, Solutions, and Legal Information ...................... 29 Worldwide Sales and Design Support ....................... 29 Products .................................................................... 29 PSoC® Solutions ...................................................... 29 Cypress Developer Community ................................. 29 Technical Support ..................................................... 29 Page 3 of 29 CY7C056V CY7C057V Pin Configurations I/O33L I/O34L I/O35L A0L A1L A2L A3L A4L A5L A6L A7L B0 B1 B2 B3 OEL R/WL VDD VSS VSS CE0L CE1L M/S SEML INTL BUSYL A8L CY7C056V (16 K × 36) CY7C057V (32 K × 36) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 I/O33R I/O34R I/O35R A0R A1R A2R A3R A4R A5R A6R A7R BM SIZE WA BA OER R/WR VDD VSS VDD CE0R CE1R VDD SEMR INTR BUSYR A8R A9R A10R A11R A12R A13R NC  I/O26R I/O25R I/O24R I/O8R VDD I/O18R I/O19R I/O20R I/O21R VSS I/O22R I/O23R I/O5R I/O6R I/O7R I/O0L I/O0R I/O1R I/O2R I/O3R I/O4R VSS I/O5L VSS I/O4L I/O3L I/O2L I/O1L I/O19L I/O18L VDD I/O8L I/O7L I/O6L I/O21L I/O20L I/O23L I/O22L VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A9L A10L A11L A12L A13L NC  I/O26L I/O25L I/O24L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 I/O32L I/O31L VSS I/O30L I/O29L I/O28L I/O27L VDD I/O17L I/O16L I/O15L I/O14L VSS I/O13L I/O12L I/O11L I/O10L I/O9L I/O9R I/O10R I/O11R I/O12R I/O13R VSS I/O14R I/O15R I/O16R I/O17R VDD I/O27R I/O28R I/O29R I/O30R VSS I/O31R I/O32R Figure 1. 144-pin TQFP pinout (Top View) Notes 4. This pin is A14L for CY7C057V. 5. This pin is A14R for CY7C057V. Document Number: 38-06055 Rev. *J Page 4 of 29 CY7C056V CY7C057V Pin Configurations (continued) Figure 2. 172-ball BGA pinout (Top View) 1 2 3 4 5 6 A I/O32L I/O30L NC VSS I/O13L VDD B A0L I/O33L I/O29 I/O17L C NC A1L I/O31L I/O27L D A2L A3L I/O35L I/O34L E A4L A5L NC B0L NC F VDD A6L A7L B1L NC G OEL B2L B3L H VSS R/WL J A9L K 8 I/O11L I/O11R I/O9R 10 11 12 13 14 VDD I/O13R VSS NC I/O30R I/O32R I/O29R I/O33R A0R I/O27R I/O31R A1R NC I/O34R I/O35R A3R A2R NC BM NC A5R A4R NC SIZE A7R A6R VDD CE0L CE0R BA WA OER A8L CE1L CE1R A8R R/WR VSS A10L VSS M/S NC NC VDD VDD A10R A9R A11L A12L NC SEML NC NC SEMR NC A12R A11R L BUSYL A13L INTL I/O26L M NC NC I/O22L I/O18L NC N I/O24L I/O20L I/O8L I/O6L P I/O23L I/O21L NC VSS NC I/O9L 9 I/O17R Document Number: 38-06055 Rev. *J I/O14L I/O12L 7 I/O12R I/O14R I/O15L I/O10L I/O10R I/O15R I/O28L I/O16L VSS VSS NC I/O25L I/O19L I/O16R I/O28R NC NC NC NC VSS VSS I/O19R I/O25R I/O26R INTR A13R BUSYR I/O7L I/O2L I/O2R I/O7R NC I/O18R I/O22R NC NC I/O5L I/O3L I/O0L I/O0R I/O3R I/O5R I/O6R I/O8R I/O20R I/O24R I/O4L VDD I/O1L I/O1R VDD I/O4R VSS NC I/O21R I/O23R Page 5 of 29 CY7C056V CY7C057V Pin Definitions Left Port Right Port Description A0L–A13/14L A0R–A13/14R Address (A0–A13 for 16K; A0–A14 for 32K devices) SEML SEMR Semaphore Enable CE0L, CE1L CE0R, CE1R Chip Enable (CE is LOW when CE0 VIL and CE1 VIH) INTL INTR Interrupt flag BUSYL BUSYR Busy flag I/O0L–I/O35L I/O0R–I/O35R Data bus input/output OEL OER Output Enable R/WL R/WR Read/Write Enable B0–B3 Byte select inputs. Asserting these signals enables read and write operations to the corresponding bytes of the memory array. BM, SIZE See bus matching for details. WA, BA See bus matching for details. M/S Master or Slave select VSS Ground VDD Power Selection Guide CY7C056V CY7C057V -12 CY7C056V CY7C057V -15 Unit Maximum access time 12 15 ns Typical operating current 250 240 mA Typical standby current for ISB1 (Both ports TTL level) 55 50 mA Typical standby current for ISB3 (Both ports CMOS level) 10 10 A Description Document Number: 38-06055 Rev. *J Page 6 of 29 CY7C056V CY7C057V Architecture Functional Overview The CY7C056V and CY7C057V consist of an array of 16K and 32K words of 36 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE0/CE1, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE0/CE1. Each port is provided with its own Output Enable control (OE), which allows data to be read from the device. Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE0 and CE1 pins (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Table 1. Non-Contending Read/Write  Inputs Outputs B0, B1, B2, B3 SEM Operation CE R/W OE I/O0–I/O35 H X X X H High Z Deselected: Power-down X X X All H H High Z Deselected: Power-down L L X H/L H Data in and High Z L L X All L H Data in Write to selected bytes only Write to all bytes L H L H/L H Data out and High Z L H L All L H Data out Read selected bytes only X X H X X High Z H H L X L Data out Read data in semaphore flag X H Read all bytes Outputs disabled L All H L Data out Read data in semaphore flag H X X L Data in Write DIN0 into semaphore flag X X All H L Data in Write DIN0 into semaphore flag X Any L L L X Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE Not allowed is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Note 6. CE is LOW when CE0 VIL and CE1 VIH. Document Number: 38-06055 Rev. *J Page 7 of 29 CY7C056V CY7C057V Interrupts The upper two memory locations may be used for message passing. The highest memory location (3FFF for the CY7C056V, 7FFF for the CY7C057V) is the mailbox for the right port and the second-highest memory location (3FFE for the CY7C056V, 7FFE for the CY7C057V) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin.The operation of the interrupts and their interaction with Busy are summarized in Table 2. Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH) [7, 8] Function Left Port Right Port R/WL CEL OEL A0L–13L/14L INTL R/WR CER OER A0R–13R/14R INTR Set right INTR flag L L X 3FFF (7FFF) X X X X X L Reset right INTR flag X X X X X X L L 3FFF (7FFF) H Set left INTL flag X X X X L L L X 3FFE (7FFE) X 3FFE (7FFE) H X X X X X Reset left INTL flag X L L Busy Master/Slave The CY7C056V and CY7C057V provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ Chip Enables are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Notes 7. CE is LOW when CE0 VIL and CE1 VIH. 8. A0L–14L and A0R–14R, 7FFF/7FFE for the CY7C057V. 9. If BUSYL=L, then no change. 10. If BUSYR=L, then no change. Document Number: 38-06055 Rev. *J Page 8 of 29 CY7C056V CY7C057V normal semaphore access, CE must remain HIGH during SEM LOW. A CE active semaphore access is also available. The semaphore may be accessed through the right port with CE0R/CE1R active by asserting the Bus Match Select (BM) pin LOW and asserting the Bus Size Select (SIZE) pin HIGH. The semaphore may be accessed through the left port with CE0L/CE1L active by asserting all B0–3 Byte Select pins HIGH. A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. Semaphore Operation The CY7C056V and CY7C057V provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a 0), it assumes control of the shared resource, otherwise (reads a 1) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a 1), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a 1 will appear at the same semaphore address on the right port. That semaphore can now only be modified by the port showing 0 (the left port in this case). If the left port now relinquishes control by writing a 1 to the semaphore, the semaphore will be set to 1 for both ports. However, if the right port had requested the semaphore (written a 0) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches. For Table 3. Semaphore Operation Example I/O0–I/O8 Left I/O0–I/O8 Right No action Function 1 1 Semaphore free Status Left port writes 0 to Semaphore 0 1 Left port has semaphore token Right port writes 0 to Semaphore 0 1 No change. Right side has no write access to Semaphore Left port writes 1 to Semaphore 1 0 Right port obtains semaphore token Left port writes 0 to Semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to Semaphore 0 1 Left port obtains semaphore token Left port writes 1 to Semaphore 1 1 Semaphore free Right port writes 0 to Semaphore 1 0 Right port has semaphore token Right port writes 1 to Semaphore 1 1 Semaphore free Left port writes 0 to Semaphore 0 1 Left port has semaphore token Left port writes 1 to Semaphore 1 1 Semaphore free Note 11. CE is LOW when CE0 VIL and CE1 VIH. Document Number: 38-06055 Rev. *J Page 9 of 29 CY7C056V CY7C057V Table 4. Right Port Configuration [12, 13, 14] BM SIZE Configuration I/O Pins Used 0 0 × 36 (standard) I/O0–35 0 1 × 36 (CE active SEM mode) I/O0–35 1 0 × 18 I/O0–17 1 1 ×9 I/O0–8 Table 5. Right Port Operation Configuration WA BA Data Accessed  I/O Pins Used × 36 X X DQ0–35 I/O0–35 × 18 0 X DQ0–17 I/O0–17 × 18 1 X DQ18–35 I/O0–17 ×9 0 0 DQ0–8 I/O0–8 ×9 0 1 DQ9–17 I/O0–8 ×9 1 0 DQ18–26 I/O0–8 ×9 1 1 DQ27–35 I/O0–8 Table 6. Left Port Operation Control Pin Effect B0 I/O0–8 Byte control B1 I/O9–17 Byte control B2 I/O18–26 Byte control B3 I/O27–35 Byte control When reading a semaphore, data lines 0 through 8 output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Notes 12. BM and SIZE must be configured one clock cycle before operation is guaranteed. 13. In × 36 mode WA and BA pins are “Don’t Care.” 14. In × 18 mode BA pin is a “Don’t Care.” 15. DQ represents data output of the chip. Document Number: 38-06055 Rev. *J Page 10 of 29 CY7C056V CY7C057V Bus Match Operation Long-Word (36-bit) Operation The right port of the CY7C057V 32 K × 36 dual-port SRAM can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data I/O. The data lines are divided into four lanes, each consisting of 9 bits (byte-size data lines). Bus match select (BM) and bus size select (SIZE) set to a logic “0” will enable standard cycle long-word (36-bit) operation. In this mode, the right port’s I/O operates essentially in an identical fashion as does the left port of the dual-port SRAM. However no byte select control is available. All 36 bits of the long-word are shifted into and out of the right port’s I/O buffer stages. All read and write timing parameters may be identical with respect to the two data ports. When the right port is configured for a long-word size, word address (WA), and byte Address (BA) pins have no application and their inputs are “Don’t Care”  for the external user. x36 / CY7C056V CY7C057V 16K/32Kx36 Dual Port 9 / 9 / 9 / 9 / BUS MODE BA WA x9, x18, x36 / BM SIZE The bus match select (BM) pin works with bus size select (SIZE) to select bus width (long-word, word, or byte) for the right port of the dual-port device. The data sequencing arrangement is selected using the word address (WA) and byte address (BA) input pins. A logic “0” applied to both the bus match select (BM) pin and to the bus size select (SIZE) pin will select long-word (36-bit) operation. A logic “1” level applied to the bus match select (BM) pin will enable either byte or word bus width operation on the right port I/Os depending on the logic level applied to the SIZE pin. The level of bus match select (BM) must be static throughout device operation. Normally, the bus size select (SIZE) pin would have no standard-cycle application when BM = LOW and the device is in long-word (36-bit) operation. A “special” mode has been added however to disable ALL right port I/Os while the chip is active. This I/O disable mode is implemented when SIZE is forced to a logic “1” while BM is at a logic “0”. It allows the bus-matched port to support a chip enable “Don’t care” semaphore read/write access similar to that provided on the left port of the device when all Byte Select (B0–3) control inputs are deselected. The bus size select (SIZE) pin selects either a byte or word data arrangement on the right port when the bus match select (BM) pin is HIGH. A logic “1” on the SIZE pin when the BM pin is HIGH selects a byte bus (9-bit) data arrangement). A logic “0” on the SIZE pin when the BM pin is HIGH selects a word bus (18-bit) data arrangement. The level of the bus size select (SIZE) must also be static throughout normal device operation. Word (18-bit) Operation Word (18-bit) bus sizing operation is enabled when bus match select (BM) is set to a logic “1” and the bus size select (SIZE) pin is set to a logic “0.” In this mode, 18 bits of data are ported through I/O0R–17R. The level applied to the word address (WA) pin during word bus size operation determines whether the most-significant or least-significant data bits are ported through the I/O0R–17R pins in an Upper word/Lower word select fashion (note that when the right port is configured for word size operation, the Byte Address pin has no application and its input is “Don’t care” ). Device operation is accomplished by treating the WA pin as an additional address input and using standard cycle address and data setup/hold times. When transferring data in word (18-bit) bus match format, the unused I/O18R–35R pins are three-stated. Byte (9-bit) Operation Byte (9-bit) bus sizing operation is enabled when bus match select (BM) is set to a logic “1” and the bus size select (SIZE) pin is set to a logic “1.” In this mode, data is ported through I/O0R–8R in four groups of 9-bit bytes. A particular 9-bit byte group is selected according to the levels applied to the word address (WA) and byte address (BA) input pins. I/Os Rank WA BA I/O27R–35R Upper-MSB 1 1 I/O18R–26R Lower-MSB 1 0 I/O9R–17R Upper-MSB 0 1 I/O0R–8R Lower-MSB 0 0 Device operation is accomplished by treating the word address (WA) pin and the byte address (BA) pins as additional address inputs having standard cycle address and data set-up/hold times. When transferring data in byte (9-bit) bus match format, the unused I/O9R–35R pins are three-stated. Note 16. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along with unused inputs) must not be allowed to float. They must be forced either HIGH or LOW. Document Number: 38-06055 Rev. *J Page 11 of 29 CY7C056V CY7C057V Maximum Ratings Output current into outputs (LOW) ............................. 20 mA Exceeding maximum ratings  may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55°C to +125 °C Static discharge voltage .......................................... > 2001 V Latch-up current .................................................... > 200 mA Operating Range Supply voltage to ground potential ..............–0.5 V to +4.6 V Range DC voltage applied to outputs in High Z state .......................... –0.5 V to VDD+0.5 V Commercial DC input voltage ........................... –0.5 V to VDD + 0.5 V  Ambient Temperature VDD 0 °C to +70 °C 3.3 V ± 165 mV –40 °C to +85 °C 3.3 V ± 165 mV Industrial Electrical Characteristics Over the Operating Range Parameter  CY7C056V CY7C057V Description -12 Min VOH Output HIGH voltage (VDD = Min., IOH = –4.0 mA) 2.4 VOL Output LOW voltage (VDD = Min., IOL = +4.0 mA) – Unit -15 Typ – Max Min – 2.4 0.4 – Typ – Max – V 0.4 V VIH Input HIGH voltage 2.0 – 2.0 – V VIL Input LOW voltage – 0.8 – 0.8 V IOZ Output leakage current –10 10 –10 10 A ICC Operating current (VDD = Max., IOUT = 0 mA), output disabled 240 360 mA 265 385 mA 50 70 mA 65 95 mA 175 230 mA 190 255 mA 0.01 1 mA 0.01 1 mA 155 200 mA 170 215 mA ISB1 ISB2 ISB3 ISB4 Commercial 250 Industrial Standby current (Both ports TTL level and deselected), f = fMAX Commercial Standby current (One port TTL level and deselected), f = fMAX Commercial Standby current (Both ports CMOS level and deselected), f =0 Commercial Standby current (One Port CMOS level and deselected), f = fMAX Commercial – 55 Industrial Industrial 75 – – 180 240 – 0.01 Industrial Industrial 385 1 – 160 210 – – Notes 17. The voltage on any input or I/O pin can not exceed the power pin during power-up. 18. Pulse width < 20 ns. 19. Deselection for a port occurs if CE0 is HIGH or if CE1 is LOW. 20. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. Document Number: 38-06055 Rev. *J Page 12 of 29 CY7C056V CY7C057V Capacitance Parameter  Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VDD = 3.3 V Max Unit 10 pF 10 pF AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms OUTPUT 3.3 V Z0 = 50 R = 50 R1 = 590 C  OUTPUT VTH = 1.5 V C = 5 pF (b) Three-State Delay (Load 2) (a) Normal Load (Load 1) 3.0 V ALL INPUT PULSES R2 = 435 VSS 10% 90% 90% 10% 3 ns 3 ns for access time (ns) 7 6 5 4 3 2 1 20 30 60 80 100 200 Capacitance (pF) (b) Load Derating Curve Notes 21. Tested initially and after any design or process changes that may affect these parameters. 22. External AC Test Load Capacitance = 10 pF. 23. (Internal I/O pad Capacitance = 10 pF) + AC Test Load. Document Number: 38-06055 Rev. *J Page 13 of 29 CY7C056V CY7C057V Data Retention Mode The CY7C056V and CY7C057V are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, within VDD to VDD – 0.2 V. 2. CE must be kept between VDD – 0.2 V and 70% of VDD during the power-up and power-down transitions. 3. The RAM can begin operation > tRC after VDD reaches the minimum operating voltage (3.15 volts). Timing Data Retention Mode VCC 3.15 V VCC 2.0 V 3.15 V VCC to VCC – 0.2 V CE Parameter ICCDR1 Test Conditions @ VDDDR = 2 V tRC V IH Max Unit 50 A Notes 24. CE is LOW when CE0 VIL and CE1 VIH. 25. CE = VDD, Vin = VSS to VDD, TA = 25 C. This parameter is guaranteed but not tested. Document Number: 38-06055 Rev. *J Page 14 of 29 CY7C056V CY7C057V Switching Characteristics Over the Operating Range CY7C056V CY7C057V Parameter  Description -12 Unit -15 Min Max Min Max Read Cycle tRC Read cycle time 12 – 15 – ns tAA Address to data valid – 12 – 15 ns tOHA Output hold from address change 3 – 3 – ns tACE[27, 28] CE LOW to data valid – 12 – 15 ns tDOE OE LOW to data valid – 8 – 10 ns tLZOE [27, 29, 30, 31] OE Low to low Z 0 – 0 – ns tHZOE[27, 29, 30, 31] tLZCE[27, 26, 30, 31] tHZCE[27, 29, 30, 31] OE HIGH to High Z – 10 – 10 ns CE LOW to Low Z 3 – 3 – ns CE HIGH to High Z – 10 – 10 ns tLZBE Byte Enable to Low Z 3 – 3 – ns tHZBE Byte Enable to High Z – 10 – 10 ns tPU [27, 31] CE LOW to power-up 0 – 0 – ns tPD[27, 31] CE HIGH to power-down – 12 – 15 ns tABE Byte Enable access time – 12 – 15 ns tWC Write cycle time 12 – 15 – ns tSCE[27, 28] CE LOW to write end 10 – 12 – ns tAW Address valid to write end 10 – 12 – ns tHA Address hold from write end 0 – 0 – ns tSA Address set-up to write start 0 – 0 – ns tPWE Write pulse width 10 – 12 – ns tSD Data set-up to write end 10 – 10 – ns tHD Data hold from write end 0 – 0 – ns tHZWE[30, 31] tLZWE[30, 31] tWDD tDDD R/W LOW to High Z – 10 – – ns R/W HIGH to Low Z 3 – 3 – ns Write pulse to data delay – 25 – – ns Write data valid to read data valid – 20 – 25 ns Write Cycle Notes 26. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH and 10-pF load capacitance. 27. CE is LOW when CE0 VIL and CE1 VIH. 28. To access RAM, CE = L and SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 29. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 30. Test conditions used are Load 2. 31. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 32. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. Document Number: 38-06055 Rev. *J Page 15 of 29 CY7C056V CY7C057V Switching Characteristics (continued) Over the Operating Range CY7C056V CY7C057V Parameter  Description -12 Unit -15 Min Max Min Max Busy Timing  tBLA BUSY LOW from address match – 12 – 15 ns tBHA BUSY HIGH from address mismatch – 12 – 15 ns tBLC BUSY LOW from CE LOW – 12 – 15 ns tBHC BUSY HIGH from CE HIGH – 12 – 15 ns tPS Port set-up for priority 5 – 5 – ns tWB R/W LOW after BUSY (Slave) 0 – 0 – ns tWH R/W HIGH after BUSY HIGH (Slave) 11 – 13 – ns tBDD BUSY HIGH to data valid – 12 – 15 ns Busy Timing  Interrupt Timing  tINS INT set time – 12 – 15 ns tINR INT reset time – 12 – 15 ns Semaphore Timing tSOP SEM flag update pulse (OE or SEM) 10 – 10 – ns tSWRD SEM flag write to read time 5 – 5 – ns tSPS SEM flag contention window 5 – 5 – ns tSAA SEM address access time – 12 – 15 ns Notes 33. Test conditions used are Load 1. 34. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). Document Number: 38-06055 Rev. *J Page 16 of 29 CY7C056V CY7C057V Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access) [35, 36, 37] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [35, 38, 39] tACE CE0, CE1, B0, B1, SELECT VALID B2, B3, WA, BA tHZCE tDOE OE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU CURRENT tPD ICC ISB Figure 6. Read Cycle No. 3 (Either Port) [35, 37, 38, 39] tRC ADDRESS tAA tOHA B 0, B 1 , B 2, B3, WA, BA BYTE SELECT VALID tLZCE tHZCE tABE CE0, CE1 CHIP SELECT VALID tACE tHZCE tLZCE DATA OUT Notes 35. R/W is HIGH for read cycles. 36. Device is continuously selected. CE0 = VIL, CE1=VIH, and B0, B1, B2, B3, WA, BA are valid. This waveform cannot be used for semaphore reads. 37. OE = VIL. 38. Address valid prior to or coinciding with CE0 transition LOW and CE1 transition HIGH. 39. To access RAM, CE0 = VIL, CE1=VIH, B0, B1, B2, B3, WA, BA are valid, and SEM = VIH. To access semaphore, CE0 = VIH, CE1=VIL and SEM = VIL or CE0 and SEM=VIL, and CE1= B0 = B1 = B2 = B3, =VIH. Document Number: 38-06055 Rev. *J Page 17 of 29 CY7C056V CY7C057V Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (R/W Controlled Timing) [40, 41, 42, 43] tWC ADDRESS tHZOE  OE tAW [44, 45] CHIP SELECT VALID CE0, CE1 tPWE tSA tHA R/W tHZWE DATA OUT tLZWE NOTE 47 NOTE 47 tSD tHD DATA IN Figure 8. Write Cycle No. 2 (CE Controlled Timing) [40, 41, 42, 48] tWC ADDRESS tAW [44, 45] CHIP SELECT VALID CE0, CE1 tSA tSCE tHA R/W tSD tHD DATA IN Notes 40. R/W must be HIGH during all address transitions. 41. A write occurs during the overlap (tSCE or tPWE) of CE0=VIL and CE1=VIH or SEM=VIL and B0–3 LOW. 42. tHA is measured from the earlier of CE0/CE1 or R/W or (SEM or R/W) going HIGH at the end of Write Cycle. 43. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 44. To access RAM, CE0 = VIL, CE1=SEM = VIH. 45. To access byte B0, CE0 = VIL, B0 = VIL, CE1=SEM = VIH. To access byte B1, CE0 = VIL, B1 = VIL, CE1=SEM = VIH. To access byte B2, CE0 = VIL, B2 = VIL, CE1=SEM = VIH. To access byte B3, CE0 = VIL, B3 = VIL, CE1=SEM = VIH. 46. Transition is measured ±150 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 47. During this period, the I/O pins are in the output state, and input signals must not be applied. 48. If the CE0 LOW and CE1 HIGH or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document Number: 38-06055 Rev. *J Page 18 of 29 CY7C056V CY7C057V Switching Waveforms (continued) Figure 9. Semaphore Read After Write Timing, Either Side  tOHA tSAA A0–A2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tSCE tSOP tSD I/O0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Figure 10. Timing Diagram of Semaphore Contention [50, 51, 52] A0L–A2L MATCH R/WL SEM L tSPS A0R–A2R MATCH R/WR SEMR Notes 49. CE0 = HIGH and CE1 = LOW for the duration of the above timing (both write and read cycle). 50. I/O0R = I/O0L = LOW (request semaphore); CE0R = CE0L = HIGH and CE1R = CE1L= LOW. 51. Semaphores are reset (available to both ports) at cycle start. 52. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. Document Number: 38-06055 Rev. *J Page 19 of 29 CY7C056V CY7C057V Switching Waveforms (continued) Figure 11. Timing Diagram of Write with BUSY (M/S = HIGH)  tWC ADDRESSR MATCH tPWE R/WR tSD DATA IN R tHD VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATAOUTL VALID tWDD Figure 12. Write Timing with Busy Input (M/S = LOW) tPWE R/W BUSY tWB tWH Note 53. CE0L = CE0R = LOW; CE1L = CE1R = HIGH. Document Number: 38-06055 Rev. *J Page 20 of 29 CY7C056V CY7C057V Switching Waveforms (continued) Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)  CEL Valid First: ADDRESSL,R ADDRESS MATCH CE0L, CE1L CHIP SELECT VALID tPS CE0R, CE1R CHIP SELECT VALID tBLC tBHC BUSYR CER Valid First: ADDRESSL,R ADDRESS MATCH CE0L, CE1L CHIP SELECT VALID tPS CE0R, CE1R CHIP SELECT VALID tBLC tBHC BUSYL Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)  Left Address Valid First: tRC or tWC ADDRESSL ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSYR Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSYR Note 54. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. Document Number: 38-06055 Rev. *J Page 21 of 29 CY7C056V CY7C057V Switching Waveforms (continued) Figure 15. Interrupt Timing Diagrams Left Side Sets INTR: ADDRESSL tWC WRITE 3FFF (7FFF for CY7C057V) tHA  CE0L, CE1L CHIP SELECT VALID R/WL INTR tINS  Right Side Clears INTR: tRC READ 3FFF (7FFF for CY7C057V) ADDRESSR CHIP SELECT VALID CE0R, CE1R tINR  R/WR OER INTR Right Side Sets INTL: ADDRESSR tWC WRITE 3FFE (7FFE for CY7C057V) tHA CE0R, CE1R CHIP SELECT VALID R/WR INTR  tINS Left Side Clears INTL: tRC READ 3FFE (7FFE for CY7C057V) ADDRESSL CE0L, CE1L CHIP SELECT VALID tINR R/WL OEL INTL Notes 55. tHA depends on which enable pin (CE0L/CE1L or R/WL) is deasserted first. 56. tINS or tINR depends on which enable pin (CE0L/CE1L or R/WL) is asserted last. Document Number: 38-06055 Rev. *J Page 22 of 29 CY7C056V CY7C057V Ordering Information 16 K × 36 3.3 V Asynchronous Dual Port SRAM Speed (ns) 15 Package Name Ordering Code CY7C056V-15AXC A144 Package Type 144-pin TQFP (Pb-free) Operating Range Commercial 32 K × 36 3.3 V Asynchronous Dual Port SRAM Speed (ns) Package Name Ordering Code Package Type Operating Range 12 CY7C057V-12AXC A144 144-pin TQFP (Pb-free) Commercial 15 CY7C057V-15AXC A144 144-pin TQFP (Pb-free) Commercial CY7C057V-15AXI A144 144-pin TQFP (Pb-free) Industrial CY7C057V-15BBI BB172 172-ball BGA Industrial CY7C057V-15BBXC BB172 172-ball BGA Commercial Ordering Code Definitions CY 7 C 05 X V – XX XX X X Temperature Grade: X = C or I C = Commercial; I = Industrial Pb-free Package Type: XX = A or BB A = 144-pin TQFP; BB = 172-ball BGA Speed grade: XX = 12 ns or 15 ns V = 3.3 V Depth: X = 6 or 7 6 = 16K; 7 = 32K Width: 05 = × 36 Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-06055 Rev. *J Page 23 of 29 CY7C056V CY7C057V Package Diagrams Figure 16. 144-pin TQFP (20 × 20 × 1.4 mm) A144SA Package Outline, 51-85047 51-85047 *E Document Number: 38-06055 Rev. *J Page 24 of 29 CY7C056V CY7C057V Package Diagrams (continued) Figure 17. 172-ball FBGA (15 × 15 × 1.25 mm) BB172 Package Outline, 51-85114 51-85114 *E Document Number: 38-06055 Rev. *J Page 25 of 29 CY7C056V CY7C057V Acronyms Acronym Document Conventions Description Units of Measure BGA Ball Grid Array CE Chip Enable °C degree Celsius CMOS Complementary Metal Oxide Semiconductor MHz megahertz FBGA Fine-Pitch Ball Grid Array µA microampere I/O Input/Output mA milliampere INT Interrupt mV millivolt OE Output Enable ns nanosecond R/W Read or Write Enable ohm SRAM Static Random Access Memory pF picofarad TQFP Thin Quad Flat Pack V volt W watt Document Number: 38-06055 Rev. *J Symbol Unit of Measure Page 26 of 29 CY7C056V CY7C057V Errata This section describes the errata for the 32K/16K × 36 Asynchronous Dual-Port Static RAM – CY7C057V / CY7C056V. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. If you have questions, contact your local Cypress Sales Representative or raise a technical support case at www.cypress.com/go/support. Part Numbers Affected Part Number CY7C057V/CY7C056V (all packages and options) Device Characteristics 32K/16K × 36 Asynchronous Dual-Port Static RAM Qualification Status Product Status: This device is currently in production. Errata Summary This table defines the errata applicability to the devices. Items VDD conditions during Brown-out Part Numbers CY7C057V / CY7C056V Minimum value Maximum Value Fix Status VDD drops to less than 1.5 V during a Brown-out – To be announced by end of March 2015 1. VDD conditions during Brown-out ■ Problem Definition In the event of a brown-out, if the supply voltage (VDD) drops to a value less than 1.5 V, there is a possibility that the internal POR (power-on-reset) circuit could malfunction, resulting in functional failures after power-up again. ■ Parameters Affected Device functionality would be affected on following power-up cycles. Hence, all parameters would be affected. ■ Trigger Condition If the supply voltage (VDD) drops to a value less than 1.5 V, there is a possibility that the internal POR (power-on-reset) circuit could malfunction, resulting in functional failures after power-up again. ■ Scope of Impact This issue could affect end systems where there are brown-out events. ■ Workaround It is recommended that customers take adequate measures to avoid supply voltage (VDD) dropping below 1.5 V. If the above workaround is not possible, we recommend performing a forced power cycle, for a period greater than 500 ms. ■ Fix Status To be announced by end of March 2015. Document Number: 38-06055 Rev. *J Page 27 of 29 CY7C056V CY7C057V Document History Page Document Title: CY7C056V/CY7C057V, 3.3 V 16 K / 32 K × 36 FLEx36™ Asynchronous Dual-Port Static RAM Document Number: 38-06055 Rev. ECN No. Issue Date Orig. of Change ** 110214 12/16/01 SZV Change from Spec number: 38-00742 to 38-06055 *A 122305 12/27/02 RBI Updated Maximum Ratings: Added Note 17 and referred the same note in maximum ratings. *B 393770 See ECN YIM Added Pb-Free Logo. Updated Ordering Information (Added Pb-Free parts to ordering information namely CY7C056V-12AXC, CY7C056V-15AXC, CY7C057V-12AXC, CY7C057V-15AXC, CY7CO57V-15AXI). *C 2897217 03/22/2010 RAME Updated Ordering Information. Updated Package Diagrams. *D 3093365 11/25/2010 ADMU Updated Ordering Information (Removed part CY7C057V-15BBC, added part CY7C057V-15AXI) and added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated all footnotes. Updated to new template. *E 3210221 03/30/2011 ADMU Updated Ordering Information (Removed parts CY7C056V-15AC and CY7C057V-12BBC). *F 3403652 10/14/2011 ADMU Updated Ordering Information (Removed part CY7C057V-12AC). Updated Package Diagrams. *G 3828475 12/03/2012 SMCH Updated Functional Overview: Updated Interrupts: Updated Table 2. Updated Semaphore Operation: Updated description. Description of Change Updated Package Diagrams: spec 51-85114 – Changed revision from *D to *E. *H 4613785 01/05/2015 AJU Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. *I 4632386 01/20/2015 AJU Updated Package Diagrams: spec 51-85047 – Changed revision from *D to *E. *J 5018928 11/18/2015 NILE Updated to new template. Completing Sunset Review. Updated to new template. Added Errata. Document Number: 38-06055 Rev. *J Page 28 of 29 CY7C056V CY7C057V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06055 Rev. *J Revised November 18, 2015 Page 29 of 29 FLEx36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.