THIS SPEC IS OBSOLETE Spec No: 002-02760 Spec Title: S4041-1B1 8 GB / 16 GB, 3.0 V E.MMC FLASH Replaced by: None S4041-1B1 8 GB / 16 GB, 3.0 V e.MMC Flash Features Key Supported Features ■ e.MMC 4.51 Specification compatible ❐ Backward compatible with previous e.MMC specifications ■ Boot Operation ■ Partition Management ■ Storage temperature ❐ 40 °C to +85 °C ■ Boot Area Partition ■ Operating voltage ❐ VCCQ: 1.7 V - 1.95 V or 2.7 V - 3.6 V ❐ VCC: 2.7 V - 3.6 V ■ Replay Protected Memory Block (RPMB) ■ Sleep (CMD5) ■ Sanitize ■ Trim ■ High Priority Interrupt ■ Background Operations ■ Auto Background Operations ■ Hardware Reset ■ HS200 ■ Health Monitoring ■ Density: 8/16 GB of data storage ■ Data bus width: ❐ SDR mode: 1 bit, 4 bit, 8 bit ❐ DDR mode: 4 bit, 8 bit ❐ HS200 mode: 4 bit, 8 bit ■ Clock frequency: 52 MHz, 200 MHz (e.MMC 4.51) ❐ SDR mode: up to 52 MHz ❐ DDR mode: up to 52 MHz ❐ HS200 mode: up to 200 MHz ■ BGA packages ❐ 153-ball VFBGA: 13 mm 11.5 mm 1.0 mm ❐ 100-ball LBGA: 18 mm 14 mm 1.4 mm ■ Operating temperature range ❐ Embedded: 25 °C to +85 °C ❐ Industrial: 40 °C to +85 °C Cypress Semiconductor Corporation Document Number: 002-02760 Rev. *H • Performance ■ Sequential Read (MB/s): 120 ■ Sequential Write (MB/s): 20 ❐ Based on 16-GB device ❐ Bus in x8 I/O and HS200 modes ■ Random Read (IOPS): 5000 ■ Random Write (IOPS): 1400 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 03, 2016 S4041-1B1 General Description Cypress® e.MMC is a managed NAND memory solution designed for embedded applications. Cypress e.MMC includes a flash controller and a standard MLC NAND flash memory, and is compatible with the JEDEC JESD84-B451 with backwards compatibility to previous e.MMC specifications. Designed for faster throughput and large data transfer, Cypress e.MMC offers high performance, great reliability, and minimal latency. In addition to higher performance, Cypress’s e.MMC offers optimum power management features resulting in reduced power consumption, making it an ideal solution for mobile applications. In addition, highly optimized Cypress firmware fully utilizes the MLC NAND capabilities leveraging wear-leveling, defect management, garbage collection, and ECC to enhance product life. The Cypress e.MMC product family offers a vast array of the JEDEC e.MMC features including HS200, high priority interrupt (HPI), boot partitions, RPMB partitions, background operations, hardware reset, and power off notification. Combined with an advanced e.MMC feature set and Cypress’s commitment to quality, Cypress e.MMC is ideal for industrial applications as well as set top boxes, gaming consoles, and consumer electronic devices. Cypress Product Offering The Cypress e.MMC product offering includes: 8/16 GB in 153-FBGA (13 mm 11.5 mm) and 100-BGA (18 mm 14 mm) packages. ■ 8 GB: S40410081 ❐ 153 VFBGA (13 11.5 1.0, 0.5 mm ball pitch) ❐ 100 LBGA (18 14 1.4, 1.0 mm ball pitch) ■ 16 GB: S40410161 ❐ 153 VFBGA (13 11.5 1.0, 0.5 mm ball pitch) ❐ 100 LBGA (18 14 1.4, 1.0 mm ball pitch) Document Number: 002-02760 Rev. *H Page 2 of 29 S4041-1B1 Contents Package Configurations .................................................. 4 Architecture ...................................................................... 6 Key Supported e.MMC Features ..................................... 7 Boot Operation ............................................................ 7 Partition Management ................................................. 7 Sleep (CMD5) .............................................................. 8 High Priority Interrupt (HPI) ......................................... 8 Background Operations ............................................... 8 Auto Background Operations ...................................... 8 Trim ............................................................................. 8 Sanitize ........................................................................ 8 Hardware Reset .......................................................... 8 Health Monitoring ........................................................ 9 Field Firmware Update ................................................ 9 Register Values ............................................................... 10 Operating Conditions Register .................................. 10 Card Identification Register ....................................... 10 Product Table ............................................................ 10 Card Specific Data Register ...................................... 11 Extended CSD Register (EXT_CSD) ........................ 12 AC Parameter .................................................................. 18 Bus Timing ................................................................ 18 High Speed Timing .................................................... 18 Document Number: 002-02760 Rev. *H Backward Compatible Timing .................................... 19 DDR Interface Timing ................................................ 19 Timing Specifications for HS200 Mode ..................... 20 Signal Levels ............................................................. 23 Open-Drain Mode Bus Signal Level .......................... 23 Push-Pull Mode Bus Signal Level — High Voltage e.MMC ................................................. 23 Push-Pull Bus Signal Level — Dual Voltage e.MMC ................................................. 23 DC Parameter .................................................................. 24 Supply Voltage .......................................................... 24 Bus Operating Condition ........................................... 24 Power Consumption (Temperature = 25 °C) ............. 24 Ordering Information ...................................................... 25 Valid Combinations ................................................... 25 Package Diagrams .......................................................... 26 Document History Page ................................................. 28 Sales, Solutions, and Legal Information ...................... 29 Worldwide Sales and Design Support ....................... 29 Products .................................................................... 29 PSoC® Solutions ...................................................... 29 Cypress Developer Community ................................. 29 Technical Support ..................................................... 29 Page 3 of 29 S4041-1B1 Package Configurations Figure 1. FBGA 153 (Top View, Balls Down) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A NC DAT0 DAT1 DAT2 RFU RFU NC NC NC NC NC NC NC NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC NC NC VDDI NC VSSQ NC VCCQ NC NC NC NC NC NC NC NC NC NC NC NC NC NC B C D NC NC E NC NC NC RFU VCC VSS RFU RFU RFU NC NC NC NC NC VCC RFU NC NC NC NC NC RFU VSS RFU NC NC NC F G H NC NC NC RFU VSS NC NC NC NC NC NC RFU VCC NC NC NC NC NC NC RST_N RFU RFU VSS VCC RFU NC NC NC NC NC NC NC NC NC NC NC NC VCCQ CMD CLK J K L M NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC RFU NC NC NC NC N NC VSSQ NC VCCQ VSSQ NC P NC NC VCCQ VSSQ VCCQ VSSQ RFU Figure 2. BGA 100 (Top View, Balls Down) 1 2 NC NC 3 4 5 6 7 8 9 10 NC NC A B NC NC C D RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU VDDI RFU RFU RFU RFU RFU VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VCCQ RFU RFU RFU RFU VCCQ VSSQ RFU RFU RFU RFU RFU RFU RFU RFU DAT0 DAT2 RFU RFU RFU RFU DAT5 DAT7 VCCQ VSSQ VCCQ RFU RFU VCCQ VSSQ VCCQ RFU RFU VSSQ RST_N RFU VSSQ RFU RFU DAT1 DAT3 RFU RFU RFU RFU DAT4 DAT6 VSSQ VCCQ RFU CMD CLK RFU VCCQ VSSQ E F G H J K L M N P T NC NC U NC Document Number: 002-02760 Rev. *H NC NC NC Page 4 of 29 S4041-1B1 Table 1. Pin Description Pin Name Type DAT0 - DAT7 I/O Bidirectional data channels used for data transfers Description CMD I/O Bidirectional command channel used for device initialization and command transfers CLK Input Clock input RST_N Input Hardware reset VCC Power Supply voltage for the flash memory VCCQ Power Supply voltage for the memory controller and MMC interface VDDI Power Internal power node. Connect capacitor to ground. VSS Power Ground pin for the flash memory VSSQ Power Ground pin for the memory controller and MMC interface NC — Not connected RFU — Reserved for future use. Do not connect. Document Number: 002-02760 Rev. *H Page 5 of 29 S4041-1B1 Architecture Cypress e.MMC is an embedded non-volatile storage solution with a MultiMediaCard (MMC) interface, a high performance memory controller, and state of the art flash memory all supported by Cypress optimized flash management software. Based on the JEDEC industry-standard MMC System Specification v4.51, the Cypress e.MMC product family is offered in standard JEDEC BGA packages. Figure 3 represents the basic block diagram of the Cypress e.MMC. Figure 3. Cypress e.MMC Architecture VCC VDDI CREG CLK CMD DAT[7:0] Core Regulator Core Logic Block NAND I/O Block Reset MMC I/O Block VCCQ NAND Data Memory NAND Control e.MMC Controller Document Number: 002-02760 Rev. *H Page 6 of 29 S4041-1B1 Key Supported e.MMC Features Cypress e.MMC supports the JEDEC JESD84-B451 specification. Boot Operation Cypress e.MMC supports boot mode as well as alternate boot mode. Boot operations can be performed at high speed and dual data rate timings. Figure 4. MultiMediaCard State Diagram (Boot Mode) CLK CMD CMD1 DAT[0] S 010 E S 512 bytes E + CRC S 512 bytes + CRC RESP CMD2 RESP CMD3 RESP E Boot terminated Min 8 clocks + 48 clocks = 56 clocks required from CMD signal high to next MMC command 50 ms max 100 ms typ 150 ms max (Boot from Boot Partition) 1 sec max (Boot from User Area) Figure 5. MultiMediaCard State Diagram (Alternative Boot Mode)[1] CLK CMD CMD0 (1) CMD0/Reset DAT[0] Min. 74 clocks required after power is stable to start boot command S 010 E S 512 bytes E + CRC S CMD1 RESP CMD2 RESP CMD3 RESP 512 bytes E + CRC 50 ms max 100 ms typ 150 ms max (Boot from Boot Partition) 1 sec max (Boot from User Area) Partition Management e.MMC specifications allow for the device to have the following partitions: a User Data Area for general purpose storage, two boot partitions for storing boot images, and the Replay Protected Memory Block (RPMB) for data management in a replay protected and authenticated manner. The Cypress e.MMC device can be configured as below: ■ Factory configuration supplies two boot partitions size of 4 MB each and one RPMB partition size of 4 MB. These partitions are configured in Enhanced (SLC) mode for higher reliability. ■ The host can create up to four General Purpose Partitions within the User Data Area. These partitions can be configured in Enhanced (SLC) mode or Default (MLC) mode. The host will also need to configure the size of each partition. These attributes can be programmed by the host only once in the device life-cycle (one-time programmable). ■ In addition to the General Purpose Partitions the host can also configure a segment of the User Data Area to be accessed in Enhanced (SLC) mode. The host will need to specify the starting location and size. These attributes can be programmed by the host only once in the device life-cycle (one-time programmable). Note 1. CMD0 with argument 0xFFFFFFFA. Document Number: 002-02760 Rev. *H Page 7 of 29 S4041-1B1 Table 2. Partition Type Partition NAND Mode Boot Area 1 SLC Mode Boot Area 2 SLC Mode RPMB Area SLC Mode General Purpose Partition User Data Area MLC or SLC Mode Enhanced SLC Mode Default MLC Mode Figure 6. Partitions General Purpose Partition Boot 1 Boot 2 RPMB GPA 1 GPA 2 GPA 3 GPA 3 Enhanced User Data Area (SLC mode) Default User Data Area (MLC mode) User Data Area Sleep (CMD5) Sleep/Awake (CMD5) is used to switch the device between Sleep and Standby mode. During the Sleep state, VCC can be switched off for maximum power savings. While a device is in Sleep mode it can only respond to the Reset (CMD0) and Sleep/Awake (CMD5) commands. High Priority Interrupt (HPI) High Priority Interrupt (HPI) is intended to suspend an ongoing operation while allowing for a high priority read operation to be performed. Background Operations e.MMC devices are equipped with a Background Operations feature (see Table 7 on page 12). When enabled, Background Operations allow the e.MMC device to perform a number of routine data maintenance operations such as wear leveling, garbage collection, erase, and compaction while the host CPU is not being serviced. Auto Background Operations Auto Background Operations is a feature that allows the e.MMC device to fully manage background operations without any requirements from the Host. The e.MMC device will check if background operations are required at specified intervals and initiate background operations if needed. This frees the host from having to develop software to manage these maintenance tasks and ensure that the e.MMC device is operating at the optimum performance levels. Issuing any command while auto background operations are occurring will stop the current background operation activities. There will be a maximum latency of 40 ms if auto background operations are interrupted by any read or write command from the host. This feature is enabled on default and can be configured through the CMD56 command. A separate application note is available with the full details of the CMD56 command. A non-disclosure agreement (NDA) is required to view this application note. Contact your nearest Cypress sales office for more information. Trim Similar to the Erase operation, the Trim function (Table 7 on page 12) performs a targeted erase on specific write blocks. Data that is no longer needed, designated by the host, will be erased during background erase events. Sanitize Sanitize (Table 7 on page 12) is intended for applications with high security requirements that can afford the performance impact. This command is used in conjunction with standard Erase or Trim operations and requires the device to physically remove data from the unmapped user address space. The busy line will be asserted once the Sanitize operations begin and will remain busy until the operation has been completed or interrupted. Hardware Reset Used by the host to reset the device, hardware reset moves the device into a pre-idle state and disables the power-on period write protection on blocks that were set at power-on as write protected. Document Number: 002-02760 Rev. *H Page 8 of 29 S4041-1B1 Health Monitoring Health Monitoring is a proprietary feature of the Cypress e.MMC product that provides useful information about the life span of the NAND flash component. The host can query for the device’s health by using the CMD56 command to get information such as the number of bad blocks and the number of erase cycles for each block. EXT_CSD registers [269:254] also contain valuable device health information. A separate application note is available with the full details of the CMD56 command and EXT_CSD registers [269:254]. A non-disclosure agreement (NDA) is required to view this application note. Contact your nearest Cypress sales office for more information. Field Firmware Update Field Firmware Update is a feature that allows the host to upload a new version of the firmware to the e.MMC. This can be done by setting the device into FFU mode and performing writes with the arguments defined in the FFU_ARG register. A separate application note is available with the full details of this feature. A non-disclosure agreement (NDA) is required to view this application note. Contact your nearest Cypress sales office for more information. Document Number: 002-02760 Rev. *H Page 9 of 29 S4041-1B1 Register Values Operating Conditions Register Operation Conditions Register (OCR) stores the e.MMC voltage profile. In addition, it contains the status bit (31) which is set when the device power up has been completed. Table 3. OCR Register Field Description OCR Slice Reserved Value [6:0] 00 00000b VCCQ: 1.7 - 1.95 range [7] Dual Voltage: 1b VCCQ: 2.0 - 2.6 range [14:8] 000 0000b VCCQ: 2.7 - 3.6 range [23:15] 1 1111 1111b Reserved [28:24] 0 0000b Access Mode [30:29] Sector Mode: 10b [31] e.MMC power up status bit (busy)[2] Card Identification Register The Card Identification Register (CID) contains the card identification information used during the card identification phase. Table 4. CID Register Field ID Width CID Slice CID Value Manufacturer ID Field Name MID 8 [127:120] 01h Card BGA CBX 2 [113:112] 01b OEM/Application ID OID 8 [111:104] 00h Product Name PNM 48 [103:56] See Product Table. Product Revision[5] PRV 8 [55:48] PSN 32 [47:16] 32-bit unsigned binary integer assigned at random MDT 8 [15:8] CRC 7 [7:1] — 1 [0] Always 1 Product Serial Number Manufacturing Date [4] [4] CRC7 Checksum Not Used Product Table Table 5. Product Table Cypress Part Number Density Product Name in CID Register (PNM) S40410081 8 GB “S40408” – 533430343038h S40410161 16 GB “S40416” – 533430343136h Notes 2. Reserved bits should be read at ‘0’. 3. R = Read only. R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. 4. VDD represents the total consumed current for VCC and VCCQ. Document Number: 002-02760 Rev. *H Page 10 of 29 S4041-1B1 Card Specific Data Register Card Specific Data (CSD) Register contains the e.MMC access information. It includes data format, error correction, transfer speeds, and access times. It also includes information as to whether the DSR register can be accessed. Table 6. CSD Register Size (Bits) Cell Type CSD Slice CSD Value CSD Structure Field Name CSD_STRUCTURE 2 R [127:126] 3h System Specification Version SPEC_VERS 4 R [125:122] 4h 2 R [121:120] — Reserved Field ID [5] — Data Read Access Time 1 TAAC 8 R [119:112] 4Fh Data Read Access Time 2 in CLK cycles (NSAC*100) NSAC 8 R [111:104] 01h Maximum Bus Clock Frequency TRAN_SPEED 8 R [103:96] 32h Card Command Classes CCC 12 R [95:84] 0F5h Maximum Read Block Length READ_BL_LEN 4 R [83:80] 9h Partial Blocks For Read Allowed READ_BL_PARTIAL 1 R [79:79] 0h Write Block Misalignment WRITE_BLK_MISALIGN 1 R [78:78] 0h Read Block Misalignment READ_BLK_MISALIGN 1 R [77:77] 0h Dsr Implemented DSR_IMP 1 R [76:76] 0h 2 R [75:74] — [5] — Reserved Device Size *C_SIZE 12 R [73:62] FFFh Maximum Read Current at VDD min VDD_R_CURR_MIN 3 R [61:59] 7h Maximum Read Current at VDD max VDD_R_CURR_MAX 3 R [58:56] 7h Maximum Write Current at VDD min VDD_W_CURR_MIN 3 R [55:53] 7h Maximum Write Current at VDD max VDD_W_CURR_MAX 3 R [52:50] 7h Device Size Multiplier C_SIZE_MULT 3 R [49:47] 7h Erase Group Size ERASE_GRP_SIZE 5 R [46:42] 1Fh Erase Group Size Multiplier ERASE_GRP_MULT 5 R [41:37] 1Fh Write Protect Group Size WP_GRP_SIZE 5 R [36:32] 8 GB: 0Fh 16 GB: 1Fh Write Protect Group Enable WP_GRP_ENABLE 1 R [31:31] 1h Manufacturer Default DEFAULT_ECC 2 R [30:29] 0h Write Speed Factor R2W_FACTOR 3 R [28:26] 2h Maximum Write Data Block Length WRITE_BL_LEN 4 R [25:22] 9h Partial Blocks For Write Allowed WRITE_BL_PARTIAL 1 R [21:21] 0h [5] 4 R [20:17] — Content Protection Application CONTENT_PROT_APP 1 R [16:16] 0h File Format Group FILE_FORMAT_GRP 1 R/W [15:15] 0h Copy Flag (OTP) COPY 1 R/W [14:14] 0h Permanent Write Protection PERM_WRITE_PROTECT 1 R/W [13:13] 0h Reserved — Notes 5. Reserved bits should be read at ‘0’. 6. R = Read only. R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. 7. VDD represents the total consumed current for VCC and VCCQ. Document Number: 002-02760 Rev. *H Page 11 of 29 S4041-1B1 Table 6. CSD Register (Continued) Size (Bits) Cell Type CSD Slice CSD Value Temporary Write Protection Field Name TMP_WRITE_PROTECT Field ID 1 R/W/E [12:12] 0h File Format FILE_FORMAT 2 R/W [11:10] 0h ECC Code ECC 2 R/W/E [9:8] 0h Calculated CRC CRC 7 R/W/E [7:1] — 1 — [0] Always 1 Not Used — Notes 5. Reserved bits should be read at ‘0’. 6. R = Read only. R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. 7. VDD represents the total consumed current for VCC and VCCQ. Extended CSD Register (EXT_CSD) The Extended CSD Register defines the e.MMC selected modes and properties. It is 512 bytes long. The most significant 320 bytes, also know as Properties segment, define the e.MMC capabilities and cannot be modified by the host. The remaining 192 bytes define e.MMC operating modes and can be modified by the host via a Switch command. Table 7. Extended CSD Register (EXT_CSD) Field Name Field ID Reserved[8] — Size (Bytes) Cell Type EXT_CSD Slice Value 6 — [511:506] — Extended Security Commands Error EXT_SECURITY_ERR 1 R [505] 00h Supported Command Sets S_CMD_SET 1 R [504] 01h HPI Features HPI_FEATURES 1 R [503] 01h Background Operations Support BKOPS_SUPPORT 1 R [502] 01h Max Packed Read Commands MAX_PACKED_READS 1 R [501] 3Ch Max Packed Write Commands MAX_PACKED_WRITES 1 R [500] 3Ch Data Tag Support DATA_TAG_SUPPORT 1 R [499] 01h Tag Unit Size TAG_UNIT_SIZE 1 R [498] 03h Tag Resources Size TAG_RES_SIZE 1 R [497] 00h Context Management Capabilities CONTEXT_CAPABILITIES 1 R [496] 05h Large Unit Size LARGE_UNIT_SIZE_M1 1 R [495] 8 Gb: 03h 16 Gb: 07h Extended Partitions Attribute Support EXT_SUPPORT 1 R [494] 03h Supported Modes SUPPORTED_MODES 1 R [493] 01h FFU Features FFU_FEATURES 1 R [492] 00h Operation Codes Timeout OPERATION_CODE_TIMEOUT 1 R [491] 00h Notes 8. Reserved bits should be read at 0, unless otherwise specified. 9. Set to 0 after power on, hardware reset or software reset selecting backward compatibility interface timings. If the host changes the value to 1, the device will operate in high-speed mode and finally, if host changes the value to 2, HS200 interface timings will be used. 10. Set to 0 after power up and can be changed via a Switch command. 11. R = Read only. R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable. W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and not readable. 12. Value depends on state of the device. 13. Value depends on the firmware that the device is loaded with. Document Number: 002-02760 Rev. *H Page 12 of 29 S4041-1B1 Table 7. Extended CSD Register (EXT_CSD) (Continued) Field Name Field ID Size (Bytes) Cell Type EXT_CSD Slice Value FFU Argument FFU_ARG 4 R [490:487] Normal mode: 00000000h FFU mode: 0000FFFFh 181 — [486:306] — 4 R [305:302] 00000000h 32 — [301:270] — Reserved[8] Number of FW Sectors Correctly Programmed NUMBER_OF_FW_SECTORS_ CORRECTLY_PROGRAMMED Reserved[8] — Device Life Time Estimation Type B DEVICE_LIFE_TIME_EST_TYP_B 1 R [269] 01h Device Life Time Estimation Type A DEVICE_LIFE_TIME_EST_TYP_A 1 R [268] 01h Pre-EOL Information PRE_EOL_INFO 1 R [267] 01h[12] Optimal Read Size OPTIMAL_READ_SIZE 1 R [266] 01h Optimal Write Size OPTIMAL_WRITE_SIZE 1 R [265] 04h Optimal Trim Unit Size OPTIMAL_TRIM_UNIT_SIZE 1 R [264] 01h Device Version DEVICE_VERSION 2 R [263:262] B101h Firmware Version[13] FIRMWARE_VERSION 8 R [261:254] — Reserved [8] 1 — [253] — Cache Size CACHE_SIZE — 4 R [252:249] 00000000h Generic CMD6 Timeout GENERIC_CMD6_TIME 1 R [248] 19h Power Off Notification (Long) Timeout POWER_OFF_LONG_TIME 1 R [247] FFh Background Operations Status BKOPS_STATUS 1 R [246] 00h Number Of Correctly Programmed Sectors CORRECTLY_PRG_SECTORS_NU M 4 R [245:242] 00000000h 1st Initialization Time after Partitioning INI_TIMEOUT_PA 1 R [241] 32h Reserved[8] 1 — [240] — Power Class for 52 MHz, DDR at 3.6 V PWR_CL_DDR_52_360 1 R [239] 44h Power Class for 52 MHz, DDR at 1.95 PWR_CL_DDR_52_195 V 1 R [238] 99h Power Class for 200 MHz at 1.95 V PWR_CL_200_195 1 R [237] AAh Power Class for 200 MHz at 1.30 V PWR_CL_200_130 1 R [236] 00h Minimum Write Performance for 8-bit at 52 MHz in DDR mode MIN_PERF_DDR_W_8_52 1 R [235] 08h Minimum Read Performance for 8-bit at 52 MHz in DDR mode MIN_PERF_DDR_R_8_52 1 R [234] 08h 1 — [233] — — Reserved[8] — Notes 8. Reserved bits should be read at 0, unless otherwise specified. 9. Set to 0 after power on, hardware reset or software reset selecting backward compatibility interface timings. If the host changes the value to 1, the device will operate in high-speed mode and finally, if host changes the value to 2, HS200 interface timings will be used. 10. Set to 0 after power up and can be changed via a Switch command. 11. R = Read only. R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable. W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and not readable. 12. Value depends on state of the device. 13. Value depends on the firmware that the device is loaded with. Document Number: 002-02760 Rev. *H Page 13 of 29 S4041-1B1 Table 7. Extended CSD Register (EXT_CSD) (Continued) Field Name Field ID Size (Bytes) Cell Type EXT_CSD Slice Value Trim Multiplier TRIM_MULT 1 R [232] 0Fh Secure Feature Support SEC_FEATURE_SUPPORT 1 R [231] 55h Secure Erase Multiplier SEC_ERASE_MULT 1 R [230] 06h Secure TRIM Multiplier SEC_TRIM_MULT 1 R [229] 09h Boot Information BOOT_INFO 1 R [228] 07h — 1 — [227] — Boot Partition Size BOOT_SIZE_MULTI 1 R [226] 20h Access Size ACC_SIZE 1 R [225] 8 GB: 06h 16 GB: 07h High Capacity Erase Unit Size HC_ERASE_GRP_SIZE 1 R [224] 8 GB: 08h 16 GB: 10h High Capacity Erase Time Out ERASE_TIMEOUT_MULT 1 R [223] 01h Reserved[8] Reliable Write Sector Count REL_WR_SEC_C 1 R [222] 01h High Capacity Write Protect Group Size HC_WP_GRP_SIZE 1 R [221] 02h Sleep Current [VCC] S_C_VCC 1 R [220] 08h Sleep Current [VCCQ] S_C_VCCQ 1 R [219] 08h PRODUCTION_STATE_AWARENES Production State Awareness Timeout S_TIMEOUT 1 R [218] 14h Sleep/awake Time Out 1 R [217] 10h 1 — [216] 0Fh Reserved S_A_TIMEOUT [8] Sector Count — SEC_COUNT Reserved[8] — 4 R [215:212] 8 GB: 00E90000h 16 GB: 01D20000h 1 — [211] — Minimum Write Performance for 8-bit at 52 MHz MIN_PERF_W_8_52 1 R [210] 08h Minimum Read Performance for 8-bit at 52 MHz MIN_PERF_R_8_52 1 R [209] 08h Minimum Write Performance for 4-bit at 52 MHz or 8-bit at 26 MHz MIN_PERF_W_8_26_4_52 1 R [208] 08h Minimum Read Performance for 4-bit at 52 MHz or 8-bit at 26 MHz MIN_PERF_R_8_26_4_52 1 R [207] 08h Minimum Write Performance for 4-bit at 26 MHz MIN_PERF_W_4_26 1 R [206] 08h Notes 8. Reserved bits should be read at 0, unless otherwise specified. 9. Set to 0 after power on, hardware reset or software reset selecting backward compatibility interface timings. If the host changes the value to 1, the device will operate in high-speed mode and finally, if host changes the value to 2, HS200 interface timings will be used. 10. Set to 0 after power up and can be changed via a Switch command. 11. R = Read only. R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable. W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and not readable. 12. Value depends on state of the device. 13. Value depends on the firmware that the device is loaded with. Document Number: 002-02760 Rev. *H Page 14 of 29 S4041-1B1 Table 7. Extended CSD Register (EXT_CSD) (Continued) Field Name Minimum Read Performance for 4-bit at 26 MHz Size (Bytes) Cell Type EXT_CSD Slice Value MIN_PERF_R_4_26 1 R [205] 08h — 1 — [204] — Field ID Reserved[8] Power Class for 26 MHz at 3.6 V PWR_CL_26_360 1 R [203] 22h Power Class for 52 MHz at 3.6 V PWR_CL_52_360 1 R [202] 22h Power Class for 26 MHz at 1.95 V PWR_CL_26_195 1 R [201] 77h Power Class for 52 MHz at 1.95 V PWR_CL_52_195 1 R [200] 77h Partition Switching Timing PARTITION_SWITCH_TIME 1 R [199] 03h Out-of-Interrupt Busy Timing OUT_OF_INTERRUPT_TIME 1 R [198] 04h I/O Driver Strength DRIVER_STRENGTH 1 R [197] 0Fh Card Type CARD_TYPE 1 R [196] 17h Reserved [8] CSD Structure Version — 1 — [195] — CSD_STRUCTURE 1 R [194] 02h — 1 — [193] — Reserved[8] Extended CSD Revision EXT_CSD_REV 1 R [192] 06h Command Set CMD_SET 1 R/W/E_P [191] 00h 1 — [190] — 1 R [189] 00h — 1 — [188] — 1 R/W/E_P [187] 00h — 1 — [186] — 1 R/W/E_P [185] 0h[9] 1 — [184] — 1 W/E_P [183] 0h[10] 1 — [182] — 1 R [181] 00h 1 — [180] — Reserved[8] Command Set Revision — CMD_SET_REV Reserved[8] Power Class POWER_CLASS Reserved[8] High Speed Interface Timing HS_TIMING Reserved[8] Bus Width Mode — BUS_WIDTH Reserved[8] Content of Explicit Erased Memory Range — ERASED_MEM_CONT Reserved[8] — Partition Configuration PARTITION_CONFIG 1 R/W/E, R/W/E_P [179] 00h Boot Config Protection BOOT_CONFIG_PROT 1 R/W, R/W/C_P [178] 00h Boot Bus Width1 BOOT_BUS_WIDTH 1 R/W/E [177] 00h 1 — [176] — 1 R/W/E_P [175] 00h Reserved [8] High-Density Erase Group Definition — ERASE_GROUP_DEF Notes 8. Reserved bits should be read at 0, unless otherwise specified. 9. Set to 0 after power on, hardware reset or software reset selecting backward compatibility interface timings. If the host changes the value to 1, the device will operate in high-speed mode and finally, if host changes the value to 2, HS200 interface timings will be used. 10. Set to 0 after power up and can be changed via a Switch command. 11. R = Read only. R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable. W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and not readable. 12. Value depends on state of the device. 13. Value depends on the firmware that the device is loaded with. Document Number: 002-02760 Rev. *H Page 15 of 29 S4041-1B1 Table 7. Extended CSD Register (EXT_CSD) (Continued) Size (Bytes) Cell Type EXT_CSD Slice Value Boot Write Protection Status Register BOOT_WP_STATUS 1 R [174] 00h Boot Area Write Protect Register 1 R/W, R/W/C_P [173] 00h 1 — [172] — 1 R/W, R/W/C_P, R/ W/E_P [171] 00h 1 — [170] — Field Name Reserved Field ID BOOT_WP [8] User Area Write Protect Register — USER_WP Reserved[8] — FW Configuration FW_CONFIG 1 R/W [169] 00h RPMB Size RPMB_SIZE_MULT 1 R [168] 20h Write Reliability Setting Register WR_REL_SET 1 R/W [167] 00h Write Reliability Parameter Register WR_REL_PARAM 1 R [166] 05h Start Sanitize Operation SANITIZE_START 1 W/E_P [165] 00h Manually Start Background Operations BKOPS_START 1 W/E_P [164] 00h Enable Background Operations Handshake BKOPS_EN 1 R/W [163] 00h Hardware Reset Function RST_n_FUNCTION 1 R/W [162] 00h HPI Management HPI_MGMT 1 R/W/E_P [161] 00h Partitioning Support PARTITIONING_SUPPORT 1 R [160] 07h Max Enhanced Area Size MAX_ENH_SIZE_MULT 3 R [159:157] 0001D2h Partitions Attribute PARTITIONS_ATTRIBUTE 1 R/W [156] 00h Partitioning Setting PARTITION_SETTING_COMPLETED 1 R/W [155] 00h General Purpose Partition Size GP_SIZE_MULT 12 R/W [154:143] 00...00h Enhanced User Data Area Size ENH_SIZE_MULT 3 R/W [142:140] 000000h Enhanced User Data Start Address ENH_START_ADDR 4 R/W [139:136] 00000000h — Reserved[8] 1 — [135] — Bad Block Management Mode SEC_BAD_BLK_MGMNT 1 R/W [134] 00h Production State Awareness PRODUCTION_STATE_AWARENES S 1 R/W/E [133] 00h Package Case Temperature is Controlled TCASE_SUPPORT 1 W/E_P [132] 00h Periodic Wakeup PERIODIC_WAKEUP 1 R/W/E [131] 00h Program CID/CSD in DDR Mode Support PROGRAM_CID_CSD_DDR_SUPPO RT 1 R [130] 01h — 2 — [129:128] — Reserved[8] Notes 8. Reserved bits should be read at 0, unless otherwise specified. 9. Set to 0 after power on, hardware reset or software reset selecting backward compatibility interface timings. If the host changes the value to 1, the device will operate in high-speed mode and finally, if host changes the value to 2, HS200 interface timings will be used. 10. Set to 0 after power up and can be changed via a Switch command. 11. R = Read only. R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable. W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and not readable. 12. Value depends on state of the device. 13. Value depends on the firmware that the device is loaded with. Document Number: 002-02760 Rev. *H Page 16 of 29 S4041-1B1 Table 7. Extended CSD Register (EXT_CSD) (Continued) Field Name Field ID Size (Bytes) Cell Type EXT_CSD Slice Value Vendor Specific Fields VENDOR_SPECIFIC_FIELD 64 <vendor specific> [127:64] 00...00h Native Sector Size NATIVE_SECTOR_SIZE 1 R [63] 00h Sector Size Emulation USE_NATIVE_SECTOR 1 R/W [62] 00h Sector Size DATA_SECTOR_SIZE 1 R [61] 00h 1st Initialization After Disabling Sector INI_TIMEOUT_EMU Size Emulation 1 R [60] 0Ah Class 6 Command Control CLASS_6_CTRL 1 R/W/E_P [59] 00h Number Of Address Group To Be Released DYNCAP_NEEDED 1 R [58] 00h Exception Events Control EXCEPTION_EVENTS_CTRL 2 R/W/E_P [57:56] 0000h Exception Events Status EXCEPTION_EVENTS_STATUS 2 R [55:54] 0000h Extended Partitions Attribute EXT_PARTITIONS_ATTRIBUTE 2 R/W [53:52] 0000h Context Configuration CONTEXT_CONF 15 R/W/E_P [51:37] 00...00h Packed Command Status PACKED_COMMAND_STATUS 1 R [36] 00h Packed Command Failure Index PACKED_FAILURE_INDEX 1 R [35] 00h Power Off Notification POWER_OFF_NOTIFICATION 1 R/W/E_P [34] 00h Control to Turn the Cache On/Off CACHE_CTRL 1 R/W/E_P [33] 00h Flushing of the Cache FLUSH_CACHE 1 W/E_P [32] 00h 1 — [31] — 1 R/W/E_P [30] 00h Reserved [8] Mode Config MODE_CONFIG Mode Operation Codes MODE_OPERATION_CODES Reserved[8] 1 W/E_P [29] 00h 2 — [28:27] — FFU Status FFU_STATUS 1 R [26] 00h Pre Loading Data Size PRE_LOADING_DATA_SIZE 4 R/W/E_P [25:22] 00000000h Max Pre Loading Data Size MAX_PRE_LOADING_DATA_SIZE 4 R [21:18] 8 GB: 00748000h 16 GB: 00E90000h Enable Production State Awareness PRODUCT_STATE_AWARENESS_E NABLEMENT 1 R/W/E and R [17] 01h 17 — [16:0] — Reserved[8] Notes 8. Reserved bits should be read at 0, unless otherwise specified. 9. Set to 0 after power on, hardware reset or software reset selecting backward compatibility interface timings. If the host changes the value to 1, the device will operate in high-speed mode and finally, if host changes the value to 2, HS200 interface timings will be used. 10. Set to 0 after power up and can be changed via a Switch command. 11. R = Read only. R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable. W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and not readable. 12. Value depends on state of the device. 13. Value depends on the firmware that the device is loaded with. Document Number: 002-02760 Rev. *H Page 17 of 29 S4041-1B1 AC Parameter Bus Timing Figure 7. Bus Timing Diagram[14] t PP t WH CLK min (VIH ) t WL 50% V DD t IH 50% VDD t THL tISU max (VIL ) t TLH min (VIH ) Data Input Invalid Data max (VIL ) t ODLY t OSU t OH min (VOH) Output Invalid Data Data max (VOL) High Speed Timing Table 8. High Speed Timing Parameter Symbol Min Max Unit 0 52 MHz Remark Clock CLK CL 30 pF Tolerance: +100 kHz Clock Frequency Data Transfer Mode fPP Clock Frequency Identification Mode fOD 0 400 kHz — ns CL 30 pF Tolerance: +20 kHz Clock Low Time tWL 6.5 Clock High Time tWH 6.5 — ns CL 30 pF Clock Rise Time tTLH — 3 ns CL 30 pF Clock Fall Time tTHL — 3 ns CL 30 pF Inputs CMD, DAT (referenced to CLK) Input Set-up Time tISU 3 — ns CL 30 pF Input Hold Time tIH 3 — ns CL 30 pF Outputs CMD, DAT (referenced to CLK) tODLY — 13.7 ns CL 30 pF Output Hold Time tOH 2.5 — ns CL 30 pF Signal Rise Time tRISE — 3 ns CL 30 pF Signal Fall Time tFALL — 3 ns CL 30 pF Output Delay Time During Data Transfer Mode Note 14. Data must always be sampled on the rising edge of the clock. Document Number: 002-02760 Rev. *H Page 18 of 29 S4041-1B1 Backward Compatible Timing Table 9. Backward Compatible Timing Parameter Symbol Min Max Unit Remark CL 30 pF Clock CLK Clock Frequency Data Transfer Mode fPP 0 26 MHz Clock Frequency Identification Mode fOD 0 400 kHz Clock Low Time tWL 10 — ns CL 30 pF Clock High Time tWH 10 — ns — Clock Rise Time tTLH — 10 ns CL 30 pF Clock Fall Time tTHL — 10 ns CL 30 pF Inputs CMD, DAT (referenced to CLK) Input Set-Up Time tISU 3 — ns CL 30 pF Input Hold Time tIH 3 — ns CL 30 pF Outputs CMD, DAT (referenced to CLK) Output Hold Time tOH 8.3 — ns CL 30 pF Output Set-up Time tOSU 11.7 — ns CL 30 pF DDR Interface Timing Figure 8. DDR Interface Timing t PP min (V IH ) CLK tIHddr tIHddr tISUddr max (VIL ) tISUddr min (V IH ) Input Data Data Data Invalid max (VIL ) Output t ODLYddr(max) t ODLYddr(max) tODLYddr(min) tODLYddr(min) min (VOH ) I Data Data Data max (VOL ) Document Number: 002-02760 Rev. *H Page 19 of 29 S4041-1B1 Table 10. DDR Interface Timing Parameter Symbol Min Max Unit Remark 55 % Includes jitter, phase noise Input CLK1 Clock Duty Cycle — 45 Input DAT (referenced to CLK-DDR mode) Input Set-up Time tISUddr 2.5 — ns CL 20 pF Input Hold Time tIHddr 2.5 — ns CL 20 pF Output DAT (referenced to CLK-DDR mode) tODLYddr 1.5 7 ns CL 20 pF Signal Rise Time (All Signals) tRISE — 2 ns CL 20 pF Signal Fall Time (All Signals) tFALL — 2 ns CL 20 pF Output Delay Time During Data Transfer Timing Specifications for HS200 Mode HS200 Clock Timing HS200 mode is available when VCCQ is 1.7V to 1.95V, and the clock timing should conform with the timing diagram shown in Figure 9. CLK input timings need to meet the clock timing across the entire range of operating environment. CLK timings must be measured while CMD and DAT signals are either high or low. HS200 supports clock frequencies of up to 200 MHz. Figure 9. HS200 Clock Signal Timing tPERIOD VCCQ Clock Input VIH VT VIL VSS tTLH tTHL Table 11. HS200 Clock Signal Timing Symbol Min Max Unit tPERIOD 5 — ns 200 MHz (max.) between rising edges. Remark tTLH, tTHL — 0.2 tPERIOD ns tTLH, tTHL < 1 ns (max.) at 200 MHz, CBGA = 12 pF. The absolute max. value of tTLH, tTLH is 10 ns regardless of clock frequency. Duty Cycle 30 70 % — Note 15. VIH denotes VIH(min.), and VIL denotes VIL(max.). 16. VT = 0.975 V, Clock Threshold (VCCQ = 1.8 V); indicates reference points for timing measurements. Document Number: 002-02760 Rev. *H Page 20 of 29 S4041-1B1 HS200 Input Timing Figure 10. HS200 Device Input Timing[17, 18] tPERIOD VCCQ Clock Input VT VSS tISU VCCQ tIH VIH CMD.DAT[7-0] Input VIL VIH Valid Window VIL VSS Table 12. HS200 Device Input Timing Symbol Min Max Unit Remark tISU 1.40 — ns 5 pF CBGA 12 pF tIH 0.8 — ns 5 pF CBGA 12 pF HS200 Output Timing The tPH parameter is defined to allow device output delay to be longer than tPERIOD. tPH may have random phase relation to the clock upon initialization. The Host is ultimately responsible to find the optimal sampling point for the Device outputs, while switching to the HS200 mode. The impact of a temperature drift (TPH) has to be taken into account when setting the sampling point. Output valid data window (tVW) is available regardless of the drift (TPH) while the position of data window varies by the drift. Figure 11. HS200 Device Output Timing[19] tPERIOD VCCQ Clock Input VT VSS tPH tVW VOH CMD.DAT[7-0] Input VOL VCCQ VOH Valid Window VOL VSS Note 17. tISU and tIH are measured at VIL(max.) and VIH(min.). 18. VIH denotes VIH(min.), and VIL denotes VIL(max.). 19. VOH denotes VOH(min.), and VOL denotes VOL(max.). Document Number: 002-02760 Rev. *H Page 21 of 29 S4041-1B1 Table 13. HS200 Device Output Timing[20] Symbol tPH TPH tVW Min 0 Max 2 +1550 350 (T = 20 °C) (T = 90 °C) 0.575 — Unit Notes UI Device output momentary phase from CLK input to CMD or DAT lines output. Does not include a long term temperature drift. ps Delay variation due to temperature change after tuning. Total allowable shift of output valid window (tVW) from last system Tuning procedure. TPH is 2600 ps for T from 25 °C to 125 °C during operation. UI tVW = 2.88 ns at 200 MHz. Host path may add Signal Integrity induced noise, skews, and so on. Expected tVW at Host input is larger than 0.475 UI. Figure 12. ΔTPH = -350 ps TPH Consideration ΔTPH = 1550 ps Sampling point Valid Window Sampling point after turning Valid Window Valid Window Sampling point after junction heated to +90°C Sampling point after junction cooled to -20°C Implementation Guide: The host should avoid sampling errors that are caused by the TPH drift. Tuning should be performed while the device wakes up after sleep. Reducing operating frequency can help overcome the TPH drift. Note 20. Unit Interval (UI) is one-bit nominal time (i.e., UI = 5 ns at 200 MHz). Document Number: 002-02760 Rev. *H Page 22 of 29 S4041-1B1 Signal Levels Figure 13. Signal Levels V V CCQ Input High Level Output High Level V OH V IH undefined V IL Input Low Level Output Low Level V OL V SS t Open-Drain Mode Bus Signal Level Table 14. Open-Drain Mode Bus Signal Level Parameter Symbol Min Max Unit Conditions Output High Voltage VOH VCCQ -0.2 — V IOH = 100 µA Output Low Voltage VOL — 0.3 V IOLL = 2 mA Push-Pull Mode Bus Signal Level — High Voltage e.MMC Table 15. Push-Pull Mode Bus Signal Level — High Voltage e.MMC Parameter Symbol Min Max Unit Conditions Output High Voltage VOH 0.75 * VCCQ — V IOH = 100 µA at VCCQ min Output Low Voltage VOL — 0.125 * VCCQ V IOL = 100 µA at VCCQ min Input High Voltage VIH 0.625 * VCCQ VCCQ + 0.3 V — Input Low Voltage VIL 0.25 * VCCQ V — VSS -0.3 Push-Pull Bus Signal Level — Dual Voltage e.MMC Table 16. Push-Pull Bus Signal Level — Dual Voltage e.MMC Parameter Symbol Min Max Unit Conditions Output High Voltage VOH VCCQ -0.45V — V IOH = 2 mA Output Low Voltage VOL — 0.45V V IOL = 2 mA Input High Voltage VIH 0.65 * VCCQ VCCQ + 0.3 V — Input Low Voltage VIL 0.35 * VCCQ V — Document Number: 002-02760 Rev. *H VSS -0.3 Page 23 of 29 S4041-1B1 DC Parameter Supply Voltage Table 17. Supply Voltage Symbol Min Max Unit VCC 2.7 3.6 V VCCQ 2.7 3.6 V 1.7 1.95 V 0.5 0.5 V VSS Bus Operating Condition Table 18. Bus Operating Condition Parameter Peak Voltage on all lines Input Leakage Current (after changing the bus width and disconnecting the internal pull-up resistors) Output Leakage Current (after changing the bus width and disconnecting the internal pull-up resistors) Min Max Unit 0.5 2 VCCQ + 0.5 V 2 µA 2 2 µA Power Consumption (Temperature = 25 °C) Table 19. Power Consumption (Temperature = 25 °C)[21, 22, 23] VCCQ Density 8 GB 16 GB Mode 3.6V VCC 1.95V 3.6V SDR52 DDR52 HS200 SDR52 DDR52 HS200 Write [mA] 50 50 100 100 100 100 Read [mA] 50 50 100 100 100 100 100 150 150 100 150 150 Standby 650 µA Sleep (CMD5) 500 µA Write [mA] 50 50 100 Read [mA] 50 50 100 Standby 700 µA Sleep (CMD5) 500 µA Note 21. Measurements averaged over periods of 100 ms. 22. In Standby mode, CLK is set low. 23. In Sleep mode, VCC power supply is off. Document Number: 002-02760 Rev. *H Page 24 of 29 S4041-1B1 Ordering Information The ordering part number is formed by a valid combination of the following: S4041 008 1 B1 B1 W 00 0 Packing Type 0 = Tray 3 = 13” Tape and Reel Model Number 00 = 1 NAND Die 01 = 2 NAND Die Temperature Range W = Embedded (25 °C to +85 °C) I = Industrial (40 °C to + 85 °C) Package B1 = FBGA 153, 13 11.5 mm B2 = BGA 100, 18 14 mm Controller B1 = e.MMC 4.51 Revision 1 = MLC NAND Density 008 = 8 GB 016 = 16 GB Device Family S4041 Cypress e.MMC Family Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Contact your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Table 20. Valid Combinations Device Family S4041 Density 008 016 Revision Controller Package Type Temperature Range 1 B1 B1, B2 W, I Document Number: 002-02760 Rev. *H Model Number 00 01 Packing Type Package Description 0, 3 BGA Page 25 of 29 S4041-1B1 Package Diagrams Figure 14. VFBGA 153 (13 11.5 1.0 mm) NOTES: PACKAGE RLH/RMA 153 JEDEC MO-276 DXE 13.00 mm x 11.50 mm PACKAGE NOTE SYMBOL MIN NOM MAX A --- --- 1.00 A1 0.17 --- --- 2. ALL DIMENSIONS ARE IN MILLIMETERS. PROFILE BALL HEIGHT D 13.00 BSC BODY SIZE E 11.50 BSC BODY SIZE D1 6.50 BSC MATRIX FOOTPRINT E1 6.50 BSC MATRIX FOOTPRINT MD 14 14 MATRIX SIZE E DIRECTION n 153 BALL COUNT eE 0.25 0.30 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. 4. 0.35 0.50 BSC SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL DIAMETER eD 0.50 BSC BALL PITCH 0.25 BSC SOLDER BALL PLACEMENT D5-D11,E11-K11,L4-L11,E4-K4 F6-F9,G6-G9,H6-H9,J6-J9 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = 0. BALL PITCH SD / SE DEPOPULATED SOLDER BALL LOCATIONS e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. MATRIX SIZE D DIRECTION ME Øb 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5-2009. THIS OUTLINE CONFORMS TO JEP95, SECTION 4.6. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 . 8. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 9. TEST PADS MAY BE PRESENT BUT ARE NOT SHOWN. THEY ARE FOR INTERNAL USE ONLY AND ARE NOT SOLDER BALLS. g5028 \ f16-038.63 \ 3-21-2014 Document Number: 002-02760 Rev. *H Page 26 of 29 S4041-1B1 Figure 15. LBGA 100 (18 14 1.4 mm) NOTES: PACKAGE L2B/L3B 100 JEDEC MO-304 DXE 18.00mm X 14.00mm PACKAGE SYMBOL MIN. NOM. MAX. A --- --- 1.40 A1 0.25 --- --- NOTE 5. SYMBOL “MD” IS THE BALL MATRIX SIZE IN THE “D” DIRECTION. SYMBOL “ME” IS THE BALL MATRIX SIZE IN THE “E” DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6. DIMENSION “b” IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = e/2 8. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. BODY SIZE 14.00 BSC BODY SIZE D1 16.00 BSC MATRIX FOOTPRINT E1 9.00 BSC MATRIX FOOTPRINT MD 17 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION 100 0.45 BALL POSITION DESIGNATION PER JEP 95, SECTION 3, SPP-020. BALL HEIGHT 18.00 BSC 0.40 3. 4. E n 2. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5-2009. THIS OUTLINE CONFORMS TO JEP 95, SECTION 4.6. ALL DIMENSIONS ARE IN MILLIMETERS. PROFILE D Ob 1. BALL COUNT 0.50 BALL DIAMETER eE 1.00 BSC BALL PITCH eD 1.00 BSC BALL PITCH SE 0.50 BSC SOLDER BALL PLACEMENT A3-A8,B2-B9,C1-C10,U3-U8, T2-T9,R1-R10,D10-P10,D1-P1 DEPOPULATED SOLDER BALL LOCATIONS 9. e REPRESENTS THE SOLDER BALL GRID PITCH. TEST PADS MAY BE PRESENT BUT ARE NOT SHOWN. THEY ARE FOR INTERNAL USE ONLY AND ARE NOT SOLDER BALLS. gs5027-l2b/l3b 100-3/21/2014 Document Number: 002-02760 Rev. *H Page 27 of 29 S4041-1B1 Document History Page Document Title: S4041-1B1, 8 GB / 16 GB, 3.0 V e.MMC Flash Document Number: 002-02760 Revision ** ECN Orig. of Change BWHA Submission Date Description of Change 04/17/2014 Global: Changed S4041-1 to S4041-1B1 Features: Operating Temperature Range: changed ‘Extended Commercial’ to ‘Super Commercial’ Physical Diagram: Updated figures: VFBGA 153 — Package Dimensions 13 mm x 11.5 mm x 1.0 mm LBGA 100 — Package Dimensions 18 mm x 14 mm x 1.4 mm Extended CSD Register (EXT_CSD)Updated Extended CSD Register (EXT_CSD) table Ordering Information: Updated Model Number and Controller descriptions Temperature Range: changed ‘Extended Commercial’ to ‘Super Commercial’ *A BWHA 08/05/2014 Key Supported Features: Changed ‘Secure Erase’ to Sanitize Removed Secure Trim Key Supported e.MMC Features: Changed ‘Secure Erase’ to Sanitize. Updated section Removed Secure Trim section Register Values: Updated Extended CSD Register (EXT_CSD) table DC Parameter: Power Consumption (Temperature = 25°C) table: corrected Standby and Sleep (CMD5) values, corrected Note 2 Ordering Information: Valid Combinations table: corrected Model Numbers *B BWHA 10/06/2014 Features: Added Storage Temperature Performance: Corrected Random Read and Random Write General Description: Updated section Recommended System Configuration: Removed section *C BWHA 10/16/2014 Global: Data Sheet designation updated from Advance Information to Preliminary Features: Operating Temperature Range: changed ‘Super Commercial’ to ‘Embedded’ Auto Background Operations: Added Auto Background Operations section Ordering Information: Temperature Range: changed ‘Super Commercial’ to ‘Embedded’ BWHA 11/14/2014 Ordering InformationUpdated Revision description. BWHA 01/12/2015 PerformanceChanged ‘Random Read (IOPS) to 5000. Changed ‘Sequential Read (MB/s)’ to 120. BWHA 02/26/2015 Package Configurations: FBGA 153 (Top View, Balls Down) figure: corrected ball C5 to NC. *D *E *F *G 4963172 BWHA 11/16/2015 Updated to new template. *H 5160239 XILA 03/03/2016 Obsolete datasheet. Document Number: 002-02760 Rev. *H Page 28 of 29 S4041-1B1 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2014-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 002-02760 Rev. *H Revised March 03, 2016 Page 29 of 29 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.