CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM Features Functional Description ■ True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation ■ Organization of 2-Mbit, 4-Mbit, and 9-Mbit devices ■ Pipelined output mode allows fast operation The FLEx36™ family includes 2M, 4M, and 9M pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3 V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time. ■ 0.18-micron Complimentary metal oxide semiconductor (CMOS) for optimum speed and power ■ High-speed clock to data access ■ 3.3 V low power ❐ Active as low as 225 mA (typ) ❐ Standby as low as 55 mA (typ) ■ Mailbox function for message passing ■ Global master reset ■ Separate byte enables on both ports ■ Commercial and industrial temperature ranges ■ IEEE 1149.1-compatible Joint test action group (JTAG) boundary scan ■ 172-Ball fine-pitch ball grid array (FBGA) (1 mm pitch) (15 mm × 15 mm) ■ 176-Pin thin quad plastic flatpack (TQFP) (24 mm × 24 mm × 1.4 mm) The CY7C0853V/CY7C0853AV device in this family has limited features. Please see Address Counter and Mask Register Operations on page 9 for details. ■ Counter wrap around control ❐ Internal mask register controls counter wrap-around ❐ Counter-interrupt flags to indicate wrap-around ❐ Memory block retransmit operation For a complete list of related documentation, click here. ■ Counter readback on address lines ■ Mask register readback on address lines ■ Dual chip enables on both ports for easy depth expansion During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally (more details to follow). The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (CNTINT) flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST). Product Selection Guide Density Part number 2-Mbit (64 K × 36) 4-Mbit (128 K × 36) 9-Mbit (256 K × 36) CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Max. speed (MHz) 167 167 133 Max. access time - clock to data (ns) 4.0 4.0 4.7 Typical operating current (mA) 225 225 270 Package 176-pin TQFP, 172-ball FBGA 176-pin TQFP, 172-ball FBGA Cypress Semiconductor Corporation Document Number: 38-06070 Rev. *O • 198 Champion Court • 172-ball FBGA San Jose, CA 95134-1709 • 408-943-2600 Revised November 18, 2015 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Logic Block Diagram The Logic Block Diagram is as follows. [1] OEL R/WL OER R/WR B0L B0R B1L B1R B2L B2R B3L B3R CE0L CE1L DQ27L–DQ35L DQ18L–DQ26L DQ9L–DQ17L DQ0L–DQ8L CE0R CE1R 9 9 9 9 I/O Control 9 I/O Control 9 9 9 Addr. Read Back DQ27R–DQ35R DQ18R–DQ26R DQ9R–DQ17R DQ0R–DQ8R Addr. Read Back True Dual-Ported RAM Array A0L–A17L 18 18 Mask Register Mask Register A0R–A17R CNT/MSKR CNT/MSKL ADSL Counter/ Address Register CNTENL CNTRSTL CLKL Address Address Decode Decode Mirror Reg Interrupt Logic CNTEN CNTRSTR Mirror Reg CNTINTL INTL ADS Counter/ Address Register MRST Reset Logic TMS TDI TCK JTAG TDO CLKR CNTINTR Interrupt Logic INTR Note 1. 9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits. Document Number: 38-06070 Rev. *O Page 2 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 7 Functional Overview ........................................................ 8 Master Reset ............................................................... 8 Mailbox Interrupts ........................................................ 8 Read/Write and Enable Operation (Any Port) ............. 8 Address Counter and Mask Register Operations ........ 9 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13 Performing a TAP Reset ........................................... 13 Performing a Pause/Restart ...................................... 13 Identification Register Definitions ................................ 13 Scan Registers Sizes ..................................................... 13 Instruction Identification Codes .................................... 13 Maximum Ratings ........................................................... 14 Operating Range ............................................................. 14 Electrical Characteristics ............................................... 14 Capacitance .................................................................... 15 AC Test Load and Waveforms ....................................... 15 Switching Characteristics .............................................. 16 JTAG Timing ................................................................... 18 Switching Waveforms .................................................... 19 Document Number: 38-06070 Rev. *O Ordering Information ...................................................... 30 256 K × 36 (9 M) 3.3 V Synchronous CY7C0853V/CY7C0853AV Dual-Port SRAM ................... 30 128 K × 36 (4 M) 3.3 V Synchronous CY7C0852V/CY7C0852AV Dual-Port SRAM ................... 30 64 K × 36 (2 M) 3.3 V Synchronous CY7C0851V/CY7C0851AV Dual-Port SRAM ................... 30 Ordering Code Definitions ......................................... 31 Package Diagrams .......................................................... 32 Acronyms ........................................................................ 35 Document Conventions ................................................. 35 Units of Measure ....................................................... 35 Document History Page ................................................. 36 Sales, Solutions, and Legal Information ...................... 39 Worldwide Sales and Design Support ....................... 39 Products .................................................................... 39 PSoC® Solutions ...................................................... 39 Cypress Developer Community ................................. 39 Technical Support ..................................................... 39 Page 3 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Pin Configurations Figure 1. 172-ball BGA pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A DQ32L DQ30L CNTINTL VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS CNTINTR DQ30R DQ32R B A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R C NC A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R NC D A2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R E A4L A5L CE1L B0L VDD VSS VDD VDD B0R CE1R A5R A4R F VDD A6L A7L B1L VDD VSS B1R A7R A6R VDD G OEL B2L B3L CE0L CE0R B3R B2R OER H VSS R/WL A8L CLKL CLKR A8R R/WR VSS J A9L A10L VSS ADSL VSS VDD ADSR MRST A10R A9R K A11L A12L A15L[2] CNTRSTL VDD VDD VSS VDD CNTRSTR A15R[2] A12R A11R L CNT/MSKL A13L CNTENL DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R CNTENR A13R CNT/MSKR M A16L[2] A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R[2] N DQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R P DQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R CY7C0851V/CY7C0851AV CY7C0852V/CY7C0851AV Note 2. For CY7C0851V/CY7C0851AV, pins M1 and M14 are NC. Document Number: 38-06070 Rev. *O Page 4 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Pin Configurations (continued) Figure 2. 172-ball BGA pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A DQ32L DQ30L NC VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS NC DQ30R DQ32R B A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R C A17L A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R A17R D A2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R E A4L A5L VDD B0L VDD VSS VDD VDD B0R VDD A5R A4R F VDD A6L A7L B1L VDD VSS B1R A7R A6R VDD G OEL B2L B3L VSS VSS B3R B2R OER H VSS R/WL A8L CLKL CLKR A8R R/WR VSS J A9L A10L VSS VSS VSS VDD VSS MRST A10R A9R K A11L A12L A15L VDD VDD VDD VSS VDD VDD A15R A12R A11R L VDD A13L VSS DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R VSS A13R VDD M A16L A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R N DQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R P DQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R Document Number: 38-06070 Rev. *O CY7C0853V/CY7C0853AV Page 5 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Pin Configurations (continued) A2L 4 5 6 A3L VSS VDD 7 8 9 A4L A5L 10 11 A6L CE1L B2L 12 13 14 15 16 17 B3L 18 OEL CE0L 19 20 21 22 A1L A7L B0L B1L VDD VDD VSS VSS R/WL CLKL VSS ADSL CNTENL CNTRSTL CNT/MSKL DQ32R DQ33R 133 DQ31R DQ30R VSS VDD 136 135 134 137 DQ27R DQ29R DQ28R 139 138 140 DQ16R CNTINTR INTR 142 141 143 DQ14R DQ17R DQ15R 145 144 146 VSS DQ13R 148 147 VDD 150 149 DQ11R DQ12R 151 DQ10R 153 152 DQ9L DQ9R 154 DQ10L 156 155 DQ12L DQ11L 157 VDD 159 158 DQ13L VSS 160 DQ14L 162 161 DQ15L DQ17L 163 DQ16L 165 164 INTL CNTINTL 166 DQ27L 168 167 DQ28L DQ29L 169 DQ30L 171 170 172 VDD VSS DQ31L 2 3 174 173 1 DQ35L NC A0L DQ33L DQ32L DQ34L 176 175 Figure 3. 176-pin TQFP pinout (Top View) 132 131 130 129 128 127 126 125 124 23 24 25 26 27 A1R A2R A3R VSS VDD A4R A5R A6R 120 119 A7R B0R 118 117 116 115 B1R 113 112 111 110 109 108 107 106 105 104 103 28 29 30 DQ35R NC A0R 123 122 121 114 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV DQ34R CE1R B2R B3R OER CE0R VDD VDD VSS VSS R/WR CLKR MRST ADSR CNTENR CNTRSTR CNT/MSKR 102 101 A11L A12L 31 32 33 34 35 36 VSS 37 96 VSS VDD A13L 38 39 40 95 VDD A13R Document Number: 38-06070 Rev. *O A8R A9R A10R A11R A12R A14R A15R[2] A16R[2] DQ24R 88 DQ20R DQ23R DQ26R DQ22R 85 86 87 84 VSS VDD DQ21R 82 83 81 DQ19R DQ25R DQ18R 79 80 78 TMS TCK DQ8R 76 77 75 DQ6R DQ7R DQ5R 73 74 71 72 VSS DQ4R VDD 70 68 69 DQ2R DQ3R DQ1R 67 65 66 DQ0L DQ0R DQ1L 64 62 63 DQ3L DQ2L VDD 61 59 60 DQ4L VSS DQ5L 58 56 57 DQ7L DQ6L DQ8L 55 53 54 TDI TDO DQ18L 52 50 51 DQ25L DQ19L DQ21L 49 47 48 DQ24L DQ20L 41 42 43 44 VDD VSS A15L[2] A16L[2] 94 93 92 91 90 89 DQ22L A14L 98 97 45 46 A10L 100 99 DQ26L DQ23L A8L A9L Page 6 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Pin Definitions Left Port A0L–A17L [3] Right Port A0R–A17R [3] Description Address inputs. ADSL[4] ADSR[4] Address strobe input. Used as an address qualifier. This signal should be asserted LOW for the part using the externally supplied address on the address pins and for loading this address into the burst address counter. CE0L[4] CE0R[4] Active LOW chip enable input. CE1L[4] CE1R[4] Active HIGH chip enable input. CLKL CLKR Clock signal. Maximum clock input rate is fMAX. CNTENL[4] CNTENR[4] Counter enable input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are asserted LOW. CNTRSTL[4] CNTRSTR[4] Counter reset input. Asserting this signal LOW resets to zero the unmasked portion of the burst address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN. CNT/MSKL[4] CNT/MSKR[4] Address counter mask register enable input. Asserting this signal LOW enables access to the mask register. When tied HIGH, the mask register is not accessible and the address counter operations are enabled based on the status of the counter control signals. DQ0L–DQ35L DQ0R–DQ35R Data bus input/output. OEL OER Output enable input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. INTL INTR Mailbox interrupt flag output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. CNTINTL[4] CNTINTR[4] Counter interrupt output. This pin is asserted LOW when the unmasked portion of the counter is incremented to all “1s.” R/WL R/WR Read/Write enable input. Assert this pin LOW to write to, or HIGH to Read from the dual port memory array. B0L–B3L B0R–B3R Byte select inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. MRST Master reset input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power up. TMS JTAG test mode select input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. TDI JTAG test data input. Data on the TDI input is shifted serially into selected registers. TCK JTAG test clock input. TDO JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. VSS Ground inputs. VDD Power inputs. Notes 3. 9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits. 4. These pins are not available for CY7C0853V/CY7C0853AV device. Document Number: 38-06070 Rev. *O Page 7 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Functional Overview is the mailbox for the right port and 3FFFE is the mailbox for the left port. Table 1 shows that in order to set the INTR flag, a Write operation by the left port to address 3FFFF asserts INTR LOW. At least one byte has to be active for a Write to generate an interrupt. A valid Read of the 3FFFF location by the right port resets INTR HIGH. At least one byte has to be active in order for a Read to reset the interrupt. When one port Writes to the other port’s mailbox, the INT of the port that the mailbox belongs to is asserted LOW. The INT is reset when the owner (port) of the mailbox Reads the contents of the mailbox. The interrupt flag is set in a flow-thru mode (that is it follows the clock edge of the writing port). Also, the flag is reset in a flow-thru mode (that is it follows the clock edge of the reading port). Master Reset The FLEx36 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchronously to the clocks. The MRST initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). The MRST also forces the Mailbox Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH. The MRST must be performed on the FLEx36 family devices after power up. Mailbox Interrupts Each port can read the other port’s mailbox without resetting the interrupt. And each port can write to its own mailbox without setting the interrupt. If an application does not require message passing, INT pins should be left open. The upper two memory locations may be used for message passing and permit communications between ports. Table 1 shows the interrupt operation for both ports of CY7C853V/CY7C0853AV. The highest memory location, 3FFFF Table 1. Interrupt Operation Example [5, 6, 7, 8, 9] Left Port Function R/WL Right Port CEL A0L–17L INTL R/WR CER A0R–17R INTR Set right INTR flag L L 3FFFF X X X X L Reset right INTR flag X X X X H L 3FFFF H Set left INTL flag X X X L L L 3FFFE X Reset left INTL flag H L 3FFFE H X X X X Read/Write and Enable Operation (Any Port) Table 2. Read/Write and Enable Operation (Any Port) [12, 13, 10, 11] Inputs OE Outputs Operation CE0 CE1 R/W DQ0–DQ35 X H X X High Z Deselected X X L X High Z Deselected X L H L DIN Write L L H H DOUT Read L H X High Z Outputs disabled H CLK X Notes 5. 9 M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits. 6. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge. 7. OE is “Don’t Care” for mailbox operation. 8. At least one of B0, B1, B2, or B3 must be LOW. 9. A16x is a NC for CY7C0851V/CY7C0851AV, therefore the Interrupt Addresses are FFFF and FFFE. 10. OE is an asynchronous input signal. 11. When CE changes state, deselection and Read happen after one cycle of latency. 12. 9 M device has 18 address bits, 4M device has 17 address bits, and 2 M device has 16 address bits. 13. “X” = “Don’t Care”, “H” = HIGH, “L” = LOW. Document Number: 38-06070 Rev. *O Page 8 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Address Counter and Mask Register Operations [14] This section describes the features only apply to CY7C0851V / CY7C0851AV / CY7C0852V / CY7C0852AV devices, but not to the CY7C0853V/CY7C0853AV device. Each port of these devices has a programmable burst address counter. The burst counter contains three registers: a counter register, a mask register, and a mirror register. The counter register contains the address used to access the RAM array. It is changed only by the Counter Load, Increment, Counter Reset, and by master reset (MRST) operations. The mask register value affects the Increment and Counter Reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is changed only by the Mask Load and Mask Reset operations, and by the MRST. The mask register defines the counting range of the counter register. It divides the counter register into two regions: zero or more “0s” in the most significant bits define the masked region, one or more “1s” in the least significant bits define the unmasked region. Bit 0 may also be “0”, masking the least significant counter bit and causing the counter to increment by two instead of one. The mirror register is used to reload the counter register on increment operations (see “retransmit”, below). It always contains the value last loaded into the counter register, and is changed only by the Counter Load operation, and by the MRST. Table 3 summarizes the operation of these registers and the required input control signals. The MRST control signal is asynchronous. All the other control signals in Table 3 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the port’s CLK. All these counter and mask operations are independent of the port’s chip enable inputs (CE0 and CE1). Counter enable (CNTEN) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. A port’s burst counter is loaded when the port’s address strobe (ADS) and CNTEN signals are LOW. When the port’s CNTEN is asserted and the ADS is deasserted, the address counter increments on each LOW to HIGH transition of that port’s clock signal. This will Read/Write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array, and loops back to the start. Counter reset (CNTRST) is used to reset the unmasked portion of the burst counter to 0s. A counter-mask register is used to control the counter wrap. Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port) [15, 16] CLK X MRST L CNT/MSK CNTRST X X ADS X CNTEN Operation X Master reset Description Reset address counter to all 0s and mask register to all 1s. Reset counter unmasked portion to all 0s. H H L X X Counter reset H H H L L Counter load H H H L H H H H H L Load counter with external address value presented on address lines. Counter readback Read out counter internal value on address lines. Counter increment Internally increment address counter value. H H H H H Counter hold H L L X X Mask reset H L H L L Mask load H L H L H Mask readback H L H H X Reserved Constantly hold the address value for multiple clock cycles. Reset mask register to all 1s. Load mask register with value presented on the address lines. Read out mask register value on address lines. Operation undefined Notes 14. This section describes the CY7C0852V/CY7C0852AV, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851V/CY7C0851AV has 16 address bits, register lengths of 16 bits, and a maximum address value of FFFF. 15. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW. 16. Counter operation and mask register operation is independent of chip enables. Document Number: 38-06070 Rev. *O Page 9 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Counter Reset Operation Counter Interrupt All unmasked bits of the counter are reset to “0.” All masked bits remain unchanged. The mirror register is loaded with the value of the burst counter. A Mask Reset followed by a Counter Reset will reset the counter and mirror registers to 00000, as will master reset (MRST). The counter interrupt (CNTINT) is asserted LOW when an increment operation results in the unmasked portion of the counter register being all “1s.” It is deasserted HIGH when an Increment operation results in any other value. It is also de-asserted by Counter Reset, Counter Load, Mask Reset and Mask Load operations, and by MRST. Counter Load Operation The address counter and mirror registers are both loaded with the address value presented at the address lines. Counter Readback Operation The internal value of the counter register can be read out on the address lines. Readback is pipelined; the address is valid tCA2 after the next rising edge of the port’s clock. If address readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) is three-stated. Figure 4 on page 11 shows a block diagram of the operation. Counter Increment Operation Once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addressing the entire memory array. Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be a “1” for a counter bit to change. The counter register is incremented by 1 if the least significant bit is unmasked, and by 2 if it is masked. If all unmasked bits are “1”, the next increment wraps the counter back to the initially loaded value. If an Increment results in all the unmasked bits of the counter being “1s”, a counter interrupt flag (CNTINT) is asserted. The next Increment returns the counter register to its initial value, which was stored in the mirror register. The counter address can instead be forced to loop to 00000 by externally connecting CNTINT to CNTRST.[17] An increment that results in one or more of the unmasked bits of the counter being “0” deasserts the counter interrupt flag. The example in Figure 5 on page 12 shows the counter mask register loaded with a mask value of 0003Fh unmasking the first 6 bits with bit “0” as the LSB and bit “16” as the MSB. The maximum value the mask register can be loaded with is 1FFFFh. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of 8h. The base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. The counter address starts at address 8h. The counter increments its internal address value till it reaches the mask register value of 3Fh. The counter wraps around the memory block to location 8h at the next count. CNTINT is issued when the counter reaches its maximum value. Counter Hold Operation The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. Retransmit Retransmit is a feature that allows the Read of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal “mirror register” is used to store the initially loaded address counter value. When the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this “mirror register”. If the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the “mirror register”. Thus, the repeated access of the same data is allowed without the need for any external logic. Mask Reset Operation The mask register is reset to all “1s”, which unmasks every bit of the counter. Master reset (MRST) also resets the mask register to all “1s”. Mask Load Operation The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment operations. Permitted values are of the form 2n – 1 or 2n – 2. From the most significant bit to the least significant bit, permitted values have zero or more “0s”, one or more “1s”, or one “0”. Thus 1FFFF, 003FE, and 00001 are permitted values, but 1F0FF, 003FC, and 00000 are not. Mask Readback Operation The internal value of the mask register can be read out on the address lines. Readback is pipelined; the address is valid tCM2 after the next rising edge of the port’s clock. If mask readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) is three-stated. Figure 4 on page 11 shows a block diagram of the operation. Counting by Two When the least significant bit of the mask register is “0,” the counter increments by two. This may be used to connect the CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV as a 72-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 72-bit data in even memory locations, and the other half in odd memory locations. Note 17. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together. Document Number: 38-06070 Rev. *O Page 10 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Figure 4. Counter, Mask, and Mirror Logic Block Diagram [18] CNT/MSK CNTEN Decode Logic ADS CNTRST MRST Bidirectional Address Lines Mask Register Counter/ Address Register Address RAM Decode Array CLK Load/Increment 17 From Address Lines Mirror Counter 1 To Readback and Address Decode 1 0 17 From Mask Register From Mask From Counter 0 Increment Logic Wrap 17 17 17 Bit 0 17 +1 Wrap Detect 1 +2 Wrap 0 1 17 To Counter 0 Note 18. 9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits. Document Number: 38-06070 Rev. *O Page 11 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Figure 5. Programmable Counter-Mask Register Operation [19, 20] Example: Load Counter-Mask Register = 3F CNTINT H 0 0 0s 216 215 H X X Xs 216 215 Max Address Register L X X H X X 216 215 1 1 1 1 Unmasked Address X 0 0 1 0 0 Xs X 1 1 1 1 Mask Register bit-0 0 26 25 24 23 22 21 20 216 215 Max + 1 Address Register 1 26 25 24 23 22 21 20 Masked Address Load Address Counter = 8 0 1 1 Address Counter bit-0 1 26 25 24 23 22 21 20 Xs X 0 0 1 0 0 0 26 25 24 23 22 21 20 Notes 19. 9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits. 20. The “X” in this diagram represents the counter upper bits. Document Number: 38-06070 Rev. *O Page 12 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C0851V / CY7C0851AV / CY7C0852V / CY7C0852AV / CY7C0853V / CY7C0853AV incorporates an IEEE 1149.1 serial boundary scan [21] test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs. The TAP operates using JEDEC-standard 3.3 V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the devices, and may be performed while the devices are operating. An MRST must be performed on the devices after power-up. Performing a Pause/Restart When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan chain outputs the next bit in the chain twice. For example, if the value expected from the chain is 1010101, the device outputs a 11010101. This extra bit causes some testers to report an erroneous failure for the devices in a scan test. Therefore the tester should be configured to never enter the PAUSE-DR state. Identification Register Definitions Instruction Field Value Description Revision number (31:28) 0h Cypress device ID (27:12) C001h Defines Cypress part number for the CY7C0851V/CY7C0851AV C002h Defines Cypress part number for the CY7C0852V/CY7C0852AV and CY7C0853V/CY7C0853AV Cypress JEDEC ID (11:1) Reserved for version number. 034h ID register presence (0) Allows unique identification of the DP family device vendor. 1 Indicates the presence of an ID register. Scan Registers Sizes Register Name Bit Size Instruction 4 Bypass 1 Identification 32 Boundary Scan n[22] Instruction Identification Codes Instruction EXTEST Code Description 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. BYPASS 1111 Places the BYR between TDI and TDO. IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO. HIGHZ 0111 Places BYR between TDI and TDO. Forces all CY7C0851AV / CY7C0852AV / CY7C0853AV output drivers to a High Z state. CLAMP 0100 Controls boundary to 1/0. Places BYR between TDI and TDO. SAMPLE/PRELOAD 1000 Captures the input/output ring contents. Places BSR between TDI and TDO. 1100 Resets the non-boundary scan logic. Places BYR between TDI and TDO. NBSRST RESERVED All other codes Other combinations are reserved. Do not use other than the above. Notes 21. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance. 22. See details in the device BSDL files. Document Number: 38-06070 Rev. *O Page 13 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV DC input voltage ........................... –0.5 V to VDD + 0.5 V [24] Maximum Ratings Exceeding maximum ratings [23] may impair the useful life of the device. These user guidelines are not tested. Storage temperature .............................. –65 °C to + 150 °C Ambient temperature with Power applied ......................................... –55 °C to + 125 °C Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (JEDEC JESD22-A114-2000B) .............................. > 2000 V Latch-up current .................................................... > 200 mA Operating Range Supply voltage to ground potential .............–0.5 V to + 4.6 V DC voltage applied to Outputs in High Z state ....................... –0.5 V to VDD + 0.5 V Range Ambient Temperature VDD 0 °C to +70 °C 3.3 V ± 165 mV –40 °C to +85 °C 3.3 V ± 165 mV Commercial Industrial Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IOZ IIX1 IIX2 ICC ISB1[25] ISB2[25] ISB3[25] ISB4[25] ISB5 Description Output HIGH voltage (VDD = Min., IOH= –4.0 mA) Output LOW voltage (VDD = Min., IOL= +4.0 mA) Input HIGH voltage Input LOW voltage Output leakage current Input leakage current except TDI, TMS, MRST Input leakage current TDI, TMS, MRST CY7C0851V / Operating current for CY7C0851AV / (VDD = Max.,IOUT = 0 mA), CY7C0852V / Outputs disabled CY7C0852AV CY7C0853V / CY7C0853AV Standby current (both ports TTL level) CEL and CER VIH, f = fMAX Standby current (one port TTL level) CEL | CER VIH, f = fMAX Standby current (both ports CMOS level) CEL and CER VDD – 0.2 V, f = 0 Standby current (one port CMOS level) CEL | CER VIH, f = fMAX CY7C0853V / Operating current (VDD = Max, IOUT = 0 mA, f = 0) CY7C0853AV Outputs disabled -167 -133 -100 Unit Min Typ Max Min Typ Max Min Typ Max 2.4 – – 2.4 – – 2.4 – – V – – 0.4 – – 0.4 – – 0.4 V 2.0 – – 2.0 – – 2.0 – – V – – 0.8 – – 0.8 – – 0.8 V –10 – 10 –10 – 10 –10 – 10 A –10 – 10 –10 – 10 –10 – 10 A –0.1 – 1.0 –0.1 – 1.0 –0.1 – 1.0 mA – 225 300 – 225 300 – – – mA – – – – 270 400 – 200 310 – 90 115 – 90 115 – 90 115 mA – 160 210 – 160 210 – 160 210 mA – 55 75 – 55 75 – 55 75 mA – 160 210 – 160 210 – 160 210 mA – – – – 70 100 – 70 100 mA Notes 23. The voltage on any input or I/O pin can not exceed the power pin during power up. 24. Pulse width < 20 ns. 25. ISB1, ISB2, ISB3 and ISB4 are not applicable for CY7C0853V / CY7C0853AV because it can not be powered down by using chip enable pins. Document Number: 38-06070 Rev. *O Page 14 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Capacitance Part Number [26] Parameter Description Test Conditions Unit 13 pF Input capacitance 10 pF CY7C0853V / CY7C0853AV CIN Input capacitance 22 pF Output capacitance 20 pF COUT TA = 25 °C, f = 1 MHz, VDD = 3.3 V Max CY7C0851V / CY7C0851AV / CIN CY7C0852V / CY7C0852AV COUT Output capacitance AC Test Load and Waveforms Figure 6. AC Test Load and Waveforms 3.3 V Z0 = 50 R = 50 R1 = 590 OUTPUT OUTPUT C = 10 pF C = 5 pF VTH = 1.5 V (a) Normal Load (Load 1) R2 = 435 (b) Three-state Delay (Load 2) 3.0 V 90% ALL INPUT PULSES 10% VSS < 2 ns 90% 10% < 2 ns Note 26. COUT also references CI/O. Document Number: 38-06070 Rev. *O Page 15 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Characteristics Over the Operating Range -167 Parameter Description -133 CY7C0851V / CY7C0851AV / CY7C0852V / CY7C0852AV Min Max CY7C0851V / CY7C0851AV / CY7C0852V / CY7C0852AV Min Max -100 CY7C0853V / CY7C0853AV CY7C0853V / CY7C0853AV Min Max Min Max Unit fMAX2 Maximum operating frequency – 167 – 133 – 133 – 100 MHz tCYC2 Clock cycle time 6.0 – 7.5 – 7.5 – 10.0 – ns tCH2 Clock HIGH time 2.7 – 3.0 – 3.0 – 4.0 – ns tCL2 Clock LOW time 2.7 – 3.0 – 3.0 – 4.0 – ns tR [27] Clock rise time – 2.0 – 2.0 – 2.0 – 3.0 ns tF[27] Clock fall time – 2.0 – 2.0 – 2.0 – 3.0 ns tSA Address setuptime 2.3 – 2.5 – 2.5 – 3.0 – ns tHA Address hold time 0.6 – 0.6 – 0.6 – 0.6 – ns tSB Byte select setup time 2.3 – 2.5 – 2.5 – 3.0 – ns tHB Byte select hold time 0.6 – 0.6 – 0.6 – 0.6 – ns tSC Chip enable setup time 2.3 – 2.5 – NA – NA – ns tHC Chip enable hold time 0.6 – 0.6 – NA – NA – ns tSW R/W setup time 2.3 – 2.5 – 2.5 – 3.0 – ns tHW R/W hold time 0.6 – 0.6 – 0.6 – 0.6 – ns tSD Input data setup time 2.3 – 2.5 – 2.5 – 3.0 – ns tHD Input data hold time 0.6 – 0.6 – 0.6 – 0.6 – ns tSAD ADS setup time 2.3 – 2.5 – NA – NA – ns tHAD ADS hold time 0.6 – 0.6 – NA – NA – ns tSCN CNTEN setup time 2.3 – 2.5 – NA – NA – ns tHCN CNTEN hold time 0.6 – 0.6 – NA – NA – ns tSRST CNTRST setup time 2.3 – 2.5 – NA – NA – ns tHRST CNTRST hold time 0.6 – 0.6 – NA – NA – ns tSCM CNT/MSK setup time 2.3 – 2.5 – NA – NA – ns tHCM CNT/MSK hold time 0.6 – 0.6 – NA – NA – ns tOE Output enable to data valid – 4.0 – 4.4 – 4.7 – 5.0 ns tOLZ[28, 29] OE to Low Z 0 – 0 – 0 – 0 – ns tOHZ[28, 29] OE to High Z 0 4.0 0 4.4 0 4.7 0 5.0 ns tCD2 Clock to data valid – 4.0 – 4.4 – 4.7 – 5.0 ns tCA2 Clock to counter address valid – 4.0 – 4.4 – NA – NA ns tCM2 Clock to mask register readback valid – 4.0 – 4.4 – NA – NA ns tDC Data output hold after clock HIGH 1.0 – 1.0 – 1.0 – 1.0 – ns Note 27. Except JTAG signals (tr and tf < 10 ns [max.]). 28. This parameter is guaranteed by design, but it is not production tested. 29. Test conditions used are Load 2. Document Number: 38-06070 Rev. *O Page 16 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Characteristics (continued) Over the Operating Range -167 Parameter Description -133 CY7C0851V / CY7C0851AV / CY7C0852V / CY7C0852AV Min Max Clock HIGH to output High Z 0 Clock HIGH to output Low Z 1.0 tSINT Clock to INT set time tRINT Clock to INT reset time tSCINT tRCINT tCKHZ[30, 31] tCKLZ[30, 31] CY7C0851V / CY7C0851AV / CY7C0852V / CY7C0852AV -100 CY7C0853V / CY7C0853AV CY7C0853V / CY7C0853AV Min Max Min Max Unit Min Max 4.0 0 4.4 0 4.7 0 5.0 ns 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns Clock to CNTINT set time 0.5 5.0 0.5 5.7 NA NA NA NA ns Clock to CNTINT reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns 5.2 – 6.0 – 6.0 – 8.0 – ns 7.0 – 7.5 – 7.5 – 10.0 – ns Port to Port Delays tCCS Clock to clock skew Master Reset Timing tRS Master reset pulse width tRSS Master reset setup time 6.0 – 6.0 – 6.0 – 8.5 – ns tRSR Master reset recovery time 6.0 – 7.5 – 7.5 – 10.0 – ns tRSF Master reset to outputs inactive – 10.0 – 10.0 – 10.0 – 10.0 ns tRSCNTINT Master reset to counter interrupt flag reset time – 10.0 – 10.0 – NA – NA ns Notes 30. This parameter is guaranteed by design, but it is not production tested. 31. Test conditions used are Load 2. Document Number: 38-06070 Rev. *O Page 17 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV JTAG Timing Parameter 167/133/100 Description Min Max Unit fJTAG Maximum JTAG TAP controller frequency – 10 MHz tTCYC TCK clock cycle time 100 – ns tTH TCK clock HIGH time 40 – ns tTL TCK clock LOW Time 40 – ns tTMSS TMS setup to TCK clock rise 10 – ns tTMSH TMS hold after TCK clock rise 10 – ns tTDIS TDI setup to TCK clock rise 10 – ns tTDIH TDI hold after TCK clock rise 10 – ns tTDOV TCK clock LOW to TDO valid – 30 ns tTDOX TCK clock LOW to TDO invalid 0 – ns Figure 7. JTAG Switching Waveform tTH Test Clock TCK tTMSS tTL tTCYC tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO Document Number: 38-06070 Rev. *O tTDOX tTDOV Page 18 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Waveforms Figure 8. Master Reset tRS MRST ALL ADDRESS/ DATA LINES tRSF tRSS ALL OTHER INPUTS tRSR INACTIVE ACTIVE TMS CNTINT INT TDO Figure 9. Read Cycle [32, 33, 34, 35, 36] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSB tHB tSW tSA tHW tHA tSC tHC B0–B3 R/W ADDRESS DATAOUT An An+1 1 Latency An+2 tDC tCD2 Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tOLZ OE tOE Notes 32. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge. 33. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge. 34. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH. 35. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock. 36. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document Number: 38-06070 Rev. *O Page 19 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Waveforms (continued) Figure 10. Bank Select Read [37, 38] tCH2 tCYC2 tCL2 CLK tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE(B1) tCD2 tHC tSC tCD2 tHA tSA tDC A0 ADDRESS(B2) A1 tCKHZ Q3 Q1 Q0 DATAOUT(B1) tCD2 tCKHZ tDC tCKLZ A3 A2 A4 A5 tHC tSC CE(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 Q4 Q2 tCKLZ Figure 11. Read-to-Write-to-Read (OE = LOW) [36, 39, 40, 41, 42] tCH2 tCYC2 tCKLZ tCL2 CLK CE tSC tHC tSW tHW R/W tSW tHW An ADDRESS tSA An+1 An+2 tHA DATAIN An+2 An+3 An+4 tSD tHD tCD2 tCKHZ Dn+2 Qn DATAOUT tCD2 tCD2 Qn+1 Qn+3 tCKLZ READ NO OPERATION WRITE READ Notes 37. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 38. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH. 39. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 40. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. 41. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 42. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document Number: 38-06070 Rev. *O Page 20 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Waveforms (continued) Figure 12. Read-to-Write-to-Read (OE Controlled) [43, 44, 45, 46] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSW tHW R/W tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA tHA tSD tHD Dn+2 DATAIN Dn+3 tCD2 DATAOUT tCD2 tCD2 Qn Qn+1 Qn+4 tOHZ OE READ WRITE READ Figure 13. Read with Address Counter Advance [45] tCH2 tCYC2 tCL2 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx–1 READ EXTERNAL ADDRESS tCD2 Qx Qn tDC READ WITH COUNTER Qn+1 COUNTER HOLD Qn+2 Qn+3 READ WITH COUNTER Notes 43. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK. Numbers are for reference only 44. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 45. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 46. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document Number: 38-06070 Rev. *O Page 21 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Waveforms (continued) Figure 14. Write with Address Counter Advance [47] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD Dn+1 tHD WRITE EXTERNAL ADDRESS Dn+1 WRITE WITH COUNTER Dn+2 Dn+3 WRITE COUNTER HOLD Dn+4 WRITE WITH COUNTER Figure 15. Disabled to Read-to-Read to Read-to-Write tCL2 tCYC2 tCH2 CLK tSC tHC CE tSW tHW R/W tSW tHW tHA tSA An ADDRESS tHA tSA An+1 An+4 An+3 An+2 OE tSD DATAIN tHD Dn+3 tCD2 DATAOUT Qn DISABLED READ READ Qn+1 READ Qn+2 WRITE READ Note 47. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document Number: 38-06070 Rev. *O Page 22 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Waveforms (continued) Figure 16. Disabled to Write- to- Read to Write-to-Read tCL2 tCYC2 tCH2 CLK tSC tHC CE tHW tSW R/W tSA tHA ADDRESS An An+4 An+3 An+2 An+1 tOE OE tSD tHD DATAIN Dn Dn+2 tCD2 Qn+3 Qn+1 DATAOUT DISABLED WRITE READ READ WRITE READ Figure 17. Disabled-to-Read to Disabled-to-Write tCL2 tCYC2 tCH2 CLK tSC tHC CE R/W tSW tHW ADDRESS tSA An+4 An+3 An+2 An+1 An tHA tOE OE tOHZ tSD tHD DATAIN Dn+2 tCD2 DATAOUT Qn+3 Qn DISABLED Document Number: 38-06070 Rev. *O READ DISABLED WRITE READ READ Page 23 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Waveforms (continued) Figure 18. Read-to-Readback to Read-to-Read (R/W = HIGH) tCL2 tCYC2 tCH2 CLK tHAD tSAD ADS CNTEN tSCN tHCN tSA An+1 ADDRESS COUNTER INTERNAL ADDRESS tHA An An+1 An+2 An+3 An+4 OE DATAOUT Qn+1 READ INCREMENT Document Number: 38-06070 Rev. *O NO OPERATION READBACK INCREMENT Qn+3 Qn+2 READ READ INCREMENT READ INCREMENT Page 24 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Waveforms (continued) Figure 19. Counter Reset [48, 49, 50] tCYC2 tCH2 tCL2 CLK tSA INTERNAL ADDRESS Ax tSW tHW tSD tHD An 1 0 Ap Am An ADDRESS tHA Ap Am R/W ADS CNTEN tSRST tHRST CNTRST DATAIN D0 tCD2 tCD2 [50] DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 tCKLZ READ ADDRESS 0 READ ADDRESS 1 Q1 READ ADDRESS An Qn READ ADDRESS Am Notes 48. CE0 = B0–B3 = LOW; CE1 = MRST = CNT/MSK = HIGH. 49. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. 50. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document Number: 38-06070 Rev. *O Page 25 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Waveforms (continued) Figure 20. Readback State of Address Counter or Mask Register [51, 52, 53, 54] tCYC2 tCH2 tCL2 CLK tCA2 or tCM2 tSA tHA EXTERNAL ADDRESS A0–A16 An* An INTERNAL ADDRESS An+1 An An+2 An+4 An+3 tSAD tHAD ADS tSCN tHCN CNTEN tCD2 DATAOUT Qx-2 LOAD EXTERNAL ADDRESS tCKHZ Qx-1 Qn READBACK COUNTER INTERNAL ADDRESS INCREMENT tCKLZ Qn+1 Qn+2 Qn+3 Notes 51. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 52. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle. 53. Address in input mode. Host can drive address bus after tCKHZ. 54. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document Number: 38-06070 Rev. *O Page 26 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Waveforms (continued) Figure 21. Left_Port (L_Port) Write to Right_Port (R_Port) Read [55, 56, 57] tCH2 tCYC2 tCL2 CLKL tHA tSA L_PORT ADDRESS An tSW tHW R/WL tCKHZ tSD L_PORT tCKLZ Dn DATAIN CLKR tHD tCYC2 tCL2 tCCS tCH2 tSA R_PORT ADDRESS tHA An R/WR tCD2 R_PORT Qn DATAOUT tDC Notes 55. CE0 = OE = ADS = CNTEN = B0 – B3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 56. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data is Read out. 57. If tCCS < minimum specified value, then R_Port is Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS > minimum specified value, then R_Port is Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock. Document Number: 38-06070 Rev. *O Page 27 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Waveforms (continued) Figure 22. Counter Interrupt and Retransmit [58, 59, 60, 61, 62] tCH2 tCYC2 tCL2 CLK tSCM tHCM CNT/MSK ADS CNTEN COUNTER INTERNAL ADDRESS 1FFFC 1FFFD 1FFFE tSCINT 1FFFF Last_Loaded Last_Loaded +1 tRCINT CNTINT Notes 58. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value 59. CE0 = OE = B0–B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 60. CNTINT is always driven. 61. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 62. The mask register assumed to have the value of 1FFFFh. Document Number: 38-06070 Rev. *O Page 28 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Switching Waveforms (continued) Figure 23. MailBox Interrupt Timing [63, 64, 65, 66, 67] tCH2 tCYC2 tCL2 CLKL tSA L_PORT ADDRESS tHA 3FFFF An+1 An An+2 An+3 tSINT tRINT INTR tCH2 tCYC2 tCL2 CLKR tSA R_PORT ADDRESS Am tHA Am+1 3FFFF Am+3 Am+4 Notes 63. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 64. Address “3FFFF” is the mailbox location for R_Port of a 9M device. 65. L_Port is configured for Write operation, and R_Port is configured for Read operation. 66. At least one byte enable (B0 – B3) is required to be active during interrupt operations. 67. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock. Document Number: 38-06070 Rev. *O Page 29 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. 256 K × 36 (9 M) 3.3 V Synchronous CY7C0853V/CY7C0853AV Dual-Port SRAM Speed (MHz) 133 100 Ordering Code CY7C0853V-133BBI Package Diagram Package Type 51-85146 172-ball BGA (15 × 15 × 1.6 mm) with 1 mm pitch CY7C0853V-133BBXI 172-ball BGA (15 × 15 × 1.6 mm) with 1 mm pitch (Pb-free) CY7C0853V-133BBC 172-ball BGA (15 × 15 × 1.6 mm) with 1 mm pitch CY7C0853AV-100BBI 51-85146 172-ball BGA (15 × 15 × 1.6 mm) with 1 mm pitch CY7C0853V-100BBC 172-ball BGA (15 × 15 × 1.6 mm) with 1 mm pitch Operating Range Industrial Commercial Industrial Commercial 128 K × 36 (4 M) 3.3 V Synchronous CY7C0852V/CY7C0852AV Dual-Port SRAM Speed (MHz) 167 133 Ordering Code Package Diagram Package Type CY7C0852V-167BBC 51-85114 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch CY7C0852AV-167AXC 51-85132 176-pin TQFP (24 × 24 × 1.4 mm) (Pb-free) CY7C0852AV-133AXC 51-85132 176-pin TQFP (24 × 24 × 1.4 mm) (Pb-free) CY7C0852AV-133BBI 51-85114 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch CY7C0852AV-133AXI 51-85132 176-pin TQFP (24 × 24 × 1.4 mm) (Pb-free) CY7C0852V-133BBC 51-85114 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch CY7C0852V-133BBI 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch Operating Range Commercial Industrial Commercial Industrial 64 K × 36 (2 M) 3.3 V Synchronous CY7C0851V/CY7C0851AV Dual-Port SRAM Speed (MHz) 167 Ordering Code CY7C0851V-167BBC CY7C0851AV-167BBXC 133 CY7C0851AV-133BBI Document Number: 38-06070 Rev. *O Package Diagram Package Type 51-85114 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch Operating Range Commercial 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch (Pb-free) 51-85114 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch Industrial Page 30 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Ordering Code Definitions CY 7 C 0 8 5 X X - XXX XX X X Temperature Range: X = I or C I = Industrial; C = Commercial X = Pb-free (RoHS Compliant) Package Type: X = BB or A BB = 172-ball BGA A = 176-pin TQFP Speed Grade: XXX = 100 MHz or 133 MHz or 167 MHz X = V or AV V or AV = 3.3 V Depth: X = 1 or 2 or 3 1 = 64 K 2 = 128 K 3 = 256 K Width: 5 = × 36 Family Code: 8 = Synchronous Port: 0 = Dual Port Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-06070 Rev. *O Page 31 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Package Diagrams Figure 24. 172-ball FBGA (15 × 15 × 1.6 mm) BB172SD (For Single or Stacked Die) Package Outline, 51-85146 51-85146 *E Document Number: 38-06070 Rev. *O Page 32 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Package Diagrams (continued) Figure 25. 172-ball FBGA (15 × 15 × 1.25 mm) BB172 Package Outline, 51-85114 51-85114 *E Document Number: 38-06070 Rev. *O Page 33 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Package Diagrams (continued) Figure 26. 176-pin TQFP (24 × 24 × 1.4 mm) A176S Package Outline, 51-85132 51-85132 *C Document Number: 38-06070 Rev. *O Page 34 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Acronyms Acronym Document Conventions Description CMOS Complementary Metal Oxide Semiconductor FBGA Fine-Pitch Ball Grid Array I/O Input/Output JTAG Joint Test Action Group SRAM Static Random Access Memory TCK Test Clock Input TDI Test Data Input TDO Test Data Output TQFP Thin Quad Flat Pack Document Number: 38-06070 Rev. *O Units of Measure Symbol Unit of Measure °C degree Celsius MHz megahertz µA microampere mA milliampere mV millivolt ns nanosecond ohm pF picofarad V volt W watt Page 35 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Document History Page Document Title: CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV/CY7C0853V/CY7C0853AV, FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM Document Number: 38-06070 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 127809 08/04/03 SPN This data sheet has been extracted from another data sheet: The 2 M / 4 M / 9 M data sheet. The following changes have been made from the original as pertains to this device: Updated capacitance values Updated “Read-to-Write-to-Read (OE Controlled)” waveform Revised static discharge voltage Corrected 0853 pins L3 and L12 Added discussion of Pause/Restart for JTAG boundary scan Power up requirements added to Maximum Ratings information Revised tCD2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns Updated ICC numbers Updated tHA, tHB, tHD for -100 speed Separated out from the 4 M data sheet Added 133 MHz Industrial device to Ordering Information table *A 210948 See ECN YDT Changed mailbox addresses from 1FFFE and 1FFFF to 3FFFE and 3FFFF. *B 216190 See ECN YDT / DCON *C 231996 See ECN YDT Updated Functional Description (Removed “A particular port can write to a certain location while another port is reading that location.”). *D 238938 See ECN WWZ Merged 0853 (9 M × 36) with 0852 (4 M × 36) and 0851 (2 M × 36), add 0850 (1 M × 36), to the data sheet. Added Product Selection Guide. Added JTAG ID code for 1 M device. Updated Scan Registers Sizes (Added Note 22 and referred the same note in the Bit Size ‘n’ of Bondary Scan). Updated boundary scan section. Updated function description for the merge and addition. *E 329122 See ECN SPN Updated Ordering Information (Updated part numbers). *F 389877 See ECN KGH Updated Read-to-Write-to-Read timing diagram to reflect accurate bus turnaround scheme. Added ISB5 Changed tRSCNTINT to 10 ns Changed tRSF to 10 ns Added figure Disabled-to-Read-to-Read-to-Read-to-Write Added figure Disabled-to-Write-to-Read-to-Write-to-Read Added figure Disabled-to-Read-to-Disabled-to-Write Added figure Read-to-Readback-to-Read-to-Read (R/W = HIGH) Updated Read-to-Write-to-Read timing diagram to correct the data out schemes Updated Disabled-to-Read-to-Read-to-Read-to-Write timing diagram to correct the chip enable, data in, and data out schemes Updated Disabled-to-Write-to-Read-to-Write-to-Read timing diagram to correct the chip enable and output enable schemes Updated Disabled-to-Read-to-Disabled-to-Write timing diagram to correct the chip enable and output enable schemes *G 391597 See ECN SPN Updated counter reset section to reflect mirror register behavior *H 2544945 07/29/08 VKN / AESA Document Number: 38-06070 Rev. *O Corrected Revision of Document. CMS does not reflect this rev change. Updated Ordering Information (Updated part numbers). Updated to new template. Page 36 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Document History Page (continued) Document Title: CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV/CY7C0853V/CY7C0853AV, FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM Document Number: 38-06070 Rev. ECN No. Submission Date Orig. of Change *I 2897087 03/22/10 RAME Updated Ordering Information (Removed obsolete parts from ordering information table). Updated Package Diagrams. *J 3093275 11/23/2010 ADMU Added CY7C0851V/CY7C0852V/CY7C0853V parts related information in all instances across the document. Added Contents. Updated Ordering Information (Added new part CY7C0851AV-133BBI in the ordering information table) and added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated to new template. *K 3402163 10/12/2011 ADMU Updated Ordering Information (Removed pruned MPNs CY7C0853AV-100BBC, CY7C0853AV-133BBC). Updated Package Diagrams. *L 3698945 08/07/2012 SMCH Updated title to read as “CY7C0851V/CY7C0851AV/CY7C0852V/ CY7C0852AV/CY7C0853V/CY7C0853AV, FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM”. Updated Features (Removed CY7C0850AV related information). Updated Functional Description (Removed CY7C0850AV related information). Updated Product Selection Guide (Removed CY7C0850AV related information). Updated Pin Configurations (Removed CY7C0850AV related information). Updated Pin Definitions (Removed CY7C0850AV related information). Updated Mailbox Interrupts (Removed CY7C0850AV related information). Updated Address Counter and Mask Register Operations (Removed CY7C0850AV related information). Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed CY7C0850AV related information). Updated Identification Register Definitions (Removed CY7C0850AV related information). Updated Electrical Characteristics (Removed CY7C0850AV related information). Updated Capacitance (Removed CY7C0850AV related information). Updated Switching Characteristics (Removed CY7C0850AV related information). Updated Package Diagrams (Added another spec 51-85146 for 172-ball BGA package, spec 51-85132 for 176-pin TQFP package (Changed revision from *A to *B)). *M 3829988 12/04/2012 SMCH Updated Logic Block Diagram (for better clarity). Updated Functional Overview: Updated Mailbox Interrupts: Updated Note 9 referred in Table 1. Updated Address Counter and Mask Register Operations: Updated Figure 4. Updated Switching Waveforms: Updated Note 32 referred in Figure 9. Updated Package Diagrams: spec 51-85114 – Changed revision from *D to *E. *N 4581625 11/27/2014 SMCH Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Ordering Information: Removed the prune MPN CY7C0851AV-133AXI. Document Number: 38-06070 Rev. *O Description of Change Page 37 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Document History Page (continued) Document Title: CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV/CY7C0853V/CY7C0853AV, FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM Document Number: 38-06070 Rev. ECN No. Submission Date Orig. of Change *O 5018928 11/18/2015 NILE Document Number: 38-06070 Rev. *O Description of Change Updated Package Diagrams: spec 51-85146 – Changed revision from *D to *E. spec 51-85132 – Changed revision from *B to *C. Updated to new template. Completing Sunset Review. Page 38 of 39 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06070 Rev. *O Revised November 18, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 39 of 39