Cypress Semiconductor Technology Verification Qualification Report QTP# 014401 VERSION 2.1 April 2008 UMC 0.35um Technology, UMC fab, Taiwan and USB Application Chip Containing 16 bit RISC Processor SLMSX11C / SLMSX21C SLMSX31C / SLMSX41C SL1148C / SLMSX51C SL11R / SL11R-IDE SL811S / SL811ST SL811HS / SL811HST USB Controller SLAVE Controller Host Slave Controller CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Fred Whitwer Principal Reliability Engineer (408) 943-2722 Mira Ben-Tzur Reliability Engineering Director (408) 943-2675 Cypress Semiconductor USB Application w/16 bit RISC Processor, UMD 0.35um Tech, UMC fab Device SLMSX11C*, 014401 V. 2.1 Page 2 of 7 April 2008 PRODUCT QUALIFICATION HISTORY Qual Report 014401 Description of Qualification Purpose Technology verification UMC 0.35um / Product verification SLMSX11C Date Comp Dec 01 Cypress Semiconductor USB Application w/16 bit RISC Processor, UMD 0.35um Tech, UMC fab Device SLMSX11C*, 014401 V. 2.1 Page 3 of 7 April 2008 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: Qualify Technology verification UMC 0.35um, Fab UMC, Taiwan and product SLMSX11C and it metal and bond option. Marketing Part #: SLMSX*C, SL1148C, SL811*, SL11* Device Description: 3.3V , Commercial available in 28-pin PLCC, 48/100-pin LQFP package. Cypress Division: Cypress Semiconductor Corporation –Interface Product Division (IPD) Overall Die (or Mask) REV Level (pre-requisite for qualification): What ID markings on Die: Rev. B FS80A322 TECHNOLOGY/FAB PROCESS DESCRIPTION Number of Metal Layers: 4 Metal Composition: Metal 1 - 4: Al / Cu Passivation Type and Materials: PSG +SiN Free Phosphorus contents in top glass layer(%): IMD3 Number of Transistors in Device 207,732 Number of Gates in Device 55,435 Generic Process Technology/Design Rule (µ-drawn): Single Poly Four Layer Metal /0.35 µm Gate Oxide Material/Thickness (MOS): SiO2, 100Å / 65Å dual Gate Name/Location of Die Fab (prime) Facility: IMC, Hsin-Chu Taiwan Die Fab Line ID/Wafer Process ID: UMC fab / L8D47 PACKAGE AVAILABILITY PACKAGE ASSEMBLY SITE FACILITY 28-pin PLCC SPIL 48 / 100pin LQFP SPIL Note: Package Qualification details upon request Cypress Semiconductor USB Application w/16 bit RISC Processor, UMD 0.35um Tech, UMC fab Device SLMSX11C*, MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: Mold Compound Flammability Rating: A48 48-pin LQFP Sumitomo 7320CR V-O per UL94 Oxygen Rating Index: >28% Lead Frame Material: Copper Lead Finish, Composition / Thickness: Solder Ball, 85%Sn, 15%Pb Die Backside Preparation Method/Metallization: N/A Die Separation Method: Wafer Saw Die Attach Supplier: N/A Die Attach Material: Silver Epoxy 8355F Die Attach Method: Epoxy Bond Diagram Designation: 10-04500 Wire Bond Method: Thermosonic Wire Material/Size: Au, 1.1.um Thermal Resistance Theta JA °C/W: 56°C/W Package Cross Section Yes/No: N/A Assembly Process Flow: SPIL Spec No. FC-2800 Name/Location of Assembly (prime) facility: SPIL, Taichung Taiwan ELECTRICAL TEST / FINISH DESCRIPTION Test Location: KYEC Fault Coverage: 100% 014401 V. 2.1 Page 4 of 7 April 2008 Cypress Semiconductor USB Application w/16 bit RISC Processor, UMD 0.35um Tech, UMC fab Device SLMSX11C*, 014401 V. 2.1 Page 5 of 7 April 2008 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT Stress/Test High Temperature Operating Life Test Condition (Temp/Bias) Dynamic Operating Condition, Vcc Max = 3.8V, 150°C Result P/F P Early Failure Rate Electrostatic Discharge Human Body Model (ESD-HBM) 2,200V Electrostatic Discharge Charge Device Model (ESD-CDM) 500V Static Latchup 125C, 10V, ± 300mA MIL-STD-883, Method 3015.7 P P Cypress Spec. 25-00020 In accordance with JEDEC 17. Cypress Spec. 01-00081 P Cypress Semiconductor USB Application w/16 bit RISC Processor, UMD 0.35um Tech, UMC fab Device SLMSX11C*, 014401 V. 2.1 Page 6 of 7 April 2008 RELIABILITY FAILURE RATE SUMMARY Stress/Test High Temperature Operating Life Early Failure Rate1 Device Tested/ Device Hours # Fails Activation Energy Thermal AF4 Failure Rate 1,000 0 N/A N/A 0 PPM 1 Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C. Chi-squared 60% estimations used to calculate the failure rate.. 3 Thermal Acceleration Factor is calculated from the Arrhenius equation 2 ⎡E ⎡ 1 1 ⎤ ⎤ AF = exp ⎢ A ⎢ - ⎥ ⎥ ⎣ k ⎣ T 2 T1 ⎦ ⎦ where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. Cypress Semiconductor USB Application w/16 bit RISC Processor, UMD 0.35um Tech, UMC fab Device SLMSX11C*, 014401 V. 2.1 Page 7 of 7 April 2008 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 014401 Ass Loc Duration Samp Rej Failure Mechanism STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE (150C, 3.8V, Vcc Max) SLMSX11C-AC (7C679322B) 1000 0 COMP 9 0 COMP 9 0 COMP 3 0 M5K15-000 48 M5K15-000 STRESS: ESD-CHARGE DEVICE MODEL, 500V SLMSX11C-AC (7C679322B) STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015 (2,200V) SLMSX11C-AC (7C679322B) M5K15-000 STRESS: STATIC LATCH-UP TESTING, 125C, 10V, +/300mA SLMSX11C-AC (7C679322B) M5K15-000