Cypress Semiconductor Product Qualification Report QTP# 045102 VERSION 1.0 November 2005 MoBL Dual Port RAM Family R52LD3 Technology, Fab4 CYDC256A16 CYDC128A16 CYDC064A16 CYDC128A08 CYDC064A08 CYDM256A16 CYDM128A16 CYDM064A16 CYDM128A08 CYDM064A08 1.8V 4K/8K/16K x 16 and 8K/16K x 8 Consumer Dual–Port Static RAM 1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL® Dual–Port Static RAM CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Miguel Maldonado Principal Reliability Engineer (408) 943-4874 Sabbas Daniel Quality Engineering Director (408) 943-2685 Cypress Semiconductor MoBL Dual–Port RAM Device Family Assembly: ASE TAIWAN (TAIWN-G) QTP # 045102 V 1.0 Page 2 of 10 November 2005 PRODUCT QUALIFICATION HISTORY QUAL REPORT DESCRIPTION OF QUALIFICATION PURPOSE DATE COMP. 99075 New Technology R52LD-3 / New Slow Low Power MoBL SRAM, CY62137V Apr 99 045102 Qualify 256K Dual Port Device Family, R52LD3 Technology from Fab4 May 05 Cypress Semiconductor MoBL Dual–Port RAM Device Family Assembly: ASE TAIWAN (TAIWN-G) QTP # 045102 V 1.0 Page 3 of 10 November 2005 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: Qualify MoBL Dual Port RAM Device Family using R52LD3 Technology, Fab4 Marketing Part #: CYDC256A16, CYDC128A16, CYDC064A16, CYDC128A08, CYDC064A08, CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 Device Description: 1.8V 256K (16x16) MoBL Dual Port and Density Width Derivatives Cypress Division: Cypress Semiconductor Corporation – DataCom Division (DCD) Overall Die (or Mask) REV: Rev. A What ID markings on Die: 7C02618A TECHNOLOGY/FAB PROCESS DESCRIPTION – R52LD3 Number of Metal Layers: 2 Metal Composition: Metal 1: 500 Å-TiW/6000 Å Al-Cu/500 Å TiW Metal 2: 300 Å-Ti/8000 Å Al-Cu/300 Å TiW Passivation Type and Materials: 1,000A TEOS + 9,000A SiN Free Phosphorus contents in top glass layer (%): 0% Die Coating(s), if used: N/A Number of Transistors in Device: 294,920 Number of Gates in Device: 735,205 Generic Process Technology/Design Rule ( -drawn): R52 TDR (01-30065), 0.25um Technology Gate Oxide Material/Thickness (MOS): 55Å Name/Location of Die Fab (prime) Facility: Cypress Semiconductor – Bloomington Minnesota Die Fab Line ID/Wafer Process ID: 7C02618AC PACKAGE AVAILABILITY PACKAGE ASSEMBLY FACILITY SITE 100-Ball PBGA ASE Taiwan (TAIWN-G) 100-Lead TQFP CML-R Note: Package Qualification details upon request. Cypress Semiconductor MoBL Dual–Port RAM Device Family Assembly: ASE TAIWAN (TAIWN-G) QTP # 045102 V 1.0 Page 4 of 10 November 2005 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: Mold Compound Flammability Rating: BZ100 100-Ball, Plastic Ball Grid Array (FBGA) KE2270 V-O per UL94 Oxygen Rating Index: N/A Substrate Material: BT Lead Finish, Composition / Thickness: SnAgCu Die Backside Preparation Method/Metallization: Backgrind Die Separation Method: 100% Die Attach Supplier: Ablestik Die Attach Material: 2025D Die Attach Method: Epoxy Bond Diagram Designation: 10-06836 Wire Bond Method: Thermosonic Wire Material/Size: Au, 1.0mil Thermal Resistance Theta JA °C/W: 44.21°C/W Package Cross Section Yes/No: N/A Assembly Process Flow: 49-00011 Name/Location of Assembly (prime) facility: ASE Taiwan (TAIWN-G) ELECTRICAL TEST / FINISH DESCRIPTION Test Location: CML-R Fault Coverage: 100% Note: Please contact a Cypress Representative for other packages availability. Cypress Semiconductor MoBL Dual–Port RAM Device Family Assembly: ASE TAIWAN (TAIWN-G) QTP # 045102 V 1.0 Page 5 of 10 November 2005 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: Mold Compound Flammability Rating: AZ100 100-Lead Thin Qual Flat Pack (TQFP) Lead Free CEL9200CY(R)-V V-O per UL94 Oxygen Rating Index: N/A Substrate Material: Cooper Lead Finish, Composition / Thickness: NiPdAu Die Backside Preparation Method/Metallization: Backgrind Die Separation Method: 100% Die Attach Supplier: Dexter Die Attach Material: QMI 509 Die Attach Method: Epoxy Bond Diagram Designation: 10-06835 Wire Bond Method: Thermosonic Wire Material/Size: Au, 0.8mil Thermal Resistance Theta JA °C/W: 50°C/W Package Cross Section Yes/No: N/A Assembly Process Flow: 11-20046 Name/Location of Assembly (prime) facility: ASE Taiwan (TAIWN-G) ELECTRICAL TEST / FINISH DESCRIPTION Test Location: CML-R Fault Coverage: 100% Note: Please contact a Cypress Representative for other packages availability. Cypress Semiconductor MoBL Dual–Port RAM Device Family Assembly: ASE TAIWAN (TAIWN-G) QTP # 045102 V 1.0 Page 6 of 10 November 2005 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENTS Stress/Test Test Condition (Temp/Bias) Result P/F High Temperature Operating Life Dynamic Operating Condition, Vcc Max = 3.45V, 150°C Early Failure Rate Dynamic Operating Condition, Vcc Max = 3.8V, 150°C High Temperature Operating Life Dynamic Operating Condition, Vcc Max = 3.45V, 150°C Latent Failure Rate Long Life Verification Dynamic Operating Condition, Vcc Max = 3.8V, 150°C Dynamic Operating Condition, Vcc Max = 3.8V, 150°C P High Temperature Steady State Life Static Operating Condition, Vcc Max = 3.63V, 150°C P Low Temperature Operating Life -30C, 3.8V, 8 MHz P Temperature Cycle MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C Precondition: JESD22 Moisture Sensitivity MSL 3 P P P 192 Hrs, 30°C/60%RH+3IR-Reflow, 220°C+0, -5°C 192 Hrs, 30°C/60%RH+3IR-Reflow, 260°C+0, -5°C Pressure Cooker 121°C, 100%RH Precondition: JESD22 Moisture Sensitivity MSL 3 P 192 Hrs, 30°C/60%RH+3IR-Reflow, 220°C+0, -5°C 192 Hrs, 30°C/60%RH+3IR-Reflow, 260°C+0, -5°C High Accelerated Saturation Test (HAST) 140°C, 3.63V, 85%RH Precondition: JESD22 Moisture Sensitivity MSL 3 P 192 Hrs, 30°C/60%RH+3IR-Reflow, 220°C+0, -5°C High Temperature Storage 165C, no bias P Electrostatic Discharge Charge Device Model (ESD-CDM) 500V Cypress Spec. 25-00020 P Electrostatic Discharge Human Body Model (ESD-HBM) 2,200V JESD22, Method A114-B Electrostatic Discharge Human Body Model (ESD-HBM) 2,200V MIL-STD-883, Method 3015 P Static Latch-up 125C, 6.5V/11.5V, ± 300mA P In accordance with JEDEC 17. Cypress Spec. 01-00081 P Cypress Semiconductor MoBL Dual–Port RAM Device Family Assembly: ASE TAIWAN (TAIWN-G) QTP # 045102 V 1.0 Page 7 of 10 November 2005 RELIABILITY FAILURE RATE SUMMARY Stress/Test High Temperature Operating Life Early Failure Rate High Temperature Operating Life1,2 Long Term Failure Rate . Device Tested/ Device Hours # Fails Activation Energy Acceleration Factor3 Failure Rate 1,165 Devices 0 N/A N/A 0 PPM 460,500 HRs 1 0.7 170 13 FITs 1 Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C. Chi-squared 60% estimations used to calculate the failure rate. 3 Thermal Acceleration Factor is calculated from the Arrhenius equation 2 E 1 1 AF = exp A - k T 2 T1 where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. Cypress Semiconductor MoBL Dual–Port RAM Device Family Assembly: ASE TAIWAN (TAIWN-G) QTP # 045102 V 1.0 Page 8 of 10 November 2005 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 99075 Assy Loc Duration Samp Rej Failure Mechanism STRESS: ESD-CHARGE DEVICE MODEL, 500V CY62137V-ZSIB 4852210 619903364 CSPI-R COMP 3 0 CY62137V-ZSIB 4851023 619907600 CSPI-R COMP 3 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE (150C, 3.8V, >Vcc Max) CY62137V-ZSIB 4852210 619903364 CSPI-R 48 1505 0 CY62137V-ZSIB 4902501 619905577 CSPI-R 48 1504 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE (150C, 3.8V, >Vcc Max) CY62137V-ZSIB 4852210 619903364 CSPI-R 80 405 0 CY62137V-ZSIB 4852210 619903364 CSPI-R 500 405 1 CY62137V-ZSIB 4902501 619905577 CSPI-R 80 396 0 CY62137V-ZSIB 4902501 619905577 CSPI-R 500 396 0 1000 404 0 STRESS: LONG LIFE VERIFICATION, (150C, 3.8V, >Vcc Max) CY62137V-ZSIB 4852210 619903364 CSPI-R STRESS: HIGH TEMP DYNAMIC STEADY STATE LIFE TEST, (150C, 3.63V, >Vcc Max) CY62137V-ZSIB 4852210 619903364 CSPI-R 80 80 0 CY62137V-ZSIB 4852210 619903364 CSPI-R 168 80 0 45 0 STRESS: LOW TEMPERATURE OPERATING LIFE, (-30C, 3.8V, 8 MHZ) CY62137V-ZSIB 4852210 619903364 CSPI-R 500 STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, 2,200V CY62137V-ZSIB 4852210 619903364 CSPI-R COMP 3 0 CY62137V-ZSIB 4851023 619907600 CSPI-R COMP 3 0 STRESS: HIGH TEMPERATURE STORAGE, 165C, no bias CY62137V-ZSIB 4852210 619903364 CSPI-R 336 47 0 CY62137V-ZSIB 4852210 619903364 CSPI-R 1000 47 0 CY62137V-ZSIB 4902501 619905577 CSPI-R 336 48 0 STRESS: TC CONDITION C, -65C TO 150C, PRE COND 192 HRS 30C/60% RH, MSL3 CY62137V-ZSIB 4852210 619903364 CSPI-R 300 48 0 CY62137V-ZSIB 4852210 619903364 CSPI-R 1000 48 0 CY62137V-ZSIB 4902501 619905577 CSPI-R 300 48 0 CY62137V-ZSIB 4902501 619905577 CSPI-R 1000 48 0 UNKNOWN Cypress Semiconductor MoBL Dual–Port RAM Device Family Assembly: ASE TAIWAN (TAIWN-G) QTP # 045102 V 1.0 Page 9 of 10 November 2005 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 99075 Assy Loc Duration Samp Rej Failure Mechanism STRESS: PRESSURE COOKER TEST (121C, 100%RH), PRE COND 192HRS 30C/60%RH, MSL3 CY62137V-ZSIB 4852210 619903364 CSPI-R 168 48 0 STRESS: HI-ACCEL SATURATION TEST, (140C, 3.63V), 85%RH, PRE COND 192 HR 30C/60%RH, MSL3 CY62137V-ZSIB 4852210 619903364 CSPI-R 128 48 0 CY62137V-ZSIB 4852210 619903364 CSPI-R 256 48 0 CY62137V-ZSIB 4902501 619905577 CSPI-R 128 48 0 CY62137V-ZSIB 4902501 619905577 CSPI-R 256 48 0 CY62137V-ZSIB 4903568 619907944 CSPI-R 128 48 0 Cypress Semiconductor MoBL Dual–Port RAM Device Family Assembly: ASE TAIWAN (TAIWN-G) QTP # 045102 V 1.0 Page 10 of 10 November 2005 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 045102 Assy Loc Duration Samp Rej STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 3.45V, Vcc Max CYDC256A16 (7C02618A) 4503160 610513409 TAIWN-G 48 1165 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 3.45V, Vcc Max CYDC256A16 (7C02618A) 4503160 610513409 TAIWN-G 80 120 0 CYDC256A16 (7C02618A) 4503160 610513409 TAIWN-G 500 120 0 STRESS: ESD-CHARGE DEVICE MODEL, 500V CYDC256A16 (7C02618A) 4503160 610513409 TAIWN-G COMP 9 0 CYDM256A16 (7C02618A) 4503160 610510254 TAIWN-G COMP 9 0 9 0 COMP 3 0 COMP 3 0 STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, 2,200V CYDM256A16 (7C02618A) 4503160 610510254 TAIWN-G COMP STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V CYDM256A16 (7C02618A) 4503160 610510254 TAIWN-G STRESS: STATIC LATCH-UP TESTING (125C, 6.5V, +/-300mA) CYDM256A16 (7C02618A) 4503160 610510254 TAIWN-G STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRE COND 192 HR 30C/60%RH, MSL3 CYDM256A16 (7C02618A) 4503160 610510254 TAIWN-G 168 50 0 CYDM256A16 (7C02618A) 4503160 610510254 TAIWN-G 288 48 0 STRESS: TC COND. C -65C TO 150C, PRE COND 192 HRS 30C/60%RH, MSL3 CYDM256A16 (7C02618A) 4503160 610510254 TAIWN-G 300 50 0 CYDM256A16 (7C02618A) 4503160 610510254 TAIWN-G 500 50 0 CYDM256A16 (7C02618A) 4503160 610510254 TAIWN-G 1000 50 0 Failure Mechanism