The following document contains information on Cypress products. MB9B120J Series 32-bit Microcontroller FM3 Family Fact Sheet MB9B120J Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low power consumption mode and competitive cost. MB9B120J Series are based on the ARM Cortex-M3 Processor with Flash memory and SRAM, and has peripheral functions such as various timers, ADCs and Communication Interfaces. 1. − − − − − − − − − − − − − − − FEATURES 2. 32bit ARM Cortex-M3 Core Processor version：r2p1 Clock Maximum clock frequency：72MHz Base Timer：8 channels (Max.) Multi-function Timer：1 unit (Max.) 16-bit free-run timer ×3channels/unit Input capture ×4channels/unit Output compare ×6channels/unit A/D activation compare ×1channel/unit Waveform generator ×3channels/unit 16-bit PPG timer ×3channels/unit QPRC：1 channel Dual Timer：1 unit Watch dog Timer：1 channel (SW) + 1 channel (HW) Multi-function Serial Interface：4 channels (Max.) 2 Selectable from UART/CSIO/LIN/I C DMA Controller：4 channels Real-Time Clock：1 unit External Interrupt Controller Unit Up to 7 external interrupt input pins Include one non-maskable interrupt (NMI) 12-bit A/D Converter Max. 8 channels (1 unit) Low Power Consumption Mode 4 low power consumption modes supported SLEEP mode/TIMER mode/RTC mode/STOP mode General Purpose I/O port：23 (Max.) Unique ID Built-in CR Debug Serial Wire Debug Port (SW-DP) Low Voltage Detector：2 channels Clock Super Visor Power Supply：2.7 to 5.5V PRODUCT LINEUP Part number Parameter 3. MB9BF121J Flash (Byte) 64K RAM (Byte) 8K ORDERING INFORMATION Package Part number MB9BF121JPMC MB9BF121JWQN 4. Plastic・LQFP(0.8mm pitch),32-pin (FPT-32P-M30) Plastic・QFN(0.5mm pitch),32-pin (LCC-32P-M73) PACKAGE EXAMPLE OF REFERENCE Plastic ・ LQFP、32-pins (FPT-32P-M30) Publication Number MB9B120J_NP706-00036 ® Revision 1.0 Issue Date February 12, 2014 ® Copyright © 2013-2014 Spansion Inc. All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit® EclipseTM, ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. F a c t S h e e t 5. BLOCK DIAGRAM MB9BF121J SWCLK, SWDIO SWO SRAM0 4 Kbyte SW-DP ROM Table Multi-layer AHB (Max 72MHz) Cortex-M3 Core I @72MHz(Max) D NVIC Sys AHB-APB Bridge: APB0(Max 40MHz) Dual-Timer WatchDog Timer (Software) INITX Clock Reset Generator WatchDog Timer (Hardware) SRAM1 4 Kbyte Flash I/F On-Chip Flash 64 Kbyte Security DMAC 4ch. CSV CLK X0A X1A Main Osc Sub Osc PLL CR 4MHz Source Clock AHB-AHB Bridge X0 X1 CR 100kHz CROUT TIOAx TIOBx AINx BINx ZINx Base Timer 16-bit 8ch./ 32-bit 4ch. QPRC 1ch. A/D Activation Compare 1ch. IC0x FRCKx 16-bit Input Capture 4ch. 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. DTTI0X RTO0x Power On Reset Unit 0 AHB-APB Bridge : APB2 (Max 40MHz) ANxx 12-bit A/D Converter AHB-APB Bridge : APB1 (Max 40MHz) AVRH, AVRL Waveform Generator 3ch. 16-bit PPG 3ch. Multi-function Timer LVD Ctrl LVD IRQ-Monitor Regulator C RTCCO, SUBOUT Real-Time Clock External Interrupt Controller 7-pin + NMI INTx NMIX MODE-Ctrl MD0, MD1 GPIO P0x, P1x, . . . Pxx PIN-Function-Ctrl Multi-function Serial I/F 4ch. (with FIFO ch.0/ch.1) SCKx SINx SOTx ARM and Cortex are the trademarks of ARM Limited in the EU and other countries. 2 MB9B120J_NP706-00036-1v0-E, February 12, 2014