Cypress Semiconductor Product Qualification Report QTP# 020905 VERSION 3.0 July 2006 R52FFD-3 Technology, Fab 4 CY7C68000 CY7C68000A TX2™ USB 2.0 UTMI Transceiver MoBL-USB TX2™ USB 2.0 UTMI Transceiver CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Sabbas Daniel VP Quality Engineering (408) 943-2685 Fredrick Whitwer Principal Reliability Engineer (408) 943-2722 Cypress Semiconductor TX2 USB 2.0 UTMI Transceiver, R52FFD-3 Technology, Fab 4 Device: CY7C68000/CY7C68000A QTP# 020905, V. 3.0 July 2006 Page 2 of 11 TECHNOLOGY QUALIFICATION HISTORY Qual Report Description of Qualification Purpose Date Comp 99311 New R52D-3 Technology /New 2Meg,CY7C1329 SRAM device Aug 99 011205 New Technology derivative R52FFD-3, Fab 4 / New 1Meg, GB/s Quad Port Switch CY7C04312BV/ CY7C04314BV June 01 020905 New TX2 USB 2.0 UTMI Transceiver CY7C68000 Oct 02 062105 7C68005AC - TX2+ Four Mask change for Timing Improvement Jun 06 Cypress products are manufactured using qualified processes. The technology qualification for this product is referenced above and must be considered to get a complete and thorough evaluation of the reliability of the product. Cypress Semiconductor TX2 USB 2.0 UTMI Transceiver, R52FFD-3 Technology, Fab 4 Device: CY7C68000/CY7C68000A QTP# 020905, V. 3.0 July 2006 Page 3 of 11 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: Qualify New TX2 USB 2.0 UTMI Transceiver CY7C68000 in R52FFD-3, Fab 4 Marketing Part #: CY7C68000, CY7C68000A Device Description: 3.3V, Commercial, available in 56-Lead SSOP/QFN/VFBGA package Cypress Division: Cypress Semiconductor Corporation – Consumer & Communication Division Overall Die (or Mask) REV: What ID markings on Die: Rev. A 7C68000A TECHNOLOGY/FAB PROCESS DESCRIPTION Number of Metal Layers: 2 Metal Composition: Metal 1: 500Å TiW/6,000Å Al-0.5%Cu/300Å TiW Metal 2: 300Å Ti/8,000Å Al-0.5%Cu/300Å TiW Passivation Type and Materials: 1,000Å Oxide / 9,000 Å Nitride Free Phosphorus contents in top glass layer (%): 0% Die Coating(s), if used: N/A Number of Transistors: 40,000 Number of Gates: 10,000 Generic Process Technology/Design Rule (µ-drawn): CMOS, Double Metal, 0.25 µm Gate Oxide Material/Thickness (MOS): SiO2 55Å Name/Location of Die Fab (prime) Facility: Cypress Semiconductor – Bloomington, MN Die Fab Line ID/Wafer Process ID: Fab4/R52FFD-3 PACKAGE AVAILABILITY PACKAGE ASSEMBLY FACILITY SITE 56-Lead QFN CML-RA, KOREA-L 56-Lead SSOP TAIWAN-T, CML-R, CML-RA 56-Ball VFBGA TAIWAN-G Note: Package Qualification details upon request. Cypress Semiconductor TX2 USB 2.0 UTMI Transceiver, R52FFD-3 Technology, Fab 4 Device: CY7C68000/CY7C68000A QTP# 020905, V. 3.0 July 2006 Page 4 of 11 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: Mold Compound Flammability Rating: O563 56-Lead Shrunk Small Outline Package (SSOP) Sumitomo 6600HR V-O per UL94 Oxygen Rating Index: >28% Lead Frame Material: Silver spot plated Copper Lead Finish, Composition / Thickness: Solder Plated 85% Sn - 15% Pb Die Backside Preparation Method/Metallization: Backgrind Die Separation Method: Wafer Saw Die Attach Method: Silver Epoxy-Snap Cure Die Attach Supplier: Dexter Die Attach Material: QMI 509 Bond Diagram Designation 10-04760 Wire Bond Method: Thermosonic Wire Material/Size: Au, 1.0 mil Thermal Resistance Theta JA °C/W: 66.4°C/W Package Cross Section Yes/No: N/A Assembly Process Flow: 11-20012 Name/Location of Assembly (prime) facility: CML-R ELECTRICAL TEST / FINISH DESCRIPTION Test Location: CML-R Fault Coverage: 100% Note: Please contact a Cypress Representative for other packages availability. Cypress Semiconductor TX2 USB 2.0 UTMI Transceiver, R52FFD-3 Technology, Fab 4 Device: CY7C68000/CY7C68000A QTP# 020905, V. 3.0 July 2006 Page 5 of 11 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENTS Stress/Test Test Condition (Temp/Bias) Result P/F High Temperature Operating Life Dynamic Operating Condition, Vcc = 3.8V, 125°C Early Failure Dynamic Operating Condition, Vcc = 4.5V, 150°C High Temperature Operating Life Dynamic Operating Condition, Vcc = 3.8V, 125°C Latent Failure Rate Dynamic Operating Condition, Vcc = 3.8V, 150°C High Temperature Steady State Life Dynamic Operating Condition, Vcc = 3.63V, 150°C P Temperature Cycle MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C Precondition: JESD22 Moisture Sensitivity MSL 3 192 Hrs, 30°C/60%RH+3IR-Reflow, 220°C+0, -5°C 121°C, 100%RH, 15 Psig Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85°C/85%RH+3IR-Reflow, 220°C+0, -5°C P Pressure Cooker High Accelerated Saturation Test (HAST) 121°C, 100%RH, 15 Psig Precondition: JESD22 Moisture Sensitivity MSL 3 192 Hrs, 30°C/60%RH+3IR-Reflow, 220°C+0, -5°C 130°C/140C, 3.63V, 85%RH Precondition: JESD22 Moisture Sensitivity MSL 3 192 Hrs, 30°C/60%RH+3IR-Reflow, 220°C+0, -5°C P P P P Electrostatic Discharge Human Body Model (ESD-HBM) 2,200V MIL-STD-883, Method 3015 P Electrostatic Discharge Charge Device Model (ESD-CDM) 500V Cypress Spec. 25-00020 P Low Temperature Operating Life -30°C, 4.3V P High Temperature 165°C, no bias P Age Bond Pull MIL-STD0883, Method 2011 P Current Density Cypress Spec. 22-00029 P Acoustic Microscopy Cypress Spec. 25-00104 P SEM X-Section MIL-STD-883C, Method 2018.2 P Static Latch up Sensitivity 125ºC, ± 200mA, ± 300mA In accordance with JEDEC 17. Cypress Spec. 01-00081 P Cypress Semiconductor TX2 USB 2.0 UTMI Transceiver, R52FFD-3 Technology, Fab 4 Device: CY7C68000/CY7C68000A QTP# 020905, V. 3.0 July 2006 Page 6 of 11 RELIABILITY FAILURE RATE SUMMARY Device Tested/ Device Hours # Fails Activation Energy Acceleration Factor4 Failure Rate4 High Temperature Operating Life Early Failure Rate 1,020 Devices 0 N/A N/A 0 PPM High Temperature Operating Life Long Term Failure Rate1,,2 2,058,244 HRs 3 0.7 170 3 FIT Stress/Test . 1 Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C. Chi-squared 60% estimations used to calculate the failure rate. 3 Thermal Acceleration Factor is calculated from the Arrhenius equation 2 E 1 1 AF = exp A - k T 2 T1 where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. 4 LFR FIT Rate was based on QTP #011205 and QTP #99311 Cypress Semiconductor TX2 USB 2.0 UTMI Transceiver, R52FFD-3 Technology, Fab 4 Device: CY7C68000/CY7C68000A QTP# 020905, V. 3.0 July 2006 Page 7 of 11 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 99311 Assy Loc Duration Samp Rej Failure Mechanism STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 4.5V, Vcc Max CY7C1329-AC (7C1329D)) 4905886 619909761 CSPI-R 48 2988 0 CY7C1329-AC (7C1329D)) 4905886 619909761 CSPI-R 48 1205 0 CY7C1329-AC (7C1329D)) 4905886 619909776 CSPI-R 48 871 0 CY7C1329-AC (7C1329D)) 4909345 619911324 CSPI-R 48 1584 1 CY7C1329-AC (7C1329D)) 4909345 619911327 CSPI-R 48 1669 0 PARTICLE DEFECT STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 3.8V, Vcc Max CY7C1329-AC (7C1329D)) 4905886 619909761 CSPI-R 80 1196 0 CY7C1329-AC (7C1329D)) 4905886 619909761 CSPI-R 500 799 0 CY7C1329-AC (7C1329D)) 4909345 619911324 CSPI-R 80 1491 1 UNKNOWN CAUSE CY7C1329-AC (7C1329D)) 4909345 619911324 CSPI-R 500 1199 1 UNKNOWN CAUSE CY7C1329-AC (7C1329D)) 4909345 619911327 CSPI-R 80 1640 0 CY7C1329-AC (7C1329D)) 4909345 619911327 CSPI-R 500 1451 1 STRESS: HIGH TEMP STEADY STATE LIFE TEST, 150C, 3.63V CY7C1329-AC (7C1329D)) 4842121 619815465 CSPI-R 80 80 0 CY7C1329-AC (7C1329D)) 4842121 619815465 CSPI-R 168 80 0 CY7C1329-AC (7C1329D)) 4843204 619815797 CSPI-R 80 80 0 CY7C1329-AC (7C1329D)) 4843204 619815797 CSPI-R 168 80 0 CSPI-R COMP 3 0 CSPI-R COMP 3 0 STRESS: ESD-CHARGE DEVICE MODEL, 750V CY7C1329-AC (7C1329D)) 4901357 619903817 STRESS: ESD-CHARGE DEVICE MODEL, 1000V CY7C1329-AC (7C1329D)) 4853292 619902690 STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V CY7C1329-AC (7C1329D)) 4853292 619902690 CSPI-R COMP 3 0 CY7C1329-AC (7C1329D)) 4901357 619903817 CSPI-R COMP 3 0 STRESS: HIGH TEMPERATURE STORAGE, 165C, no bias CY7C1329-AC (7C1329D)) 4842121 619815465 CSPI-R 336 48 0 CY7C1329-AC (7C1329D)) 4843204 619815797 CSPI-R 336 48 0 UNKNOWN CAUSE Cypress Semiconductor TX2 USB 2.0 UTMI Transceiver, R52FFD-3 Technology, Fab 4 Device: CY7C68000/CY7C68000A QTP# 020905, V. 3.0 July 2006 Page 8 of 11 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # Assy Loc 99311 Duration Samp Rej COMP 3 0 CSPI-R COMP 3 0 STRESS: STATIC LATCH-UP TESTING, 125C, 9.96V, +/200mA CY7C1329-AC (7C1329D)) 4853292 619902690 CSPI-R STRESS: STATIC LATCH-UP TESTING, 125C, 9.98V, +/200mA CY7C1329-AC (7C1329D)) 4901357 619903817 STRESS: STATIC LATCH-UP TESTING, 125C, 10V, +/200mA CY7C1329-AC (7C1329D)) 4853292 619902690 CSPI-R COMP 3 0 CY7C1329-AC (7C1329D)) 4901357 619903817 CSPI-R COMP 3 0 STRESS: HI-ACCEL SATURATION TEST, 140C, 85%RH, 3.63V, PRE COND 192 HR 30C/60%RH, MSL3 CY7C1329-AC (7C1329D)) 4853292 619902690 CSPI-R 128 48 0 CY7C1329-AC (7C1329D)) 4853292 619902690 CSPI-R 256 48 0 CY7C1329-AC (7C1329D)) 4901357 619903817 CSPI-R 128 48 0 STRESS: PRESSURE COOKER TEST, 121C, 100%RH, 15Psig, PRE COND 192 HR 30C/60%RH, MSL3 CY7C1329-AC (7C1329D)) 4853292 619902690 CSPI-R 168 48 0 CY7C1329-AC (7C1329D)) 4901357 619903817 CSPI-R 168 46 0 STRESS: TC COND. C -65C TO 150C, PRECOND 192 HRS 30C/60%RH, MSL3 CY7C1329-AC (7C1329D)) 4842121 619815465 CSPI-R 300 48 0 CY7C1329-AC (7C1329D)) 4842121 619815465 CSPI-R 1000 48 0 CY7C1329-AC (7C1329D)) 4843204 619815797 CSPI-R 300 45 0 CY7C1329-AC (7C1329D)) 4843204 619815797 CSPI-R 1000 45 0 Failure Mechanism Cypress Semiconductor TX2 USB 2.0 UTMI Transceiver, R52FFD-3 Technology, Fab 4 Device: CY7C68000/CY7C68000A QTP# 020905, V. 3.0 July 2006 Page 9 of 11 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 011205 Assy Loc Duration Samp Rej Failure Mechanism STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 3.8V, Vcc Max CY7C0430BV-BGI (7C04301A) 4049157 610108702 TAIWN-G 96 700 0 CY7C0430BV-BGI (7C04301A) 4101120 610110033 TAIWN-G 96 504 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 125C, 3.8V, Vcc Max CY7C0430BV-BGI (7C04301A) 4049157 610108702 TAIWN-G 168 410 0 CY7C0430BV-BGI (7C04301A) 4049157 610108702 TAIWN-G 500 409 0 CY7C0430BV-BGI (7C04301A) 4049157 610108702 TAIWN-G 1000 408 0 CY7C0430BV-BGI (7C04301A) 4101120 610110033 TAIWN-G 168 410 0 CY7C0430BV-BGI (7C04301A) 4101120 610110033 TAIWN-G 500 409 0 CY7C0430BV-BGI (7C04301A) 4101120 610110033 TAIWN-G 1000 407 0 TAIWN-G COMP 9 0 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY7C0430BV-BGI (7C04301A) 4101120 610110033 STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V CY7C0430BV-BGI (7C04301A) 4101120 610110033 TAIWN-G COMP 9 0 TAIWN-G COMP 3 0 TAIWN-G 500 48 0 STRESS: STATIC LATCH-UP TESTING, 125C, 10V, +/300mA CY7C0430BV-BGI (7C04301A) 4101120 610110033 STRESS: LOW TEMPERATURE OPERATING LIFE, -30C, 4.3V CY7C0430BV-BGI (7C04301A) 4025035 610044436 STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 3.63V, PRE COND 192 HR 30C/60%RH, MSL3 CY7C0430BV-BGI (7C04301A) 4044731 610051943 TAIWN-G 128 46 0 CY7C0430BV-BGI (7C04301A) 4045135 610101405 TAIWN-G 128 57 0 STRESS: PRESSURE COOKER TEST, 121C, 100%RH, 15 Psig, PRE COND 192 HR 30C/60%RH, MSL3 CY7C0430BV-BGI (7C04301A) 4044731 610051943 TAIWN-G 168 48 0 CY7C0430BV-BGI (7C04301A) 4045135 610101405 TAIWN-G 168 50 0 CY7C0430BV-BGI (7C04301A) 4044731 610051943 TAIWN-G COMP 15 0 CY7C0430BV-BGI (7C04301A) 4045135 610101405 TAIWN-G COMP 15 0 CY7C0430BV-BGI (7C04301A) 4047508 610103357 TAIWN-G COMP 15 0 STRESS: ACOUSTIC Cypress Semiconductor TX2 USB 2.0 UTMI Transceiver, R52FFD-3 Technology, Fab 4 Device: CY7C68000/CY7C68000A QTP# 020905, V. 3.0 July 2006 Page 10 of 11 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 011205 Assy Loc Duration Samp Rej Failure Mechanism STRESS: TC COND. C -65C TO 150C, PRE COND 192 HRS 30C/60%RH, MSL3 CY7C0430BV-BGI (7C04301A) 4044731 610051943 TAIWN-G 300 48 0 CY7C0430BV-BGI (7C04301A) 4044731 610051943 TAIWN-G CY7C0430BV-BGI (7C04301A) 4044731 610051943 TAIWN-G 500 48 0 1000 47 0 CY7C0430BV-BGI (7C04301A) 4045135 610101405 TAIWN-G 300 50 0 CY7C0430BV-BGI (7C04301A) 4045135 610101405 TAIWN-G 500 50 0 CY7C0430BV-BGI (7C04301A) 4045135 610101405 TAIWN-G 1000 50 0 *STRESS: TC COND. C -65C TO 150C CY7C0430BV-BGI (7C04301A 4049157 610108702 TAIWN-G 300 48 0 CY7C0430BV-BGI (7C04301A) 4049157 610108702 TAIWN-G 500 48 0 CY7C0430BV-BGI (7C04301A) 4049157 610108702 TAIWN-G 1000 47 0 CY7C0430BV-BGI (7C04301A) 4101120 610110033 TAIWN-G 300 48 0 CY7C0430BV-BGI (7C04301A) 4101120 610110033 TAIWN-G 500 48 0 CY7C0430BV-BGI (7C04301A) 4101120 610110033 TAIWN-G 1000 47 0 *Note: No precondition performed. Cypress Semiconductor TX2 USB 2.0 UTMI Transceiver, R52FFD-3 Technology, Fab 4 Device: CY7C68000/CY7C68000A QTP# 020905, V. 3.0 July 2006 Page 11 of 11 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 020905 Assy Loc Duration Samp Rej Failure Mechanism STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 3.8V, Vcc Max CY7C68000-OC (7C68000A) 4221915 610224472/3/4 CML-R 96 1020 0 STRESS: PRESSURE COOKER TEST, 121C, 100%RH,15 Psig, PRE COND 168 HR 85C/85%RH, MSL1 CY7C68000-OC (7C68000A) STRESS: 4221915 610224472/3/4 CML-R 168 50 0 CML-R COMP 9 0 ESD-CHARGE DEVICE MODEL, 500V CY7C68000-OC (7C68000A) 4221915 610224472/3/4 STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V CY7C68000-OC (7C68000A) 4221915 610224472/3/4 CML-R COMP 9 0 CML-R COMP 3 0 STRESS: STATIC LATCH-UP TESTING, 125C, 10V, +/300mA CY7C68000-OC (7C68000A) 4221915 610224472/3/4