PSoC® 3:CY8C32 Automotive Family Datasheet:可编程片上系统 (PSoC®)

PSoC® 3: CY8C32
Automotive Family Datasheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip while being AEC-Q100 compliant. The CY8C32 family offers a modern method
of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans
the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition
channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C32 family is also a high-performance
configurable digital system with some part numbers including interfaces such as USB, and multimaster inter-integrated circuit (I2C).
In addition to communication interfaces, the CY8C32 family has an easy to configure logic array, flexible routing to all I/O pins, and a
high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt
components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C32 family provides
unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes
through simple firmware updates.
Features
Up to four 16-bit configurable timer, counter, and PWM blocks
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
transmitter receiver (UART), and I2C
• Many others available in catalog
 Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
 Analog peripherals (1.71 V  VDDA  5.5 V)
 1.024 V ± 0.1% internal voltage reference across –40 °C to
+85 °C
 Configurable delta-sigma ADC with 8- to 12-bit resolution
• Sample rates up to 192 ksps
• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion
ratio (SINAD), ±1-bit INL/DNL
 One 8-bit, 8-Msps IDACs or 1-Msps VDACs
 Two comparators with 95-ns response time
 CapSense support
 Programming, debug, and trace
 JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
 Eight address and one data breakpoint
 4-KB instruction trace buffer
2
 Bootloader programming supportable through I C, SPI,
UART, USB, and other interfaces
 Precision, programmable clocking
 3- to 62-MHz internal oscillator over full temperature and
voltage range
 4- to 25-MHz crystal oscillator for crystal PPM accuracy
 Internal PLL clock generation up to 50 MHz
 32.768-kHz watch crystal oscillator
 Low-power internal oscillator at 1, 33, and 100 kHz
 Temperature and packaging
 –40 °C to +85 °C degrees automotive temperature
 –40 °C to +125 °C Extended temperature range
 48-pin SSOP, and 100-pin TQFP package options
 AEC-Q100 compliant.


 Single cycle 8051 CPU
DC to 50 MHz operation
Multiply and divide instructions
 Flash program memory, up to 64 KB, 100,000 write cycles,
20 years retention, and multiple security features
 512-byte flash cache
 Up to 8-KB flash error correcting code (ECC) or configuration
storage
 Up to 8 KB SRAM
 Up to 2 KB electrically erasable programmable read-only
memory (EEPROM), 1 M cycles, and 20 years retention
 24-channel direct memory access (DMA) with multilayer
AHB[1] bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
 Low voltage, ultra low-power
 Wide operating voltage range: 1.71 V to 5.5 V
 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz
 Low-power modes including:
• 1-µA sleep mode with real time clock and low-voltage
detect (LVD) interrupt
• 200-nA hibernate mode with RAM retention
 Versatile I/O system
 29 to 72 I/O (62 GPIOs, eight special input/outputs (SIO),
two USBIOs[2])
 Any GPIO to any digital or analog peripheral routability
[2]
 LCD direct drive from any GPIO, up to 46 × 16 segments
®
 CapSense support from any GPIO
 1.2-V to 5.5-V I/O interface voltages, up to four domains
 Maskable, independent IRQ on any pin or port
 Schmitt-trigger transistor-transistor logic (TTL) inputs
 All GPIO configurable as open drain high/low, pull-up/
pull-down, High Z, or strong output
 Configurable GPIO pin state at power-on reset (POR)
 25 mA sink on SIO
 Digital peripherals
 16 to 24 programmable logic device (PLD) based universal
digital blocks (UDB)
 USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral
interface (TID#40770053) using internal oscillator[2]


Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus.
2. This feature on select devices only. See Ordering Information on page 122 for details.
Cypress Semiconductor Corporation
Document Number: 001-58402 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 3, 2014
PSoC® 3: CY8C32
Automotive Family Datasheet
Contents
1. Architectural Overview ..................................................3
2. Pinouts ............................................................................5
3. Pin Descriptions .............................................................9
4. CPU ................................................................................10
4.1 8051 CPU ..............................................................10
4.2 Addressing Modes .................................................10
4.3 Instruction Set .......................................................10
4.4 DMA and PHUB ....................................................15
4.5 Interrupt Controller ................................................17
5. Memory ..........................................................................21
5.1 Static RAM ............................................................21
5.2 Flash Program Memory .........................................21
5.3 Flash Security ........................................................21
5.4 EEPROM ...............................................................21
5.5 Nonvolatile Latches (NVLs) ...................................22
5.6 External Memory Interface ....................................23
5.7 Memory Map .........................................................24
6. System Integration .......................................................26
6.1 Clocking System ....................................................26
6.2 Power System .......................................................29
6.3 Reset .....................................................................31
6.4 I/O System and Routing ........................................33
7. Digital Subsystem ........................................................40
7.1 Example Peripherals .............................................40
7.2 Universal Digital Block ...........................................42
7.3 UDB Array Description ..........................................45
7.4 DSI Routing Interface Description .........................45
7.5 USB .......................................................................47
7.6 Timers, Counters, and PWMs ...............................47
7.7 I2C .........................................................................48
8. Analog Subsystem .......................................................49
8.1 Analog Routing ......................................................50
8.2 Delta-sigma ADC ...................................................52
8.3 Comparators ..........................................................53
8.4 LCD Direct Drive ...................................................54
Document Number: 001-58402 Rev. *G
8.5 CapSense ..............................................................55
8.6 Temp Sensor .........................................................55
8.7 DAC .......................................................................56
9. Programming, Debug Interfaces, Resources .............57
9.1 JTAG Interface ......................................................57
9.2 Serial Wire Debug Interface ..................................59
9.3 Debug Features .....................................................60
9.4 Trace Features ......................................................60
9.5 Single Wire Viewer Interface .................................60
9.6 Programming Features ..........................................60
9.7 Device Security .....................................................60
10. Development Support ................................................61
10.1 Documentation ....................................................61
10.2 Online ..................................................................61
10.3 Tools ....................................................................61
11. Electrical Specifications ............................................62
11.1 Absolute Maximum Ratings .................................62
11.2 Device Level Specifications .................................63
11.3 Power Regulators ................................................69
11.4 Inputs and Outputs ..............................................71
11.5 Analog Peripherals ..............................................82
11.6 Digital Peripherals .............................................102
11.7 Memory .............................................................108
11.8 PSoC System Resources ..................................114
11.9 Clocking .............................................................117
12. Ordering Information ................................................122
12.1 Part Numbering Conventions ............................123
13. Packaging ..................................................................124
14. Acronyms ..................................................................126
15. Reference Documents ..............................................127
16. Document Conventions ...........................................128
16.1 Units of Measure ...............................................128
17. Revision History .......................................................129
18. Sales, Solutions, and Legal Information ................132
Page 2 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
1. Architectural Overview
Introducing the CY8C32 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C32 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of automotive consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Quadrature Decoder
UDB
Sequencer
Usage Example for UDB
IMO
I2C
Universal Digital Block Array (24 x UDB)
8-bit
Timer
UDB
UDB
UDB
16-bit
PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
22 
12-bit SPI
UDB
UDB
UDB
UDB
8-bit
Timer
UDB
8-bit SPI
I 2C Slave
Master/
Slave
16-bit PRS
UDB
Logic
UDB
FS USB
2.0
4x
Timer
Counter
PWM
Logic
UDB
UART
UDB
USB
PHY
GPIOs
GPIOs
Clock Tree
32.768 KHz
(Optional)
Digital System
System Wide
Resources
Xtal
Osc
SIO
4 to 25 MHz
(Optional)
GPIOs
Digital Interconnect
12- bit PWM
RTC
Timer
System Bus
Memory System
EEPROM
SRAM
CPU System
8051
Interrupt
Controller
Program &
Debug
Program
GPIOs
WDT
and
Wake
GPIOs
Debug &
Trace
EMIF
PHUB
DMA
FLASH
ILO
Boundary
Scan
Power Management
System
GPIOs
SIOs
Clocking System
Analog System
LCD Direct
Drive
ADC
POR and
LVD
1.8V LDO
Temperature
Sensor
CapSense
Figure 1-1 illustrates the major components of the CY8C32
family. They are:
 8051 CPU subsystem
 Nonvolatile subsystem
 Programming, debug, and test subsystem
 Inputs and outputs
 Clocking
 Power
 Digital subsystem
 Analog subsystem
Document Number: 001-58402 Rev. *G
1 x DAC
Del Sig
ADC
+
2x
CMP
-
GPIOs
1.71 V to
5.5 V
Sleep
Power
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of prebuilt and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals.
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C32 family these blocks can include four 16-bit timers,
counters, and PWM blocks; I2C slave, master, and multimaster;
and FS USB.
Page 3 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
For more details on the peripherals see the “Example
Peripherals” section on page 40 of this data sheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 40 of this data sheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.1-percent
error over temperature and voltage. The configurable analog
subsystem includes:
 Analog mux
 Comparator
 Voltage reference
 Analog-to-digital converter (ADC)
 Digital-to-analog converter (DAC)
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. The heart of the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features [3]:
 Less than 100 µV offset
 A gain error of 0.2 percent
 INL less than ±2 LSB
 DNL less than ±1 LSB
 SINAD better than 84 dB in 16-bit mode
This converter addresses a wide variety of precision analog
applications, including some of the most demanding sensors.
One high-speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
PWM DAC outputs using the UDB array. This can be used to
create a pulse width modulated (PWM) DAC of up to 10 bits, at
up to 48 kHz. The digital DACs in each UDB support PWM, PRS,
or delta-sigma algorithms with programmable widths. In addition
to the ADC, and DACs, the analog subsystem provides multiple
comparators:
See the “Analog Subsystem” section on page 49 of this data
sheet for more details.
PSoC’s 8051 CPU subsystem is built around a single cycle
pipelined 8051 8-bit processor running at up to 50 MHz. The
CPU subsystem includes a programmable nested vector
interrupt controller, DMA controller, and RAM. PSoC’s nested
vector interrupt controller provides low latency by allowing the
CPU to vector directly to the first address of the interrupt service
routine, bypassing the jump instruction required by other
architectures. The DMA controller enables peripherals to
exchange data without CPU involvement. This allows the CPU
to run slower (saving power) or use those CPU cycles to improve
the performance of firmware algorithms. The single cycle 8051
CPU runs ten times faster than a standard 8051 processor. The
processor speed itself is configurable, allowing you to tune active
power consumption for specific applications.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 64 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling bootloaders. You can enable an error
correcting code (ECC) for high reliability applications. A powerful
and flexible protection model secures the user's sensitive
information, allowing selective memory block locking for read
and write protection. Up to 2 KB of byte-writeable EEPROM is
available on-chip to store application data. Additionally, selected
configuration options such as boot speed and pin drive mode are
stored in nonvolatile memory. This allows settings to activate
immediately after POR.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive[4], CapSense[5], flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow VOH to be set independently of Vddio when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I2C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with Full-Speed USB the USB
physical interface is also provided (USBIO). When not using
USB these pins may also be used for limited digital functionality
and device programming. All of the features of the PSoC I/Os are
covered in detail in the “I/O System and Routing” section on
page 33 of this data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The internal main oscillator (IMO) is the clock base for the
system, and has 1-percent accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 62 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
clock frequencies up to 50 MHz from the IMO, external crystal,
or external reference clock.
Notes
3. Refer Electrical Specifications on page 62 for the detailed ADC specification across entire voltage range and temperature.
4. This feature on select devices only. See Ordering Information on page 122 for details.
5. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-58402 Rev. *G
Page 4 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
It also contains a separate, very low-power internal low-speed
oscillator (ILO) for the sleep and watchdog timers. A 32.768-kHz
external watch crystal is also supported for use in real-time
clock (RTC) applications. The clocks, together with
programmable clock dividers, provide the flexibility to integrate
most timing requirements.
The CY8C32 family supports a wide supply operating range from
1.71 V to 5.5 V. This allows operation from regulated supplies
such as 1.8 V ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%,
or directly from a wide range of battery types.
PSoC supports a wide range of low-power modes. These include
a 200-nA hibernate mode with RAM retention and a 1-µA sleep
mode with RTC. In the second mode, the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz, or 0.8 mA running at 3 MHz.
2. Pinouts
Each VDDIO pin powers a specific set of I/O pins. (The USBIOs
are powered from VDDD.) Using the VDDIO pins, a single PSoC
can support multiple voltage levels, reducing the need for
off-chip level shifters. The black lines drawn on the pinout
diagrams in Figure 2-3 through Figure 2-4 show the pins that are
powered by each VDDIO.
Each VDDIO may source up to 100 mA [6] total to its associated
I/O pins, as shown in Figure 2-1.
Figure 2-1. VDDIO Current Limit
IDDIO X = 100 mA
VDDIO X
I/O Pins
PSoC
The details of the PSoC power modes are covered in the “Power
System” section on page 29 of this data sheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. The 1-wire SWV may also be
used for ‘printf’ style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins.
Using these standard interfaces you can debug or program the
PSoC with a variety of hardware solutions from Cypress or third
party vendors. PSoC supports on-chip break points and 4-KB
instruction and data race memory for debug. Details of the
programming, test, and debugging interfaces are discussed in
the “Programming, Debug Interfaces, Resources” section on
page 57 of this data sheet.
Conversely, for the 100-pin and 68-pin devices, the set of I/O
pins associated with any VDDIO may sink up to 100 mA [6] total,
as shown in Figure 2-2.
Figure 2-2. I/O Pins Current Limit
Ipins = 100 mA
VDDIO X
I/O Pins
PSoC
VSSD
For the 48-pin devices, the set of I/O pins associated with
VDDIO0 plus VDDIO2 may sink up to 100 mA [6] total. The set
of I/O pins associated with VDDIO1 plus VDDIO3 may sink up to
a total of 100 mA.
Note
6. The 100 mA source/ sink current per Vddio is valid only for temperature range of –40 °C to +85 °C. For extended temperature range of –40 °C to +125 °C, the maximum
source or sink current per Vddio is 40 mA.
Document Number: 001-58402 Rev. *G
Page 5 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 2-3. 48-pin SSOP Part Pinout
(SIO) P12[2]
(SIO) P12[3]
(GPIO) P0[0]
(GPIO) P0[1]
(GPIO) P0[2]
(Extref0, GPIO) P0[3]
VDDIO0
(GPIO) P0[4]
(GPIO) P0[5]
(IDAC0, GPIO) P0[6]
(GPIO) P0[7]
VCCD
VSSD
VDDD
(GPIO) P2[3]
(GPIO) P2[4]
VDDIO2
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
VSSD
NC
VSSD
VSSD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
Lines show
46
VDDIO to I/O
45
supply
44
association
43
42
41
40
39
38
37
SSOP
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
VDDIO3
P15[1] (GPIO, MHZ XTAL: XI)
P15[0] (GPIO, MHZ XTAL: XO)
VCCD
VSSD
VDDD
[7]
P15[7] (USBIO, D-, SW DCK)
[7]
P15[6] (USBIO, D+, SW DIO)
P1[7] (GPIO )
P1[6] (GPIO )
VDDIO1
P1[5] (GPIO , nTRST)
P1[4] (GPIO , TDI)
P1[3] (GPIO , TDO, SW V)
P1[2] (GPIO, Configurable XRES)
P1[1] (GPIO , TCK, SW DCK)
P1[0] (GPIO , TMS, SW DIO)
Note
7. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-58402 Rev. *G
Page 6 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
P4[5] (GPIO)
P4[4] (GPIO)
P4[3] (GPIO)
P4[2] (GPIO)
P0[7] (GPIO)
P0[6] (GPIO, IDAC0)
P0[5] (GPIO)
P0[4] (GPIO)
P15[4] (GPIO)
P6[3] (GPIO)
P6[2] (GPIO)
P6[1] (GPIO)
P6[0] (GPIO)
VDDD
VSSD
VCCD
P4[7] (GPIO)
P4[6] (GPIO)
75
74
Lines show VDDIO
to I/O supply
association
TQFP
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
VCCA
NC
NC
NC
NC
NC
NC
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO)
P3[6] (GPIO)
(GPIO) P3[5]
VDDIO3
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDIO0
P0[3] (GPIO, Extref0)
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
[8]
[8]
(USBIO, D-, SWDCK) P15[7]
VDDD
VSSD
VCCD
NC
NC
(MHZ XTAL: XO, GPIO) P15[0]
(MHZ XTAL: XI, GPIO) P15[1]
(GPIO) P3[0]
(GPIO) P3[1]
(Extref1, GPIO) P3[2]
(GPIO) P3[3]
(GPIO) P3[4]
54
53
52
51
26
27
28
29
30
31
32
33
34
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDIO1
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(GPIO) P5[4]
(GPIO) P5[5]
(GPIO) P5[6]
(GPIO) P5[7]
(USBIO, D+, SWDIO) P15[6]
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
(GPIO) P6[4]
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
VSSD
NC
VSSD
VSSD
VSSD
XRES
(GPIO) P5[0]
(GPIO) P5[1]
(GPIO) P5[2]
(GPIO) P5[3]
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(Configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(nTRST, GPIO) P1[5]
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDDIO2
P2[4] (GPIO)
P2[3] (GPIO)
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
P15[5] (GPIO)
Figure 2-4. 100-pin TQFP Part Pinout
Figure 2-5 and Figure 2-6 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog
performance on a two-layer board.
 The two pins labeled VDDD must be connected together.
 The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 and Power System on
page 29. The trace between the two VCCD pins should be as short as possible.
 The two pins labeled Vssd must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
Note
8. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-58402 Rev. *G
Page 7 of 132
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Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections
VDDD
C1
1uF
VDDD
VSSD
VSSD
VDDD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDA
C8
0.1uF
C17
1uF
VSSD
VSSA
VSSD
VDDA
VSSA
VCCA
VDDA
C9
1uF
C10
0.1uF
VSSA
VDDD
C11
0.1uF
VCCD
VSSD
VDDD
C12
0.1uF
VSSD
VDDD
VDDIO0
OA0-, REF0, P0[3]
OA0+, P0[2]
OA0OUT, P0[1]
OA2OUT, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
KHZXIN, P15[3]
KHZXOUT, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3OUT, P3[7]
OA1OUT, P3[6]
VDDIO1
P1[6]
P1[7]
P12[6], SIO
P12[7], SIO
P5[4]
P5[5]
P5[6]
P5[7]
P15[6], USB D+
P15[7], USB DVDDD
VSSD
VCCD
NC
NC
P15[0], MHZXOUT
P15[1], MHZXIN
P3[0], IDAC1
P3[1], IDAC3
P3[2], OA3-, REF1
P3[3], OA3+
P3[4], OA1P3[5], OA1+
VDDIO3
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], NTRST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSSD
VCCD
VSSD
VDDIO2
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P6[3]
P6[2]
P6[1]
P6[0]
VDDD
VSSD
VCCD
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
IDAC2, P0[7]
IDAC0, P0[6]
OA2-, P0[5]
OA2+, P0[4]
VSSD
VSSD
C2
0.1uF
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
C6
0.1uF
VDDD
VDDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDD
C15
1uF
C16
0.1uF
VSSD
VSSD
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-6 on page 9.
Document Number: 001-58402 Rev. *G
Page 8 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
VDDD
VSSA
VSSD
VDDA
VSSA
Plane
VSSD
Plane
3. Pin Descriptions
analog comparator, high sink current, and high impedance state
when the device is unpowered.
IDAC0
SWDCK
Low resistance output pin for high current DACs (IDAC).
Extref0, Extref1
Serial wire debug clock programming and debug port
connection.
External reference input to the analog system.
SWDIO
GPIO
Serial wire debug input and output programming and debug port
connection.
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense.
I2C0: SCL, I2C1: SCL
I2C SCL line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SCL if wake from sleep is not
required.
I2C0: SDA, I2C1: SDA
2C
I SDA line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SDA if wake from sleep is not
required.
kHz XTAL: Xo, kHz XTAL: Xi
32.768-kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi
4- to 25-MHz crystal oscillator pin.
nTRST
Optional JTAG test reset programming and debug port
connection to reset the JTAG connection.
SIO
Special I/O provides interfaces to the CPU, digital peripherals
and interrupts with a programmable high threshold voltage,
Document Number: 001-58402 Rev. *G
SWV
Single wire viewer debug output.
TCK
JTAG test clock programming and debug port connection.
TDI
JTAG test data in programming and debug port connection.
TDO
JTAG test data out programming and debug port connection.
TMS
JTAG test mode select programming and debug port connection.
USBIO, D+
Provides D+ connection directly to a USB 2.0 bus. May be used
as a digital I/O pin; it is powered from VDDD instead of from a
VDDIO. Pins are Do Not Use (DNU) on devices without USB.
USBIO, D–
Provides D– connection directly to a USB 2.0 bus. May be used
as a digital I/O pin; it is powered from VDDD instead of from a
VDDIO. Pins are Do Not Use (DNU) on devices without USB.
Page 9 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
VCCA.
Output of the analog core regulator or the input to the
analog core. Requires a 1uF capacitor to VSSA. The regulator
output is not designed to drive external circuits. Note that if you
use the device with an external core regulator (externally
regulated mode), the voltage applied to this pin must not
exceed the allowable range of 1.71 V to 1.89 V. When using
the internal core regulator, (internally regulated mode, the
default), do not tie any power to this pin. For details see Power
System on page 29.
VCCD.
Output of the digital core regulator or the input to the digital
core. The two VCCD pins must be shorted together, with the
trace between them as short as possible, and a 1uF capacitor to
VSSD. The regulator output is not designed to drive external
circuits. Note that if you use the device with an external core
regulator (externally regulated mode), the voltage applied to
this pin must not exceed the allowable range of 1.71 V to
1.89 V. When using the internal core regulator (internally
regulated mode, the default), do not tie any power to this pin. For
details see Power System on page 29.
VDDA
Supply for all analog peripherals and analog core regulator.
VDDA must be the highest voltage present on the device. All
other supply pins must be less than or equal to VDDA.
VDDD
Supply for all digital peripherals and digital core regulator. VDDD
must be less than or equal to VDDA.
VSSA
Ground for all analog peripherals.
VSSD
Ground for all digital logic and I/O pins.
VDDIO0, VDDIO1, VDDIO2, VDDIO3
Supply for I/O pins. Each VDDIO must be tied to a valid operating
voltage (1.71 V to 5.5 V), and must be less than or equal to
VDDA.
instruction. The single cycle 8051 CPU runs ten times faster than
a standard 8051 processor.
The 8051 CPU subsystem includes these features:
 Single cycle 8051 CPU
 Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up
to 8 KB of SRAM
 512-byte instruction cache between CPU and flash
 Programmable nested vector interrupt controller
 DMA controller
 Peripheral HUB (PHUB)
 External memory interface (EMIF)
4.2 Addressing Modes
The following addressing modes are supported by the 8051:
 Direct Addressing: The operand is specified by a direct 8-bit
address field. Only the internal RAM and the SFRs can be
accessed using this mode.
 Indirect Addressing: The instruction specifies the register which
contains the address of the operand. The registers R0 or R1
are used to specify the 8-bit address, while the data pointer
(DPTR) register is used to specify the 16-bit address.
 Register Addressing: Certain instructions access one of the
registers (R0 to R7) in the specified register bank. These
instructions are more efficient because there is no need for an
address field.
 Register Specific Instructions: Some instructions are specific
to certain registers. For example, some instructions always act
on the accumulator. In this case, there is no need to specify the
operand.
 Immediate Constants: Some instructions carry the value of the
constants directly instead of an address.
 Indexed Addressing: This type of addressing can be used only
for a read of the program memory. This mode uses the Data
Pointer as the base and the accumulator value as an offset to
read a program memory.
XRES (and configurable XRES)
 Bit Addressing: In this mode, the operand is one of 256 bits.
External reset pin. Active low with internal pull-up. Pin P1[2] may
be configured to be a XRES pin; see “Nonvolatile Latches
(NVLs)” on page 22.
4.3 Instruction Set
4. CPU
The 8051 instruction set is highly optimized for 8-bit handling and
Boolean operations. The types of instructions supported include:
 Arithmetic instructions
4.1 8051 CPU
 Logical instructions
The CY8C32 devices use a single cycle 8051 CPU, which is fully
compatible with the original MCS-51 instruction set. The
CY8C32 family uses a pipelined RISC architecture, which
executes most instructions in 1 to 2 cycles to provide peak
performance of up to 33 MIPS with an average of 2 cycles per
 Data transfer instructions
Document Number: 001-58402 Rev. *G
 Boolean instructions
 Program branching instructions
Page 10 of 132
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Automotive Family Datasheet
4.3.1 Instruction Set Summary
4.3.1.1 Arithmetic Instructions
Arithmetic instructions support the direct, indirect, register, immediate constant, and register-specific instructions. Arithmetic modes
are used for addition, subtraction, multiplication, division, increment, and decrement operations. Table 4-1 lists the different arithmetic
instructions.
Table 4-1. Arithmetic Instructions
Mnemonic
Description
Bytes
Cycles
1
1
ADD
A,Rn
Add register to accumulator
ADD
A,Direct
Add direct byte to accumulator
2
2
ADD
A,@Ri
Add indirect RAM to accumulator
1
2
ADD
A,#data
Add immediate data to accumulator
2
2
ADDC A,Rn
Add register to accumulator with carry
1
1
ADDC A,Direct
Add direct byte to accumulator with carry
2
2
ADDC A,@Ri
Add indirect RAM to accumulator with carry
1
2
ADDC A,#data
Add immediate data to accumulator with carry
2
2
SUBB A,Rn
Subtract register from accumulator with borrow
1
1
SUBB A,Direct
Subtract direct byte from accumulator with borrow
2
2
SUBB A,@Ri
Subtract indirect RAM from accumulator with borrow
1
2
SUBB A,#data
Subtract immediate data from accumulator with borrow
2
2
INC
Increment accumulator
1
1
A
INC
Rn
Increment register
1
2
INC
Direct
Increment direct byte
2
3
INC
@Ri
Increment indirect RAM
1
3
DEC
A
Decrement accumulator
1
1
DEC
Rn
Decrement register
1
2
DEC
Direct
Decrement direct byte
2
3
DEC
@Ri
Decrement indirect RAM
1
3
INC
DPTR
Increment data pointer
1
1
MUL
Multiply accumulator and B
1
2
DIV
Divide accumulator by B
1
6
DAA
Decimal adjust accumulator
1
3
Document Number: 001-58402 Rev. *G
Page 11 of 132
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Automotive Family Datasheet
4.3.1.2 Logical Instructions
The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of
nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table 4-2 shows the list of
logical instructions and their description.
Table 4-2. Logical Instructions
Mnemonic
Description
Bytes
Cycles
ANL
A,Rn
AND register to accumulator
1
1
ANL
A,Direct
AND direct byte to accumulator
2
2
ANL
A,@Ri
AND indirect RAM to accumulator
1
2
ANL
A,#data
AND immediate data to accumulator
2
2
ANL
Direct, A
AND accumulator to direct byte
2
3
ANL
Direct, #data
AND immediate data to direct byte
3
3
ORL
A,Rn
OR register to accumulator
1
1
ORL
A,Direct
OR direct byte to accumulator
2
2
ORL
A,@Ri
OR indirect RAM to accumulator
1
2
ORL
A,#data
OR immediate data to accumulator
2
2
ORL
Direct, A
OR accumulator to direct byte
2
3
ORL
Direct, #data
OR immediate data to direct byte
3
3
XRL
A,Rn
XOR register to accumulator
1
1
XRL
A,Direct
XOR direct byte to accumulator
2
2
XRL
A,@Ri
XOR indirect RAM to accumulator
1
2
XRL
A,#data
XOR immediate data to accumulator
2
2
XRL
Direct, A
XOR accumulator to direct byte
2
3
XRL
Direct, #data
XOR immediate data to direct byte
3
3
CLR
A
Clear accumulator
1
1
CPL
A
Complement accumulator
1
1
RL
A
Rotate accumulator left
1
1
RLC
A
Rotate accumulator left through carry
1
1
RR
A
Rotate accumulator right
1
1
RRC A
Rotate accumulator right though carry
1
1
SWAP A
Swap nibbles within accumulator
1
1
4.3.1.3 Data Transfer Instructions
The data transfer instructions are of three types: the core RAM,
xdata RAM, and the lookup tables. The core RAM transfer
includes transfer between any two core RAM locations or SFRs.
These instructions can use direct, indirect, register, and
immediate addressing. The xdata RAM transfer includes only the
transfer between the accumulator and the xdata RAM location.
It can use only indirect addressing. The lookup tables involve
nothing but the read of program memory using the Indexed
Document Number: 001-58402 Rev. *G
addressing mode. Table 4-3 lists the various data transfer
instructions available.
4.3.1.4 Boolean Instructions
The 8051 core has a separate bit-addressable memory location.
It has 128 bits of bit addressable RAM and a set of SFRs that are
bit addressable. The instruction set includes the whole menu of
bit operations such as move, set, clear, toggle, OR, and AND
instructions and the conditional jump instructions. Table 4-4 lists
the available Boolean instructions.
Page 12 of 132
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Automotive Family Datasheet
Table 4-3. Data Transfer Instructions
Mnemonic
Description
Bytes
Cycles
1
1
MOV
A,Rn
Move register to accumulator
MOV
A,Direct
Move direct byte to accumulator
2
2
MOV
A,@Ri
Move indirect RAM to accumulator
1
2
MOV
A,#data
Move immediate data to accumulator
2
2
MOV
Rn,A
Move accumulator to register
1
1
MOV
Rn,Direct
Move direct byte to register
2
3
MOV
Rn, #data
Move immediate data to register
2
2
MOV
Direct, A
Move accumulator to direct byte
2
2
MOV
Direct, Rn
Move register to direct byte
2
2
MOV
Direct, Direct
Move direct byte to direct byte
3
3
MOV
Direct, @Ri
Move indirect RAM to direct byte
2
3
MOV
Direct, #data
Move immediate data to direct byte
3
3
MOV
@Ri, A
Move accumulator to indirect RAM
1
2
MOV
@Ri, Direct
Move direct byte to indirect RAM
2
3
MOV
@Ri, #data
Move immediate data to indirect RAM
2
2
MOV
DPTR, #data16
Load data pointer with 16 bit constant
3
3
Move code byte relative to DPTR to accumulator
1
5
MOVC A, @A + PC
Move code byte relative to PC to accumulator
1
4
MOVX A,@Ri
Move external RAM (8-bit) to accumulator
1
4
MOVX A, @DPTR
Move external RAM (16-bit) to accumulator
1
3
MOVX @Ri, A
Move accumulator to external RAM (8-bit)
1
5
MOVX @DPTR, A
Move accumulator to external RAM (16-bit)
1
4
PUSH Direct
Push direct byte onto stack
2
3
POP
Direct
Pop direct byte from stack
2
2
XCH
A, Rn
Exchange register with accumulator
1
2
XCH
A, Direct
Exchange direct byte with accumulator
2
3
XCH
A, @Ri
Exchange indirect RAM with accumulator
1
3
Exchange low order indirect digit RAM with accumulator
1
3
Bytes
Cycles
MOVC A, @A+DPTR
XCHD A, @Ri
Table 4-4. Boolean Instructions
Mnemonic
Description
CLR
C
Clear carry
1
1
CLR
bit
Clear direct bit
2
3
SETB C
Set carry
1
1
SETB bit
Set direct bit
2
3
CPL
C
Complement carry
1
1
CPL
bit
Complement direct bit
2
3
ANL
C, bit
AND direct bit to carry
2
2
Document Number: 001-58402 Rev. *G
Page 13 of 132
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Automotive Family Datasheet
Table 4-4. Boolean Instructions (continued)
Mnemonic
Bytes
Cycles
AND complement of direct bit to carry
2
2
ORL C, bit
OR direct bit to carry
2
2
ORL C, /bit
OR complement of direct bit to carry
2
2
ANL
C, /bit
Description
MOV C, bit
Move direct bit to carry
2
2
MOV bit, C
Move carry to direct bit
2
3
JC
Jump if carry is set
2
3
Jump if no carry is set
2
3
rel
JNC rel
JB
Jump if direct bit is set
3
5
JNB bit, rel
bit, rel
Jump if direct bit is not set
3
5
JBC bit, rel
Jump if direct bit is set and clear bit
3
5
Document Number: 001-58402 Rev. *G
Page 14 of 132
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Automotive Family Datasheet
4.3.1.5 Program Branching Instructions
The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5
shows the list of jump instructions.
Table 4-5. Jump Instructions
Mnemonic
Description
Bytes
Cycles
ACALL addr11
Absolute subroutine call
2
4
LCALL addr16
Long subroutine call
3
4
RET
Return from subroutine
1
4
RETI
Return from interrupt
1
4
AJMP addr11
Absolute jump
2
3
LJMP addr16
Long jump
3
4
SJMP rel
Short jump (relative address)
2
3
JMP @A + DPTR
Jump indirect relative to DPTR
1
5
JZ rel
Jump if accumulator is zero
2
4
JNZ rel
Jump if accumulator is nonzero
2
4
CJNE A,Direct, rel
Compare direct byte to accumulator and jump if not equal
3
5
CJNE A, #data, rel
Compare immediate data to accumulator and jump if not equal
3
4
CJNE Rn, #data, rel
Compare immediate data to register and jump if not equal
3
4
CJNE @Ri, #data, rel
Compare immediate data to indirect RAM and jump if not equal
3
5
DJNZ Rn,rel
Decrement register and jump if not zero
2
4
DJNZ Direct, rel
Decrement direct byte and jump if not zero
3
5
NOP
No operation
1
1
4.4 DMA and PHUB
4.4.1 PHUB Features
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
 CPU and DMA controller are both bus masters to the PHUB
 A central hub that includes the DMA controller, arbiter, and
 Simultaneous CPU and DMA access to peripherals located on
 Multiple spokes that radiate outward from the hub to most
 Simultaneous DMA source and destination burst transactions
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
 Supports 8-, 16-, 24-, and 32-bit addressing and data
router
peripherals
Document Number: 001-58402 Rev. *G
 Eight multi-layer AHB bus parallel access paths (spokes) for
peripheral access
different spokes
on different spokes
Table 4-6. PHUB Spokes and Peripherals
PHUB Spokes
Peripherals
0
SRAM
1
IOs, PICU, EMIF
2
PHUB local configuration, Power manager,
Clocks, IC, SWV, EEPROM, Flash
programming interface
3
Analog interface and trim, Decimator
4
USB, I2C, Timers, Counters, and PWMs
5
Reserved
6
UDBs group 1
7
UDBs group 2
Page 15 of 132
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4.4.2 DMA Features
 24 DMA channels
 Each channel has one or more transaction descriptors (TD) to
configure channel behavior. Up to 128 total TDs can be defined
 TDs can be dynamically updated
Priority levels 2 to 7 are guaranteed the minimum bus bandwidth
shown in Table 4-7 after the CPU and DMA priority levels 0 and
1 have satisfied their requirements.
Table 4-7. Priority Levels
Priority Level
% Bus Bandwidth
0
100.0
 Eight levels of priority per channel
1
100.0
 Any digitally routable signal, the CPU, or another DMA channel,
2
50.0
3
25.0
 Each channel can generate up to two interrupts per transfer
4
12.5
 Transactions can be stalled or canceled
5
6.2
 Supports transaction size of infinite or 1 to 64 KB
6
3.1
 TDs may be nested and/or chained for complex transactions
7
1.5
can trigger a transaction
4.4.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100 percent of the bus bandwidth. If a tie
occurs on two DMA requests of the same priority level, a simple
round robin method is used to evenly share the allocated
bandwidth. The round robin allocation can be disabled for each
DMA channel, allowing it to always be at the head of the line.
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
4.4.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
4.4.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location). The basic
timing diagrams of DMA read and write cycles are shown in
Figure 4-1. For more description on other transfer modes, refer
to the Technical Reference Manual.
Figure 4-1. DMA Timing Diagram
ADDRESS Phase
DATA Phase
ADDRESS Phase
CLK
ADDR 16/32
DATA Phase
CLK
A
ADDR 16/32
B
WRITE
A
B
WRITE
DATA (A)
DATA
READY
DATA
DATA (A)
READY
Basic DMA Read Transfer without wait states
Document Number: 001-58402 Rev. *G
Basic DMA Write Transfer without wait states
Page 16 of 132
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4.4.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.4.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
phase TD(s) finish, a status phase TD can be invoked that reads
some memory mapped status information from the peripheral
and copies it to a location in system memory specified by the
CPU for later inspection. Multiple sets of configuration, data, and
status phase ‘subchains’ can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.4.4.7 Nested DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the
application. When complete, the second TD calls the first TD,
which again updates the second TD’s configuration. This
process repeats as often as necessary.
4.4.4.5 Scatter Gather DMA
4.5 Interrupt Controller
In the case of scatter gather DMA, there are multiple
noncontiguous sources or destinations that are required to
effectively carry out an overall DMA transaction. For example, a
packet may need to be transmitted off of the device and the
packet elements, including the header, payload, and trailer, exist
in various noncontiguous locations in memory. Scatter gather
DMA allows the segments to be concatenated together by using
multiple TDs in a chain. The chain gathers the data from the
multiple locations. A similar concept applies for the reception of
data onto the device. Certain parts of the received data may need
to be scattered to various locations in memory for software
processing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.
The interrupt controller provides a mechanism for hardware
resources to change program execution to a new address,
independent of the current task being executed by the main
code. The interrupt controller provides enhanced features not
found on original 8051 interrupt controllers:
4.4.4.4 Circular DMA
4.4.4.6 Packet Queuing DMA
Packet queuing DMA is similar to scatter gather DMA but
specifically refers to packet protocols. With these protocols,
there may be separate configuration, data, and status phases
associated with sending or receiving a packet.
For instance, to transmit a packet, a memory mapped
configuration register can be written inside a peripheral,
specifying the overall length of the ensuing data phase. The CPU
can set up this configuration information anywhere in system
memory and copy it with a simple TD to the peripheral. After the
configuration phase, a data phase TD (or a series of data phase
TDs) can begin (potentially using scatter gather). When the data
Document Number: 001-58402 Rev. *G
 Thirty-two interrupt vectors
 Jumps directly to ISR anywhere in code space with dynamic
vector addresses
 Multiple sources for each vector
 Flexible interrupt to vector matching
 Each interrupt vector is independently enabled or disabled
 Each interrupt can be dynamically assigned one of eight
priorities
 Eight level nestable interrupts
 Multiple I/O interrupt vectors
 Software can send interrupts
 Software can clear pending interrupts
Figure 4-2 on page 18 represents typical flow of events when an
interrupt triggered. Figure 4-3 on page 19 shows the interrupt
structure and priority polling.
Page 17 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 4-2. Interrupt Processing Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
S
Arrival of new Interrupt
S
Pend bit is set on next clock active edge
POST and PEND bits cleared after IRQ is sleared
S
Interrupt is posted to ascertain the priority
S
Interrupt request sent to core for processing
NA
NA
0x0010
IRQ cleared after receiving IRA
S
S
The active interrupt
number is posted to core
The active interrupt ISR
address is posted to core
S
S
NA
S
S
Interrupt generation and posting to CPU
CPU Response
Int. State
Clear
S
Completing current instruction and branching to vector address
Complete ISR and return
Notes
 1: Interrupt triggered asynchronous to the clock
 2: The PEND bit is set on next active clock edge to indicate the interrupt arrival
 3: POST bit is set following the PEND bit
 4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)
 5: ISR address is posted to CPU core for branching
 6: CPU acknowledges the interrupt request
 7: ISR address is read by CPU for branching
 8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
 10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)
 11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status
The total interrupt latency (ISR execution)
= POST + PEND + IRQ + IRA + Completing current instruction and branching
= 1+1+1+2+7 cycles
= 12 cycles
Document Number: 001-58402 Rev. *G
Page 18 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 4-3. Interrupt Structure
Interrupt Polling logic
Interrupts form Fixed
function blocks, DMA and
UDBs
Highest Priority
Interrupt Enable/
Disable, PEND and
POST logic
Interrupts 0 to 31
from UDBs
0
Interrupts 0 to 31
from Fixed
Function Blocks
1
IRQ
8 Level
Priority
decoder
for all
interrupts
Polling sequence
Interrupt
routing logic
to select 32
sources
Interrupt 2 to 30
Interrupts 0 to
31 from DMA
Individual
Enable Disable
bits
0 to 31
ACTIVE_INT_NUM
[15:0]
INT_VECT_ADDR
IRA
IRC
31
Global Enable
disable bit
When an interrupt is pending, the current instruction is completed and the program
counter is pushed onto the stack. Code execution then jumps to the program address
provided by the vector. After the ISR is completed, a RETI instruction is executed
and returns execution to the instruction following the previously interrupted
instruction. To do this the RETI instruction pops the program counter from the stack.
If the same priority level is assigned to two or more interrupts, the interrupt with the
lower vector number is executed first. Each interrupt vector may choose from three
interrupt sources: Fixed Function, DMA, and UDB. The fixed function interrupts are
Document Number: 001-58402 Rev. *G
Lowest Priority
direct connections to the most common interrupt sources and provide the lowest
resource cost connection. The DMA interrupt sources provide direct connections to
the two DMA interrupt sources provided per DMA channel. The third interrupt source
for vectors is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source. Fixed function interrupts
and all interrupt sources may be routed to any interrupt vector using the UDB
interrupt source connections.
Page 19 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 4-8. Interrupt Vector Table
#
Fixed Function
DMA
UDB
0
LVD
phub_termout0[0]
udb_intr[0]
1
Cache/ECC
phub_termout0[1]
udb_intr[1]
2
Reserved
phub_termout0[2]
udb_intr[2]
3
Sleep (Pwr Mgr)
phub_termout0[3]
udb_intr[3]
4
PICU[0]
phub_termout0[4]
udb_intr[4]
5
PICU[1]
phub_termout0[5]
udb_intr[5]
6
PICU[2]
phub_termout0[6]
udb_intr[6]
7
PICU[3]
phub_termout0[7]
udb_intr[7]
8
PICU[4]
phub_termout0[8]
udb_intr[8]
9
PICU[5]
phub_termout0[9]
udb_intr[9]
10
PICU[6]
phub_termout0[10]
udb_intr[10]
11
PICU[12]
phub_termout0[11]
udb_intr[11]
12
PICU[15]
phub_termout0[12]
udb_intr[12]
13
Comparators Combined
phub_termout0[13]
udb_intr[13]
14
Reserved
phub_termout0[14]
udb_intr[14]
phub_termout0[15]
udb_intr[15]
2
15
I C
16
Reserved
phub_termout1[0]
udb_intr[16]
17
Timer/Counter0
phub_termout1[1]
udb_intr[17]
18
Timer/Counter1
phub_termout1[2]
udb_intr[18]
19
Timer/Counter2
phub_termout1[3]
udb_intr[19]
20
Timer/Counter3
phub_termout1[4]
udb_intr[20]
21
USB SOF Int
phub_termout1[5]
udb_intr[21]
22
USB Arb Int
phub_termout1[6]
udb_intr[22]
23
USB Bus Int
phub_termout1[7]
udb_intr[23]
24
USB Endpoint[0]
phub_termout1[8]
udb_intr[24]
25
USB Endpoint Data
phub_termout1[9]
udb_intr[25]
26
Reserved
phub_termout1[10]
udb_intr[26]
27
LCD
phub_termout1[11]
udb_intr[27]
28
Reserved
phub_termout1[12]
udb_intr[28]
29
Decimator Int
phub_termout1[13]
udb_intr[29]
30
PHUB Error Int
phub_termout1[14]
udb_intr[30]
31
EEPROM Fault Int
phub_termout1[15]
udb_intr[31]
Document Number: 001-58402 Rev. *G
Page 20 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
5. Memory
5.1 Static RAM
CY8C32 SRAM is used for temporary data storage. Up to 8 KB
of SRAM is provided and can be accessed by the 8051 or the
DMA controller. See Memory Map on page 24. Simultaneous
access of SRAM by the 8051 and the DMA controller is possible
if different 4-KB blocks are accessed.
protecting your application from external access (see the
“Device Security” section on page 60). For more information
about how to take full advantage of the security features in
PSoC, see the PSoC 3 TRM.
Table 5-1. Flash Protection
Protection
Setting
Up to an additional 8 KB of flash space is available for ECC. If
ECC is not used this space can store device configuration data
and bulk user data. User code may not be run out of the ECC
flash memory section. ECC can correct one bit error and detect
two bit errors per 8 bytes of firmware memory; an interrupt can
be generated when an error is detected.
The CPU reads instructions located in flash through a cache
controller. This improves instruction execution rate and reduces
system power consumption by requiring less frequent flash
access. The cache has 8 lines at 64 bytes per line for a total of
512 bytes. It is fully associative, automatically controls flash
power, and can be enabled or disabled. If ECC is enabled, the
cache controller also performs error checking and correction,
and interrupt generation.
Flash programming is performed through a special interface and
preempts code execution out of flash. The flash programming
interface performs flash erasing, programming and setting code
protection levels. Flash in-system serial programming (ISSP),
typically used for production programming, is possible through
both the SWD and JTAG interfaces. In-system programming,
typically used for bootloaders, is also possible using serial
interfaces such as I2C, USB, UART, and SPI, or any
communications protocol.
5.3 Flash Security
All PSoC devices include a flexible flash-protection model that
prevents access and visibility to on-chip flash memory. This
prevents duplication or reverse engineering of proprietary code.
Flash memory is organized in blocks, where each block contains
256 bytes of program or data and 32 bytes of ECC or
configuration data. A total of up to 256 blocks is provided on
64-KB flash devices.
The device offers the ability to assign one of four protection
levels to each row of flash. Table 5-1 lists the protection modes
available. Flash protection levels can only be changed by
performing a complete flash erase. The Full Protection and Field
Upgrade settings disable external access (through a debugging
tool such as PSoC Creator, for example). If your application
requires code update through a bootloader, then use the Field
Upgrade setting. Use the Unprotected setting only when no
security is needed in your application. The PSoC device also
offers an advanced security feature called Device Security which
permanently disables all test, programming, and debug ports,
Document Number: 001-58402 Rev. *G
Not Allowed
Unprotected
External read and write –
+ internal read and write
Factory
Upgrade
External write + internal
read and write
5.2 Flash Program Memory
Flash memory in PSoC devices provides nonvolatile storage for
user firmware, user configuration data, bulk data storage, and
optional ECC data. The main flash memory area contains up to
64 KB of user program space.
Allowed
External read
Field Upgrade Internal read and write
External read and
write
Full Protection Internal read
External read and
write + internal write
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress data sheets. Cypress believes that its family
of products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as ‘unbreakable’. Cypress is willing to
work with the customer who is concerned about the integrity of
their code. Code protection is constantly evolving. We at Cypress
are committed to continuously improving the code protection
features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte-addressable nonvolatile
memory. The CY8C32 has up to 2 KB of EEPROM memory to
store user data. Reads from EEPROM are random access at the
byte level. Reads are done directly; writes are done by sending
write commands to an EEPROM programming interface. CPU
code execution can continue from flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into 128 rows of 16 bytes each. The CPU
can not execute out of EEPROM. There is no ECC hardware
associated with EEPROM. If ECC is required it must be handled
in firmware.
It can take as much as 20 milliseconds to write to EEPROM or
flash. During this time the device should not be reset, or
unexpected changes may be made to portions of EEPROM or
flash. Reset sources (see Section 6.3.1) include XRES pin,
software reset, and watchdog; care should be taken to make
sure that these are not inadvertently activated. Also, the low
voltage detect circuits should be configured to generate an
interrupt instead of a reset.
Page 21 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
5.5 Nonvolatile Latches (NVLs)
PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown
in Table 5-2.
Table 5-2. Device Configuration NVL Register Map
Register Address
7
6
5
4
3
2
1
0
0x00
PRT3RDM[1:0]
PRT2RDM[1:0]
PRT1RDM[1:0]
PRT0RDM[1:0]
0x01
PRT12RDM[1:0]
PRT6RDM[1:0]
PRT5RDM[1:0]
PRT4RDM[1:0]
0x02
XRESMEN
0x03
DBGEN
DIG_PHS_DLY[3:0]
PRT15RDM[1:0]
ECCEN
DPS[1:0]
CFGSPEED
The details for individual fields and their factory default settings are shown in Table 5-3:.
Table 5-3. Fields and Factory Default Settings
Field
Description
Settings
PRTxRDM[1:0]
Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog
See “Reset Configuration” on page 39. All pins of the port 01b - high impedance digital
are set to the same mode.
10b - resistive pull up
11b - resistive pull down
XRESMEN
Controls whether pin P1[2] is used as a GPIO or as an
external reset. See “Pin Descriptions” on page 9, XRES
description.
0 (default for 68-pin and 100-pin parts) - GPIO
1 (default for 48-pin parts) - external reset
DBGEN
Debug Enable allows access to the debug system, for
third-party programmers.
0 - access disabled
1 (default) - access enabled
DPS{1:0]
Controls the usage of various P1 pins as a debug port.
See “Programming, Debug Interfaces, Resources” on
page 57.
00b - 5-wire JTAG
01b (default) - 4-wire JTAG
10b - SWD
11b - debug ports disabled
ECCEN
Controls whether ECC flash is used for ECC or for general 0 - ECC disabled
configuration and data storage. See “Flash Program
1 (default) - ECC enabled
Memory” on page 21.
DIG_PHS_DLY[3:0]
Selects the digital clock phase delay.
See the TRM for details.
Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited
– see Nonvolatile Latches (NVL) on page 109.
Document Number: 001-58402 Rev. *G
Page 22 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
5.6 External Memory Interface
CY8C32 provides an EMIF for connecting to external memory
devices. The connection allows read and write accesses to
external memories. The EMIF operates in conjunction with
UDBs, I/O ports, and other hardware to generate external
memory address and control signals. At 33 MHz, each memory
access cycle takes four bus clock cycles. Figure 5-1 is the EMIF
block diagram. The EMIF supports synchronous and
asynchronous memories. The CY8C32 supports only one type
of external memory device at a time. External memory can be
accessed through the 8051 xdata space; up to 24 address bits
can be used. See “xdata Space” section on page 25. The
memory can be 8 or 16 bits wide.
Figure 5-1. EMIF Block Diagram
Address Signals
External_ MEM_ ADDR[23:0]
IO
PORTs
Data Signals
External_ MEM_ DATA[15:0]
IO
PORTs
Control Signals
IO
PORTs
Data,
Address,
and Control
Signals
IO IF
PHUB
Data,
Address,
and Control
Signals
Control
DSI Dynamic Output
Control
UDB
DSI to Port
Data,
Address,
and Control
Signals
EM Control
Signals
Other
Control
Signals
EMIF
Document Number: 001-58402 Rev. *G
Page 23 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
5.7 Memory Map
Figure 5-2. 8051 Internal Data Space
The CY8C32 8051 memory map is very similar to the MCS-51
memory map.
0x00
4 Banks, R0-R7 Each
0x1F
0x20
0x2F
0x30
5.7.1 Code Space
The CY8C32 8051 code space is 64 KB. Only main flash exists
in this space. See the Flash Program Memory on page 21.
5.7.2 Internal Data Space
Bit Addressable Area
Lower Core RAM Shared with Stack Space
(direct and indirect addressing)
0x7F
0x80
The CY8C32 8051 internal data space is 384 bytes, compressed
within a 256-byte space. This space consists of 256 bytes of
RAM (in addition to the SRAM mentioned in Static RAM on page
21) and a 128-byte space for special function registers (SFR).
See Figure 5-2. The lowest 32 bytes are used for 4 banks of
registers R0-R7. The next 16 bytes are bit-addressable.
0xFF
Upper Core RAM Shared
with Stack Space
(indirect addressing)
SFR
Special Function Registers
(direct addressing)
In addition to the register or bit address modes used with the
lower 48 bytes, the lower 128 bytes can be accessed with direct
or indirect addressing. With direct addressing mode, the upper
128 bytes map to the SFRs. With indirect addressing mode, the
upper 128 bytes map to RAM. Stack operations use indirect
addressing; the 8051 stack space is 256 bytes. See the
“Addressing Modes” section on page 10.
5.7.3 SFRs
The SFR space provides access to frequently accessed registers. The memory map for the SFR memory space is shown in Table 5-4.
Table 5-4. SFR Map
Address
0×F8
0/8
SFRPRT15DR
1/9
SFRPRT15PS
2/A
SFRPRT15SEL
3/B
–
4/C
–
5/D
–
6/E
–
7/F
–
0×F0
B
–
SFRPRT12SEL
–
–
–
–
–
0×E8
SFRPRT12DR
SFRPRT12PS
MXAX
–
–
–
–
–
0×E0
ACC
–
–
–
–
–
–
–
0×D8
SFRPRT6DR
SFRPRT6PS
SFRPRT6SEL
–
–
–
–
–
0×D0
PSW
–
–
–
–
–
–
–
0×C8
SFRPRT5DR
SFRPRT5PS
SFRPRT5SEL
–
–
–
–
–
0×C0
SFRPRT4DR
SFRPRT4PS
SFRPRT4SEL
–
–
–
–
–
–
–
–
–
–
0×B8
0×B0
SFRPRT3DR
SFRPRT3PS
SFRPRT3SEL
–
–
–
–
–
0×A8
IE
–
–
–
–
–
–
–
0×A0
P2AX
–
SFRPRT1SEL
–
–
–
–
–
0×98
SFRPRT2DR
SFRPRT2PS
SFRPRT2SEL
–
–
–
–
–
0×90
SFRPRT1DR
SFRPRT1PS
–
DPX0
–
DPX1
–
–
0×88
–
SFRPRT0PS
SFRPRT0SEL
–
–
–
–
–
0×80
SFRPRT0DR
SP
DPL0
DPH0
DPL1
DPH1
DPS
–
The CY8C32 family provides the standard set of registers found on industry standard 8051 devices. In addition, the CY8C32 devices
add SFRs to provide direct access to the I/O ports on the device. The following sections describe the SFRs added to the CY8C32
family.
Document Number: 001-58402 Rev. *G
Page 24 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
5.7.4 XData Space Access SFRs
5.7.5.1 xdata Space
The 8051 core features dual DPTR registers for faster data
transfer operations. The data pointer select SFR, DPS, selects
which data pointer register, DPTR0 or DPTR1, is used for the
following instructions:
The 8051 xdata space is 24-bit, or 16 MB in size. The majority of
this space is not ‘external’—it is used by on-chip components.
See Table 5-5. External, that is, off-chip, memory can be
accessed using the EMIF. See External Memory Interface on
page 23.
 MOVX @DPTR, A
 MOVX A, @DPTR
 MOVC A, @A+DPTR
 JMP @A+DPTR
 INC DPTR
 MOV DPTR, #data16
The extended data pointer SFRs, DPX0, DPX1, MXAX, and
P2AX, hold the most significant parts of memory addresses
during access to the xdata space. These SFRs are used only
with the MOVX instructions.
During a MOVX instruction using the DPTR0/DPTR1 register,
the most significant byte of the address is always equal to the
contents of DPX0/DPX1.
During a MOVX instruction using the R0 or R1 register, the most
significant byte of the address is always equal to the contents of
MXAX, and the next most significant byte is always equal to the
contents of P2AX.
5.7.5 I/O Port SFRs
The I/O ports provide digital input sensing, output drive, pin
interrupts, connectivity for analog inputs and outputs, LCD, and
access to peripherals through the DSI. Full information on I/O
ports is found in I/O System and Routing on page 33.
I/O ports are linked to the CPU through the PHUB and are also
available in the SFRs. Using the SFRs allows faster access to a
limited set of I/O port registers, while using the PHUB allows boot
configuration and access to all I/O port registers.
Table 5-5. XDATA Data Address Map
Address Range
0×00 0000 – 0×00 1FFF
SRAM
0×00 4000 – 0×00 42FF
Clocking, PLLs, and oscillators
0×00 4300 – 0×00 43FF
Power management
0×00 4400 – 0×00 44FF
Interrupt controller
0×00 4500 – 0×00 45FF
Ports interrupt control
0×00 4700 – 0×00 47FF
Flash programming interface
0×00 4800 - 0×00 48FF
Cache controller
0×00 4900 – 0×00 49FF
I2C controller
0×00 4E00 – 0×00 4EFF
Decimator
0×00 4F00 – 0×00 4FFF
Fixed timer/counter/PWMs
0×00 5000 – 0×00 51FF
I/O ports control
0×00 5400 – 0×00 54FF
EMIF control registers
0×00 5800 – 0×00 5FFF
Analog subsystem interface
0×00 6000 – 0×00 60FF
USB controller
0×00 6400 – 0×00 6FFF
UDB Working Registers
0×00 7000 – 0×00 7FFF
PHUB configuration
0×00 8000 – 0×00 8FFF
EEPROM
0×00 A000 – 0×00 A400
Reserved
0×00 C000 – 0×00 C800
Reserved
0×01 0000 – 0×01 FFFF
Digital Interconnect
configuration
0×05 0220 – 0×05 02F0
Debug controller
0×08 0000 – 0×08 1FFF
Flash ECC bytes
0×80 0000 – 0×FF FFFF
External memory interface
Each SFR supported I/O port provides three SFRs:
 SFRPRTxDR sets the output data state of the port (where × is
port number and includes ports 0–6, 12 and 15).
 The SFRPRTxSEL selects whether the PHUB PRTxDR
Purpose
register or the SFRPRTxDR controls each pin’s output buffer
within the port. If a SFRPRTxSEL[y] bit is high, the
corresponding SFRPRTxDR[y] bit sets the output state for that
pin. If a SFRPRTxSEL[y] bit is low, the corresponding
PRTxDR[y] bit sets the output state of the pin (where y varies
from 0 to 7).
 The SFRPRTxPS is a read only register that contains pin state
values of the port pins.
Document Number: 001-58402 Rev. *G
Page 25 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
6. System Integration
Key features of the clocking system include:
 Seven general purpose clock sources
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 50 MHz clock, accurate to ±1 percent over
voltage and temperature. Additional internal and external clock
sources allow each design to optimize accuracy, power, and
cost. Any of the clock sources can be used to generate other
clock frequencies in the 16-bit clock dividers and UDBs for
anything the user wants, for example a UART baud rate
generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows you to build clocking
systems with minimal input. You can specify desired clock
frequencies and accuracies, and the software locates or builds a
clock that meets the required specifications. This is possible
because of the programmability inherent in PSoC.
3- to 62-MHz IMO, ±1% at 3 MHz
4- to 25-MHz external crystal oscillator (MHzECO)
 Clock doubler provides a doubled clock frequency output for
the USB block, see USB Clock Domain on page 28.
 DSI signal from an external I/O pin or other logic
 24- to 50-MHz fractional PLL sourced from IMO, MHzECO,
or DSI
 1-kHz, 33-kHz, 100-kHz ILO for WDT and sleep timer
 32.768-kHz external crystal oscillator (kHzECO) for RTC
 IMO has a USB mode that auto locks to the USB bus clock
requiring no external crystal for USB (USB equipped parts only)


 Independently sourced clock in all clock dividers
 Eight 16-bit clock dividers for the digital system
 Four 16-bit clock dividers for the analog system
 Dedicated 16-bit divider for the bus clock
 Dedicated 4-bit divider for the CPU clock
 Automatic clock configuration in PSoC Creator
Table 6-1. Oscillator Summary
Source
Fmin
Tolerance at Fmin
Fmax
Tolerance at Fmax
Startup Time
IMO
3 MHz
±1% over voltage and temperature
62 MHz
±7%
13 µs max
MHzECO
4 MHz
Crystal dependent
25 MHz
Crystal dependent
5 ms typ, max is crystal dependent
DSI
0 MHz
Input dependent
50 MHz
Input dependent
Input dependent
PLL
24 MHz
Input dependent
50 MHz
Input dependent
250 µs max
Doubler
48 MHz
Input dependent
48 MHz
Input dependent
1 µs max
ILO
1 kHz
–50%, +100%
100 kHz –55%, +100%
15 ms max in lowest power mode
kHzECO
32 kHz
Crystal dependent
32 kHz
500 ms typ, max is crystal dependent
Document Number: 001-58402 Rev. *G
Crystal dependent
Page 26 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 6-1. Clocking Subsystem
3-72 MHz
IMO
4-33 MHz
ECO
External IO
or DSI
0-50 MHz
32 kHz ECO
1,33,100 kHz
ILO
12-72 MHz
Doubler
24-50 MHz
PLL
System
Clock Mux
Bus/CPU Clock
Divider 16 bit
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
7
6.1.1 Internal Oscillators
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±1-percent accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±1 percent at 3 MHz, up to ±7 percent at
62 MHz. The IMO, in conjunction with the PLL, allows generation
of other clocks up to the device's maximum frequency (see PLL).
The IMO provides clock outputs at 3, 6, 12, 24, 48, and 62 MHz.
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works at input frequency of 24 MHz,
providing 48 MHz for the USB. It can be configured to use a clock
from the IMO, MHzECO, or the DSI (external pin).
6.1.1.3 PLL
The PLL allows low-frequency, high-accuracy clocks to be
multiplied to higher frequencies. This is a trade off between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 50 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
almost any desired clock frequency. The accuracy of the PLL
output depends on the accuracy of the PLL input source. The
most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate, to generate the other clocks up to the
device’s maximum frequency.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO or DSI (external pin). The PLL clock source can be
Document Number: 001-58402 Rev. *G
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low-power modes.
6.1.1.4 Internal Low-Speed Oscillator
The ILO provides clock frequencies for low-power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz. The 1-kHz clock (CLK1K) is typically used for a
background ‘heartbeat’ timer. This clock inherently lends itself to
low-power supervisory operations such as the watchdog timer
and long sleep intervals using the central timewheel (CTW).
The central timewheel is a 1-kHz, free running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled,
except in hibernate mode and when the CPU is stopped during
debug on chip mode. It can be used to generate periodic
interrupts for timing purposes or to wake the system from a
low-power mode. Firmware can reset the central timewheel.
Systems that require accurate timing should use the RTC
capability instead of the central timewheel.
The 100-kHz clock (CLK100K) can be used as a low power
master clock. It can also generate time intervals using the fast
timewheel.
The fast timewheel is a 5-bit counter, clocked by the 100-kHz
clock. It features programmable settings and automatically
resets when the terminal count is reached. An optional interrupt
can be generated each time the terminal count is reached. This
enables flexible, periodic interrupts of the CPU at a higher rate
than is allowed using the central timewheel.
The 33-kHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768-kHz ECO clock with no need for a crystal.
Page 27 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
6.1.2 External Oscillators
6.1.2.1 MHz External Crystal Oscillator
The MHzECO provides high frequency, high precision clocking
using an external crystal (see Figure 6-2). It supports a wide
variety of crystal types, in the range of 4 to 25 MHz. When used
in conjunction with the PLL, it can generate other clocks up to the
device's maximum frequency (see PLL). The GPIO pins
connecting to the external crystal and capacitors are fixed.
MHzECO accuracy depends on the crystal chosen.
Figure 6-2. MHzECO Block Diagram
4 - 25 MHz
Crystal Osc
XCLK_MHZ
4 –25 MHz
crystal
External
Components
6.1.2.3 Digital System Interconnect
The DSI provides routing for clocks taken from external clock
oscillators connected to I/O. The oscillators can also be
generated within the device in the digital system and UDBs.
While the primary DSI clock input provides access to all clocking
resources, up to eight other DSI clocks (internally or externally
generated) may be routed directly to the eight digital clock
dividers. This is only possible if there are multiple precision clock
sources.
6.1.3 Clock Distribution
Xo
(Pin P15[0])
Xi
(Pin P15[1])
capacitance, should equal the crystal CL value. For more
information, refer to application note AN54439: PSoC 3 and
PSoC 5 External Oscillators. See also pin capacitance
specifications in the “GPIO” section on page 71.
Capacitors
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
 The master clock is used to select and supply the fastest clock
in the system for general clock requirements and clock
synchronization of the PSoC device.
 Bus clock 16-bit divider uses the master clock to generate the
6.1.2.2 32.768-kHz ECO
The 32.768-kHz external crystal oscillator (32kHzECO) provides
precision timing with minimal power consumption using an
external 32.768-kHz watch crystal (see Figure 6-3). The
32kHzECO also connects directly to the sleep timer and provides
the source for the RTC. The RTC uses a 1-second interrupt to
implement the RTC functionality in firmware.
The oscillator works in two distinct power modes. This allows
users to trade off power consumption with noise immunity from
neighboring circuits. The GPIO pins connected to the external
crystal and capacitors are fixed.
Figure 6-3. 32kHzECO Block Diagram
32 kHz
Crystal Osc
Xi
(Pin P15[3])
External
Components
XCLK32K
Xo
(Pin P15[2])
32 kHz
crystal
Capacitors
It is recommended that the external 32.768-kHz watch crystal
have a load capacitance (CL) of 6 pF or 12.5 pF. Check the
crystal manufacturer's datasheet. The two external capacitors,
CL1 and CL2, are typically of the same value, and their total
capacitance, CL1CL2 / (CL1 + CL2), including pin and trace
Document Number: 001-58402 Rev. *G
bus clock used for data transfers. Bus clock is the source clock
for the CPU clock divider.
 Eight fully programmable 16-bit clock dividers generate digital
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
many others. If more than eight digital clock dividers are
required, the UDBs and fixed function timer/counter/PWMs can
also generate clocks.
 Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, such as ADC. The analog
clock dividers include skew control to ensure that critical analog
events do not occur simultaneously with digital switching
events. This is done to reduce analog system noise.
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50 percent
duty cycle clocks, master clock resynchronization logic, and
deglitch logic. The outputs from each digital clock tree can be
routed into the digital system interconnect and then brought back
into the clock system as an input, allowing clock chaining of up
to 32 bits.
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
Page 28 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
6.2 Power System
The power system consists of separate analog, digital, and I/O supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It also
includes two internal 1.8-V regulators that provide the digital (VCCD) and analog (VCCA) supplies for the internal core logic. The
output pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in Figure 6-4. The
two VCCD pins must be shorted together, with as short a trace as possible, and connected to a 1-µF ±10-percent X5R capacitor. The
power system also contains a sleep regulator, an I2C regulator, and a hibernate regulator.
Figure 6-4. PSoC Power System
VDDD
1 µF
VDDIO2
VDDD
I/O Supply
VSSD
VCCD
VDDIO 2
VDDIO0
0.1 µF
0.1 µF
I/O Supply
VDDIO0
0.1 µF
I2C
Regulator
Sleep
Regulator
Digital
Domain
VDDA
VDDA
VCCA
Analog
Regulator
Digital
Regulators
VSSD
0.1 µF
1 µF
.
VSSA
Analog
Domain
0.1 µF
I/O Supply
VDDIO3
VDDD
VSSD
I/O Supply
VCCD
VDDIO1
Hibernate
Regulator
0.1 µF
0.1 µF
VDDIO1
VDDD
VDDIO3
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,
as shown in Figure 2-6 on page 9.
You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the internal
regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins to the VCCx
pins.
You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this configuration,
the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The allowed supply range in
this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be
disabled to reduce power consumption.
Document Number: 001-58402 Rev. *G
Page 29 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
6.2.1 Power Modes
PSoC 3 devices have four different power modes, as shown in
Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
 Active
 Alternate Active
 Sleep
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins. Figure 6-5 on page 31 illustrates the allowable
transitions between power modes. Sleep and hibernate modes
should not be entered until all VDDIO supplies are at valid
voltage levels.
 Hibernate
Table 6-2. Power Modes
Power Modes
Description
Active
Primary mode of operation, all
peripherals available
(programmable)
Alternate
Active
Entry Condition Wakeup Source Active Clocks
Regulator
Wakeup, reset, Any interrupt
Any
All regulators available.
manual register
(programmable) Digital and analog
entry
regulators can be disabled
if external regulation used.
Manual register Any interrupt
Any
All regulators available.
entry
(programmable) Digital and analog
regulators can be disabled
if external regulation used.
Similar to Active mode, and is
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
All subsystems automatically
Manual register
disabled
entry
Sleep
Manual register
All subsystems automatically
entry
disabled
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
Hibernate
Comparator,
ILO/kHzECO
PICU, I2C, RTC,
CTW, LVD
PICU
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Only hibernate regulator
active.
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Active
Alternate
Active
Sleep
Wakeup
Time
Current
(typ)
Code
Execution
Digital
Resources
Analog
Resources
Clock Sources
Available
Wakeup Sources
Reset
Sources
–
1.2 mA[9]
Yes
All
All
All
–
All
–
–
User
defined
All
All
All
–
All
<15 µs
1 µA
No
I2C
Comparator
ILO/kHzECO
Comparator,
PICU, I2C, RTC,
CTW, LVD
XRES, LVD,
WDR
200 nA
No
None
None
None
PICU
XRES
Hibernate <100 µs
Note
9. Bus clock off. Execute from cache at 6 MHz. See Table 11-2 on page 63.
Document Number: 001-58402 Rev. *G
Page 30 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 6-5. Power Mode Transitions
Active
Manual
Sleep
Hibernate
Buzz
Alternate
Active
6.2.1.1 Active Mode
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
6.2.1.2 Alternate Active Mode
Alternate Active mode is very similar to Active mode. In alternate
active mode, fewer subsystems are enabled, to reduce power
consumption. One possible configuration is to turn off the CPU
and flash, and run peripherals at full speed.
6.2.1.5 Wakeup Events
Wakeup events are configurable and can come from an interrupt
or device reset. A wakeup event restores the system to active
mode. Firmware enabled interrupt sources include internally
generated interrupts, power supervisor, central timewheel, and
I/O interrupts. Internal interrupt sources can come from a variety
of peripherals, such as analog comparators and UDBs. The
central timewheel provides periodic interrupts to allow the
system to wake up, poll peripherals, or perform real-time
functions. Reset event sources include the external reset I/O pin
(XRES), WDT, and precision reset (PRES).
6.3 Reset
CY8C32 has multiple internal and external reset sources
available. The reset sources are:
 Power source monitoring – The analog and digital power
voltages, VDDA, VDDD, VCCA, and VCCD are monitored in
several different modes during power up, active mode, and
sleep mode (buzzing). If any of the voltages goes outside
predetermined ranges then a reset is generated. The monitors
are programmable to generate an interrupt to the processor
under certain conditions before reaching the reset thresholds.
 External – The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull-up to VDDIO1. VDDD, VDDA, and VDDIO1 must
all have voltage applied before the part comes out of reset.
 Watchdog timer – A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset.
 Software – The device can be reset under program control.
Figure 6-6. Resets
Vddd Vdda
6.2.1.3 Sleep Mode
Sleep mode reduces power consumption when a resume time of
15 µs is acceptable. The wake time is used to ensure that the
regulator outputs are stable enough to directly enter active
mode.
6.2.1.4 Hibernate Mode
In hibernate mode nearly all of the internal functions are
disabled. Internal voltages are reduced to the minimal level to
keep vital systems alive. Configuration state is preserved in
hibernate mode and SRAM memory is retained. GPIOs
configured as digital outputs maintain their previous values and
external GPIO pin interrupt settings are preserved. The device
can only return from hibernate mode in response to an external
I/O interrupt. The resume time from hibernate mode is less than
100 µs.
To achieve an extremely low current, the hibernate regulator has
limited capacity. This limits the frequency of any signal present
on the input pins - no GPIO should toggle at a rate greater than
10 kHz while in hibernate mode. If pins must be toggled at a high
rate while in a low power mode, use sleep mode instead.
Power
Voltage
Level
Monitors
Reset
Pin
External
Reset
Processor
Interrupt
Reset
Controller
System
Reset
Watchdog
Timer
Software
Reset
Register
The term device reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register shows some of the resets or power voltage
monitoring interrupts. The program may examine this register to
Document Number: 001-58402 Rev. *G
Page 31 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
detect and report certain exception conditions. This register is
cleared after a power-on reset. For details see the Technical
Reference Manual.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
 IPOR – Initial power-on reset
At initial power on, IPOR monitors the power voltages VDDD,
VDDA, VCCD and VCCA. The trip level is not precise. It is set to
approximately 1 volt, which is below the lowest specified
operating voltage but high enough for the internal circuits to be
reset and to hold their reset state. The monitor generates a
reset pulse that is at least 150 ns wide. It may be much wider
if one or more of the voltages ramps up slowly.
If after the IPOR triggers either VDDX drops back below the
trigger point, in a non-monotonic fashion, it must remain below
that point for at least 10 µs. The hysteresis of the IPOR trigger
point is typically 100 mV.
After boot, the IPOR circuit is disabled and voltage supervision
is handed off to the precise low-voltage reset (PRES) circuit.
 PRES – Precise low voltage reset
This circuit monitors the outputs of the analog and digital
internal regulators after power up. The regulator outputs are
compared to a precise reference voltage. The response to a
PRES trip is identical to an IPOR reset.
After PRES has been deasserted, at least 10 µs must elapse
before it can be reasserted.
In normal operating mode, the program cannot disable the
digital PRES circuit. The analog regulator can be disabled,
which also disables the analog portion of the PRES. The PRES
circuit is disabled automatically during sleep and hibernate
modes, with one exception: During sleep mode the regulators
are periodically activated (buzzed) to provide supervisory
services and to reduce wakeup time. At these times the PRES
circuit is also buzzed to allow periodic voltage monitoring.
 ALVI, DLVI, AHVI – Analog/digital low voltage interrupt, analog
high voltage interrupt
Interrupt circuits are available to detect when VDDA and
VDDD go outside a voltage range. For AHVI, VDDA is
compared to a fixed trip level. For ALVI and DLVI, VDDA and
VDDD are compared to trip levels that are programmable, as
listed in Table 6-4. ALVI and DLVI can also be configured to
generate a device reset instead of an interrupt.
Document Number: 001-58402 Rev. *G
Table 6-4. Analog/Digital Low Voltage Interrupt, Analog High
Voltage Interrupt
Normal Voltage
Available Trip Settings
Range
VDDD 1.71 V–5.5 V
1.70 V–5.45 V in 250 mV
increments
VDDA 1.71 V–5.5 V
1.70 V–5.45 V in 250 mV
increments
VDDA 1.71 V–5.5 V
5.75 V
Interrupt Supply
DLVI
ALVI
AHVI
The monitors are disabled until after IPOR. During sleep mode
these circuits are periodically activated (buzzed). If an interrupt
occurs during buzzing then the system first enters its wakeup
sequence. The interrupt is then recognized and may be
serviced.
The buzz frequency is adjustable, and should be set to be less
than the minimum time that any voltage is expected to be out
of range. For details on how to adjust the buzz frequency, see
the TRM.
6.3.1.2 Other Reset Sources
 XRES – External reset
PSoC 3 has either a single GPIO pin that is configured as an
external reset or a dedicated XRES pin. Either the dedicated
XRES pin or the GPIO pin, if configured, holds the part in reset
while held active (low). The response to an XRES is the same
as to an IPOR reset.
After XRES has been deasserted, at least 10 µs must elapse
before it can be reasserted.
The external reset is active low. It includes an internal pull-up
resistor. XRES is active during sleep and hibernate modes.
 SRES – Software reset
A reset can be commanded under program control by setting
a bit in the software reset register. This is done either directly
by the program or indirectly by DMA access. The response to
a SRES is the same as after an IPOR reset.
Another register bit exists to disable this function.
 WRES – Watchdog timer reset
The watchdog reset detects when the software program is no
longer being executed correctly. To indicate to the watchdog
timer that it is running correctly, the program must periodically
reset the timer. If the timer is not reset before a user-specified
amount of time, then a reset is generated.
Note IPOR disables the watchdog function. The program must
enable the watchdog function at an appropriate point in the
code by setting a register bit. When this bit is set, it cannot be
cleared again except by an IPOR power on reset event.
Page 32 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
6.4 I/O System and Routing
PSoC I/Os are extremely flexible. Every GPIO has analog and
digital I/O capability. All I/Os have a large number of drive modes,
which are set at POR. PSoC also provides up to four individual
I/O voltage domains through the VDDIO pins.
There are two types of I/O pins on every device; those with USB
provide a third type. Both GPIO and SIO provide similar digital
functionality. The primary differences are their analog capability
and drive strength. Devices that include USB also provide two
USBIO pins that support specific USB functionality as well as
limited GPIO capability.
All I/O pins are available for use as digital inputs and outputs for
both the CPU and digital peripherals. In addition, all I/O pins can
generate an interrupt. The flexible and advanced capabilities of
the PSoC I/O, combined with any signal to any pin routability,
greatly simplify circuit design and board layout. All GPIO pins can
be used for analog input, CapSense, and LCD segment drive,
while SIO pins are used for voltages in excess of VDDA and for
programmable output voltages.
 Features supported by both GPIO and SIO:
 User programmable port reset state
 Separate I/O supplies and voltages for up to four groups of I/O
 Digital peripherals use DSI to connect the pins
 Input or output or both for CPU and DMA
 Eight drive modes
 Every pin can be an interrupt source configured as rising
edge, falling edge or both edges. If required, level sensitive
interrupts are supported through the DSI
 Dedicated port interrupt vector for each port
Document Number: 001-58402 Rev. *G
Slew rate controlled digital output drive mode
Access port control and configuration registers on either port
basis or pin basis
 Separate port read (PS) and write (DR) data registers to avoid
read modify write errors
 Special functionality on a pin by pin basis
 Additional features only provided on the GPIO pins:
 LCD segment drive on LCD equipped devices
 CapSense
 Analog input and output capability
 Continuous 100 µA clamp current capability
 Standard drive strength down to 1.7 V
 Additional features only provided on SIO pins:
 Higher drive strength than GPIO
 Hot swap capability (5 V tolerance at any operating VDD)
 Programmable and regulated high input and output drive
levels down to 1.2 V
 No analog input, CapSense, or LCD capability
 Over voltage tolerance up to 5.5 V
 SIO can act as a general purpose analog comparator
 USBIO features:
 Full speed USB 2.0 compliant I/O
 Highest drive strength for general purpose use
 Input, output, or both for CPU and DMA
 Input, output, or both for digital peripherals
 Digital output (CMOS) drive mode
 Each pin can be an interrupt source configured as rising
edge, falling edge, or both edges


Page 33 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 6-7. GPIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
PRT[x]CTL
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
PRT[x]SLW
PRT[x]SYNC_OUT
Vddio Vddio
PRT[x]DR
0
Digital System Output
In
1
Vddio
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Analog
Slew
Cntl
PIN
OE
1
Capsense Global Control
0
1
0
1
CAPS[x]CFG1
Switches
PRT[x]AG
Analog Global Enable
PRT[x]AMUX
Analog Mux Enable
LCD
Display
Data
PRT[x]LCD_COM_SEG
Logic & MUX
PRT[x]LCD_EN
LCD Bias Bus
Document Number: 001-58402 Rev. *G
5
Page 34 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 6-8. SIO Input/Output Block Diagram
Digital Input Path
PRT[x]SIO_HYST_EN
PRT[x]SIO_DIFF
Reference Level
PRT[x]DBL_SYNC_IN
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
Buffer
Thresholds
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
Reference Level
PRT[x]SIO_CFG
PRT[x]SLW
PRT[x]SYNC_OUT
PRT[x]DR
Driver
Vhigh
0
Digital System Output
In
1
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Slew
Cntl
PIN
OE
Figure 6-9. USBIO Block Diagram
Digital Input Path
Naming Convention
‘y’ = Pin Number
USB Receiver Circuitry
PRT[15]DBL_SYNC_IN
PRT[15]PS[6,7]
USBIO_CR1[0,1]
Digital System Input
PICU[15]INTTYPE[y]
PICU[15]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[15]INTSTAT
Digital Output Path
PRT[15]SYNC_OUT
USBIO_CR1[5]
USB or I/O
USBIO_CR1[2]
Vddd
USB SIE Control for USB Mode
PRT[15]DR1[7,6]
Digital System Output
PRT[15]BYP
1
In
Drive
Logic
D+ Open
Drain
PRT[15]DM0[7]
D- Open
Drain
PRT[15]DM1[7]
Document Number: 001-58402 Rev. *G
0
PRT[15]DM0[6]
PRT[15]DM1[6]
D+ pin only
D+ 1.5 k
Vddd
5k
Vddd Vddd
1.5 k
PIN
D+ 5 k
D- 5 k
Page 35 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
6.4.1 Drive Modes
Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-5. Three configuration bits are
used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-10 depicts a simplified pin view based on each of the eight
drive modes. Table 6-5 shows the I/O pin’s drive state based on the port data register value or digital array signal if bypass mode is
selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For
example, if a GPIO pin is configured for resistive pull-up mode and driven high while the pin is floating, the voltage measured at the
pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state.
Figure 6-10. Drive Mode
Vddio
DR
PS
0.
Pin
High Impedance
Analog
DR
PS
1.
DR
PS
Pin
High Impedance
Digital
Pin
2. Resistive
Pull Up
Vddio
DR
PS
Pin
4. Open Drain,
Drives Low
DR
PS
Vddio
DR
PS
3. Resistive
Pull Down
Vddio
DR
PS
Pin
5. Open Drain,
Drives High
Vddio
Pin
6. Strong Drive
Pin
DR
PS
Pin
7. Resistive
Pull Up and Down
Table 6-5. Drive Modes
Diagram
PRTxDM2
PRTxDM1
PRTxDM0
PRTxDR = 1
PRTxDR = 0
0
High impedance analog
Drive Mode
0
0
0
High Z
High Z
1
High Impedance digital
0
0
1
High Z
High Z
2
Resistive pull-up[10]
0
1
0
Res High (5K)
Strong Low
3
Resistive pull-down[10]
0
1
1
Strong High
Res Low (5K)
4
Open drain, drives low
1
0
0
High Z
Strong Low
5
Open drain, drive high
1
0
1
Strong High
High Z
6
Strong drive
1
1
0
Strong High
Strong Low
7
Resistive pull-up and pull-down[10]
1
1
1
Res High (5K)
Res Low (5K)
Note
10. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
Document Number: 001-58402 Rev. *G
Page 36 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
The USBIO pins (P15[7] and P15[6]), when enabled for I/O mode, have limited drive mode control. The drive mode is set using the
PRT15.DM0[7, 6] register. A resistive pull option is also available at the USBIO pins, which can be enabled using the PRT15.DM1[7,
6] register. When enabled for USB mode, the drive mode control has no impact on the configuration of the USB pins. Unlike the GPIO
and SIO configurations, the port wide configuration registers do not configure the USB drive mode bits. Table 6-6 shows the drive
mode configuration for the USBIO pins.
Table 6-6. USBIO Drive Modes (P15[7] and P15[6])
PRT15.DM1[7,6]
Pull up enable
PRT15.DM0[7,6]
Drive Mode enable
0
0
High Z
Strong Low
Open Drain, Strong Low
0
1
Strong High
Strong Low
Strong Outputs
1
0
Res High (5k)
Strong Low
Resistive Pull Up, Strong Low
1
1
Strong High
Strong Low
Strong Outputs
PRT15.DR[7,6] = 1
 High impedance analog
PRT15.DR[7,6] = 0
Description
6.4.2 Pin Registers
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/O’s digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not provide
digital input functionality.
Registers to configure and interact with pins come in two forms
that may be used interchangeably.
To achieve the lowest chip current in sleep modes, all I/Os
must either be configured to the high impedance analog mode,
or have their pins driven to a power supply rail by the PSoC
device or by external circuitry.
I/O registers are also available in pin form, which combines the
eight most commonly used port register bits into a single register
for each pin. This enables very fast configuration changes to
individual pins with a single register write.
 High impedance digital
The input buffer is enabled for digital signal input. This is the
standard high impedance (High Z) state recommended for
digital inputs.
 Resistive pull-up or resistive pull-down
Resistive pull-up or pull-down, respectively, provides a series
resistance in one of the data states and strong drive in the
other. Pins can be used for digital input and output in these
modes. Interfacing to mechanical switches is a common
application for these modes. Resistive pullup and pull-down
are not available with SIO in regulated output mode.
 Open drain, drives high and open drain, drives low
Open drain modes provide high impedance in one of the data
states and strong drive in the other. Pins can be used for digital
input and output in these modes. A common application for
these modes is driving the I2C bus signal lines.
 Strong drive
Provides a strong CMOS output drive in either high or low
state. This is the standard output mode for pins. Strong Drive
mode pins must not be used as inputs under normal
circumstances. This mode is often used to drive digital output
signals or external FETs.
All I/O registers are available in the standard port form, where
each bit of the register corresponds to one of the port pins. This
register form is efficient for quickly reconfiguring multiple port
pins at the same time.
6.4.3 Bidirectional Mode
High speed bidirectional capability allows pins to provide both
the high impedance digital drive mode for input signals and a
second user selected drive mode such as strong drive (set using
PRT×DM[2:0] registers) for output signals on the same pin,
based on the state of an auxiliary control bus signal. The
bidirectional capability is useful for processor busses and
communications interfaces such as the SPI Slave MISO pin that
requires dynamic hardware control of the output buffer.
The auxiliary control bus routes up to 16 UDB or digital peripheral
generated output enable signals to one or more pins.
6.4.4 Slew Rate Limited Mode
GPIO and SIO pins have fast and slow output slew rate options
for strong and open drain drive modes, not resistive drive modes.
Because it results in reduced EMI, the slow edge rate option is
recommended for signals that are not speed critical, generally
less than 1 MHz. The fast slew rate is for signals between 1 MHz
and 33 MHz. The slew rate is individually configurable for each
pin, and is set by the PRT×SLW registers.
 Resistive pull-up and pull-down
Similar to the resistive pull-up and resistive pull-down modes
except the pin is always in series with a resistor. The high data
state is pull-up while the low data state is pull-down. This mode
is most often used when other signals that may cause shorts
can drive the bus. Resistive pullup and pull-down are not
available with SIO in regulated output mode.
Document Number: 001-58402 Rev. *G
Page 37 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
6.4.5 Pin Interrupts
All GPIO and SIO pins are able to generate interrupts to the
system. All eight pins in each port interface to their own Port
Interrupt Control Unit (PICU) and associated interrupt vector.
Each pin of the port is independently configurable to detect rising
edge, falling edge, both edge interrupts, or to not generate an
interrupt.
Depending on the configured mode for each pin, each time an
interrupt event occurs on a pin, its corresponding status bit of the
interrupt status register is set to ‘1’ and an interrupt request is
sent to the interrupt controller. Each PICU has its own interrupt
vector in the interrupt controller and the pin status register
providing easy determination of the interrupt source down to the
pin level.
external signals that are lower in voltage than the SIO’s
respective VDDIO. SIO pins are individually configurable to
output either the standard VDDIO level or the regulated output,
which is based on an internally generated reference. Typically a
voltage DAC (VDAC) is used to generate the reference (see
Figure 6-11). The “DAC” section on page 56 has more details on
VDAC use and reference routing to the SIO pins. Resistive
pullup and pull-down drive modes are not available with SIO in
regulated output mode.
6.4.12 Adjustable Input Level
Port pin interrupts remain active in all sleep modes allowing the
PSoC device to wake from an externally generated interrupt.
While level sensitive interrupts are not directly supported; UDB
provide this functionality to the system when needed.
This section applies only to SIO pins. SIO pins by default support
the standard CMOS and LVTTL input levels but also support a
differential mode with programmable levels. SIO pins are
grouped into pairs. Each pair shares a reference generator block
which, is used to set the digital input buffer reference level for
interface to external signals that differ in voltage from VDDIO.
The reference sets the pins voltage threshold for a high logic
level (see Figure 6-11). Available input thresholds are:
6.4.6 Input Buffer Mode
 0.5 VDDIO
GPIO and SIO input buffers can be configured at the port level
for the default CMOS input thresholds or the optional LVTTL
input thresholds. All input buffers incorporate Schmitt triggers for
input hysteresis. Additionally, individual pin input buffers can be
disabled in any drive mode.
 0.4 VDDIO
6.4.7 I/O Power Supplies
Up to four I/O pin power supplies are provided depending on the
device and package. Each I/O supply must be less than or equal
to the voltage on the chip’s analog (VDDA) pin. This feature
allows users to provide different I/O voltage levels for different
pins on the device. Refer to the specific device package pinout
to determine VDDIO capability for a given port and pin. The SIO
port pins support an additional regulated high output capability,
as described in Adjustable Output Level.
 0.5 VREF
 VREF
Typically a voltage DAC (VDAC) generates the VREF reference.
“DAC” section on page 56 has more details on VDAC use and
reference routing to the SIO pins.
Figure 6-11. SIO Reference for Input and Output
Input Path
Digital
Input
Vinref
6.4.8 Analog Connections
These connections apply only to GPIO pins. All GPIO pins may
be used as analog inputs or outputs. The analog voltage present
on the pin must not exceed the VDDIO supply voltage to which
the GPIO belongs. Each GPIO may connect to one of the analog
global busses or to one of the analog mux buses to connect any
pin to any internal analog resource such as ADC or comparators.
In addition, select pins provide direct connections to specific
analog features such as the high current DAC.
Reference
Generator
SIO_Ref
PIN
Voutref
Output Path
Driver
Vhigh
6.4.9 CapSense
This section applies only to GPIO pins. All GPIO pins may be
used to create CapSense buttons and sliders. See the
“CapSense” section on page 55 for more information.
6.4.10 LCD Segment Drive
This section applies only to GPIO pins. All GPIO pins may be
used to generate Segment and Common drive signals for direct
glass drive of LCD glass. See the “LCD Direct Drive” section on
page 54 for details.
Digital
Output
Drive
Logic
6.4.11 Adjustable Output Level
This section applies only to SIO pins. SIO port pins support the
ability to provide a regulated high output level for interface to
Document Number: 001-58402 Rev. *G
Page 38 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
6.4.13 SIO as Comparator
This section applies only to SIO pins. The adjustable input level
feature of the SIOs as explained in the Adjustable Input Level
section can be used to construct a comparator. The threshold for
the comparator is provided by the SIO's reference generator. The
reference generator has the option to set the analog signal
routed through the analog global line as threshold for the
comparator. Note that a pair of SIO pins share the same
threshold. The digital input path in Figure 6-8 on page 35
illustrates this functionality. In the figure, ‘Reference level’ is the
analog signal routed through the analog global. The hysteresis
feature can also be enabled for the input buffer of the SIO, which
increases noise immunity for the comparator.
6.4.14 Hot Swap
an external device could run from 5 V. Note that the SIO pin’s VIH
and VIL levels are determined by the associated VDDIO supply
pin. The SIO pin must be in one of the following modes: 0 (high
impedance analog), 1 (high impedance digital), or 4 (open drain
drives low). See Figure 6-10 for details. Absolute maximum
ratings for the device must be observed for all I/O pins.
6.4.16 Reset Configuration
While reset is active all I/Os are reset to and held in the High
Impedance Analog state. After reset is released, the state can be
reprogrammed on a port-by-port basis to pull-down or pull-up. To
ensure correct reset operation, the port reset configuration data
is stored in special nonvolatile registers. The stored reset data is
automatically transferred to the port reset configuration registers
at reset release.
This section applies only to SIO pins. SIO pins support ‘hot swap’
capability to plug into an application without loading the signals
that are connected to the SIO pins even when no power is
applied to the PSoC device. This allows the unpowered PSoC to
maintain a high impedance load to the external device while also
preventing the PSoC from being powered through a SIO pin’s
protection diode.
6.4.17 Low-Power Functionality
Powering the device up or down while connected to an
operational I2C bus may cause transient states on the SIO pins.
The overall I2C bus design should take this into account.
Some pins on the device include additional special functionality
in addition to their GPIO or SIO functionality. The specific special
function pins are listed in Pinouts on page 5. The special features
are:
 Digital
 4- to 25-MHz crystal oscillator
 32.768-kHz crystal oscillator
2
 Wake from sleep on I C address match. Any pin can be used
for I2C if wake from sleep is not required.
 JTAG interface pins
 SWD interface pins
 SWV interface pins
 External reset
 Analog
 High current IDAC outputs
 External reference inputs
6.4.15 Over Voltage Tolerance
All I/O pins provide an over voltage tolerance feature at any
operating VDD.
 There are no current limitations for the SIO pins as they present a
high impedance load to the external circuit where VDDIO < VIN <
5.5 V.
 The GPIO pins must be limited to 100 µA using a current limiting
resistor. GPIO pins clamp the pin voltage to approximately one
diode above the VDDIO supply where VDDIO < VIN < VDDA.
 In case of a GPIO pin configured for analog input/output, the
analog voltage on the pin must not exceed the VDDIO supply
voltage to which the GPIO belongs.
A common application for this feature is connection to a bus such
as I2C where different devices are running from different supply
voltages. In the I2C case, the PSoC chip is configured into the
Open Drain, Drives Low mode for the SIO pin. This allows an
external pull-up to pull the I2C bus voltage above the PSoC pin
supply. For example, the PSoC chip could operate at 1.8 V, and
Document Number: 001-58402 Rev. *G
In all low-power modes the I/O pins retain their state until the part
is awakened and changed or reset. To awaken the part, use a
pin interrupt, because the port interrupt logic continues to
function in all low-power modes.
6.4.18 Special Pin Functionality
6.4.19 JTAG Boundary Scan
The device supports standard JTAG boundary scan chains on all
I/O pins for board level test.
Page 39 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
7. Digital Subsystem
7.1 Example Peripherals
The digital programmable system creates application specific
combinations of both standard and advanced digital peripherals
and custom logic functions. These peripherals and logic are then
interconnected to each other and to any pin on the device,
providing a high level of design flexibility and IP security.
The features of the digital programmable system are outlined
here to provide an overview of capabilities and architecture. You
do not need to interact directly with the programmable digital
system at the hardware and register level. PSoC Creator
provides a high level schematic capture graphical interface to
automatically place and route resources similar to PLDs.
The main components of the digital programmable system are:
 UDB – These form the core functionality of the digital
programmable system. UDBs are a collection of uncommitted
logic (PLD) and structural logic (Datapath) optimized to create
all common embedded peripherals and customized
functionality that are application or design specific.
 Universal digital block array – UDB blocks are arrayed within
a matrix of programmable interconnect. The UDB array
structure is homogeneous and allows for flexible mapping of
digital functions onto the array. The array supports extensive
and flexible routing interconnects between UDBs and the
Digital System Interconnect.
 Digital system interconnect (DSI) – Digital signals from UDBs,
fixed function peripherals, I/O pins, interrupts, DMA, and other
system core signals are attached to the digital system
interconnect to implement full featured device connectivity. The
DSI allows any digital function to any pin or other feature
routability when used with the universal digital block array.
Figure 7-1. CY8C32 Digital Programmable Architecture
IO Port
UDB Array
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
 Communications
I2C
UART
 SPI


 Functions
EMIF
PWMs
 Timers
 Counters


 Logic
NOT
OR
 XOR
 AND
7.1.2 Example Analog Components
 ADC

Delta-sigma
 DACs
DSI Routing Interface
Digital Core System
and Fixed Function Peripherals
The following is a sample of the digital components available in
PSoC Creator for the CY8C32 family. The exact amount of
hardware resources (UDBs, routing, RAM, flash) used by a
component varies with the features selected in PSoC Creator for
the component.
The following is a sample of the analog components available in
PSoC Creator for the CY8C32 family. The exact amount of
hardware resources (routing, RAM, flash) used by a component
varies with the features selected in PSoC Creator for the
component.
IO Port
IO Port
IO Port
UDB
7.1.1 Example Digital Components

UDB Array
UDB
The number of components available through PSoC Creator is
too numerous to list in the data sheet, and the list is always
growing. An example of a component available for use in
CY8C32 family, but, not explicitly called out in this data sheet is
the UART component.

Digital Core System
and Fixed Function Peripherals
DSI Routing Interface
The flexibility of the CY8C32 family’s UDBs which allow the user
to create a wide range of components (peripherals). The most
common peripherals were built and characterized by Cypress
and are shown in the PSoC Creator component catalog,
however, users may also create their own custom components
using PSoC Creator. Using PSoC Creator, users may also create
their own components for reuse within their organization, for
example sensor interfaces, proprietary algorithms, and display
interfaces.
Current
Voltage
 PWM
 Comparators


7.1.3 Example System Function Components
The following is a sample of the system function components
available in PSoC Creator for the CY8C32 family. The exact
amount of hardware resources (UDBs, routing, RAM, flash) used
Document Number: 001-58402 Rev. *G
Page 40 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
7.1.4 Designing with PSoC Creator
PSoC device. It is populated with an impressive selection of
content; from simple primitives such as logic gates and device
registers, through the digital timers, counters and PWMs, plus
analog components such as ADC, and DACs, and
communication protocols, such as I2C, and USB. See Example
Peripherals on page 40 for more details about available
peripherals. All content is fully characterized and carefully
documented in data sheets with code examples, AC/DC
specifications, and user code ready APIs.
7.1.4.1 More Than a Typical IDE
7.1.4.3 Design Reuse
by a component varies with the features selected in PSoC
Creator for the component.
 CapSense
 LCD drive
 LCD control
A successful design tool allows for the rapid development and
deployment of both simple and complex designs. It reduces or
eliminates any learning curve. It makes the integration of a new
design into the production stream straightforward.
PSoC Creator is that design tool.
PSoC Creator is a full featured Integrated Development
Environment (IDE) for hardware and software design. It is
optimized specifically for PSoC devices and combines a modern,
powerful software development platform with a sophisticated
graphical design tool. This unique combination of tools makes
PSoC Creator the most flexible embedded design platform
available.
Graphical design entry simplifies the task of configuring a
particular part. You can select the required functionality from an
extensive catalog of components and place it in your design. All
components are parameterized and have an editor dialog that
allows you to tailor functionality to your needs.
PSoC Creator automatically configures clocks and routes the I/O
to the selected pins and then generates APIs to give the
application complete control over the hardware. Changing the
PSoC device configuration is as simple as adding a new
component, setting its parameters, and rebuilding the project.
At any stage of development you are free to change the
hardware configuration and even the target processor. To
retarget your application (hardware and software) to new
devices, even from 8- to 32-bit families, just select the new
device and rebuild.
You also have the ability to change the C compiler and evaluate
an alternative. Components are designed for portability and are
validated against all devices, from all families, and against all
supported tool chains. Switching compilers is as easy as editing
the from the project options and rebuilding the application with
no errors from the generated APIs or boot code.
7.1.4.2 Component Catalog
The symbol editor gives you the ability to develop reusable
components that can significantly reduce future design time. Just
draw a symbol and associate that symbol with your proven
design. PSoC Creator allows for the placement of the new
symbol anywhere in the component catalog along with the
content provided by Cypress. You can then reuse your content
as many times as you want, and in any number of projects,
without ever having to revisit the details of the implementation.
7.1.4.4 Software Development
Anchoring the tool is a modern, highly customizable user
interface. It includes project management and integrated editors
for C and assembler source code, as well the design entry tools.
Project build control leverages compiler technology from top
commercial vendors such as ARM® Limited, Keil™, and
CodeSourcery (GNU). Free versions of Keil C51 and GNU C
Compiler (GCC) for ARM, with no restrictions on code size or end
product distribution, are included with the tool distribution.
Upgrading to more optimizing compilers is a snap with support
for the professional Keil C51 product and ARM RealView™
compiler.
7.1.4.5 Nonintrusive Debugging
With JTAG (4-wire) and SWD (2-wire) debug connectivity
available on all devices, the PSoC Creator debugger offers full
control over the target device with minimum intrusion.
Breakpoints and code execution commands are all readily
available from toolbar buttons and an impressive lineup of
windows—register, locals, watch, call stack, memory and
peripherals—make for an unparalleled level of visibility into the
system.
PSoC Creator contains all the tools necessary to complete a
design, and then to maintain and extend that design for years to
come. All steps of the design flow are carefully integrated and
optimized for ease-of-use and to maximize productivity.
The component catalog is a repository of reusable design
elements that select device functionality and customize your
Document Number: 001-58402 Rev. *G
Page 41 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
7.2 Universal Digital Block
 Status and control module – The primary role of this block is to
The UDB represents an evolutionary step to the next generation
of PSoC embedded digital peripheral functionality. The
architecture in first generation PSoC digital blocks provides
coarse programmability in which a few fixed functions with a
small number of options are available. The new UDB
architecture is the optimal balance between configuration
granularity and efficient implementation. A cornerstone of this
approach is to provide the ability to customize the devices digital
operation to match application requirements.
The primary purpose of the PLD blocks is to implement logic
expressions, state machines, sequencers, lookup tables, and
decoders. In the simplest use model, consider the PLD blocks as
a standalone resource onto which general purpose RTL is
synthesized and mapped. The more common and efficient use
model is to create digital functions from a combination of PLD
and datapath blocks, where the PLD implements only the
random logic and state portion of the function while the datapath
(ALU) implements the more structured elements.
Figure 7-3. PLD 12C4 Structure
PT3
PT4
PT5
PT6
PT7
Clock
and Reset
Control
PLD
12C4
(8 PTs)
PLD
12C4
(8 PTs)
7.2.1 PLD Module
PT2
PLD
Chaining
and reset selection and control.
PT1
Figure 7-2. UDB Block Diagram
 Clock and reset module – This block provides the UDB clocks
PT0
To achieve this, UDBs consist of a combination of uncommitted
logic (PLD), structured logic (Datapath), and a flexible routing
scheme to provide interconnect between these elements, I/O
connections, and other peripherals. UDB functionality ranges
from simple self contained functions that are implemented in one
UDB, or even a portion of a UDB (unused resources are
available for other functions), to more complex functions that
require multiple UDBs. Examples of basic functions are timers,
counters, CRC generators, PWMs, dead band generators, and
communications functions, such as UARTs, SPI, and I2C. Also,
the PLD blocks and connectivity provide full featured general
purpose programmable logic within the limits of the available
resources.
provide a way for CPU firmware to interact and synchronize
with UDB operation.
IN0
TC
TC
TC
TC
TC
TC
TC
TC
IN1
TC
TC
TC
TC
TC
TC
TC
TC
IN2
TC
TC
TC
TC
TC
TC
TC
TC
IN3
TC
TC
TC
TC
TC
TC
TC
TC
IN4
TC
TC
TC
TC
TC
TC
TC
TC
IN5
TC
TC
TC
TC
TC
TC
TC
TC
IN6
TC
TC
TC
TC
TC
TC
TC
TC
IN7
TC
TC
TC
TC
TC
TC
TC
TC
IN8
TC
TC
TC
TC
TC
TC
TC
TC
IN9
TC
TC
TC
TC
TC
TC
TC
TC
IN10
TC
TC
TC
TC
TC
TC
TC
TC
IN11
TC
TC
TC
TC
TC
TC
TC
TC
AND
Array
Carry In
Status and
Control
Datapath
Datapath
Chaining
Routing Channel
The main component blocks of the UDB are:
 PLD blocks – There are two small PLDs per UDB. These blocks
take inputs from the routing array and form registered or
combinational sum-of-products logic. PLDs are used to
implement state machines, state bits, and combinational logic
equations. PLD configuration is automatically generated from
graphical primitives.
 Datapath module – This 8-bit wide datapath contains structured
logic to implement a dynamically configurable ALU, a variety
of compare configurations and condition generation. This block
also contains input/output FIFOs, which are the primary parallel
data interface between the CPU/DMA system and the UDB.
Document Number: 001-58402 Rev. *G
T
T
T
T
T
T
T
T
MC0
OUT0
T
T
T
T
T
T
T
T
MC1
OUT1
T
T
T
T
T
T
T
T
MC2
OUT2
T
T
T
T
T
T
T
T
MC3
OUT3
OR
Array
Carry Out
One 12C4 PLD block is shown in Figure 7-3. This PLD has 12
inputs, which feed across eight product terms. Each product term
(AND function) can be from 1 to 12 inputs wide, and in a given
product term, the true (T) or complement (C) of each input can
be selected. The product terms are summed (OR function) to
create the PLD outputs. A sum can be from 1 to 8 product terms
wide. The 'C' in 12C4 indicates that the width of the OR gate (in
this case 8) is constant across all outputs (rather than variable
as in a 22V10 device). This PLA like structure gives maximum
flexibility and insures that all inputs and outputs are permutable
for ease of allocation by the software tools. There are two 12C4
PLDs in each UDB.
Page 42 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
7.2.2 Datapath Module
The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is
optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band
generators and many others.
Figure 7-4. Datapath Top Level
PHUB System Bus
R/W Access to All
Registers
F1
FIFOs
F0
A0
A1
D0
D1
D1
Data Registers
D0
To/From
Previous
Datapath
A1
Conditions: 2 Compares,
2 Zero Detect, 2 Ones
Detect Overflow Detect
Datapath Control
6
Control Store RAM
8 Word X 16 Bit
Input from
Programmable
Routing
Input
Muxes
Chaining
Output
Muxes
6
Output to
Programmable
Routing
To/From
Next
Datapath
Accumulators
A0
PI
Parallel Input/Output
(to/from Programmable Routing)
PO
ALU
Shift
Mask
7.2.2.1 Working Registers
7.2.2.2 Dynamic Datapath Configuration RAM
The datapath contains six primary working registers, which are
accessed by CPU firmware or DMA during normal operation.
Dynamic configuration is the ability to change the datapath
function and internal configuration on a cycle-by-cycle basis,
under sequencer control. This is implemented using the 8-word
× 16-bit configuration RAM, which stores eight unique 16-bit
wide configurations. The address input to this RAM controls the
sequence, and can be routed from any block connected to the
UDB routing matrix, most typically PLD logic, I/O pins, or from
the outputs of this or other datapath blocks.
Table 7-1. Working Datapath Registers
Name
Function
Description
A0 and A1 Accumulators
These are sources and sinks for
the ALU and also sources for the
compares.
D0 and D1 Data Registers
These are sources for the ALU
and sources for the compares.
ALU
F0 and F1 FIFOs
These are the primary interface
to the system bus. They can be a
data source for the data registers
and accumulators or they can
capture data from the
accumulators or ALU. Each FIFO
is four bytes deep.
 Increment
The ALU performs eight general purpose functions. They are:
 Decrement
 Add
 Subtract
 Logical AND
 Logical OR
 Logical XOR
 Pass, used to pass a value through the ALU to the shift register,
mask, or another UDB register.
Document Number: 001-58402 Rev. *G
Page 43 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Independent of the ALU operation, these functions are available:
7.2.2.7 Chaining
 Shift left
 Shift right
The datapath can be configured to chain conditions and signals
such as carries and shift data with neighboring datapaths to
create higher precision arithmetic, shift, CRC/PRS functions.
 Nibble swap
7.2.2.8 Time Multiplexing
 Bitwise OR mask
In applications that are over sampled, or do not need high clock
rates, the single ALU block in the datapath can be efficiently
shared with two sets of registers and condition generators. Carry
and shift out data from the ALU are registered and can be
selected as inputs in subsequent cycles. This provides support
for 16-bit functions in one (8-bit) datapath.
7.2.2.3 Conditionals
Each datapath has two compares, with bit masking options.
Compare operands include the two accumulators and the two
data registers in a variety of configurations. Other conditions
include zero detect, all ones detect, and overflow. These
conditions are the primary datapath outputs, a selection of which
can be driven out to the UDB routing matrix. Conditional
computation can use the built in chaining to neighboring UDBs
to operate on wider data widths without the need to use routing
resources.
7.2.2.4 Variable MSB
The most significant bit of an arithmetic and shift function can be
programmatically specified. This supports variable width CRC
and PRS functions, and in conjunction with ALU output masking,
can implement arbitrary width timers, counters and shift blocks.
7.2.2.5 Built in CRC/PRS
The datapath has built-in support for single cycle CRC
computation and PRS generation of arbitrary width and arbitrary
polynomial. CRC/PRS functions longer than 8 bits may be
implemented in conjunction with PLD logic, or built in chaining
may be use to extend the function into neighboring UDBs.
7.2.2.9 Datapath I/O
There are six inputs and six outputs that connect the datapath to
the routing matrix. Inputs from the routing provide the
configuration for the datapath operation to perform in each cycle,
and the serial data inputs. Inputs can be routed from other UDB
blocks, other device peripherals, device I/O pins, and so on. The
outputs to the routing can be selected from the generated
conditions, and the serial data outputs. Outputs can be routed to
other UDB blocks, device peripherals, interrupt and DMA
controller, I/O pins, and so on.
7.2.3 Status and Control Module
The primary purpose of this circuitry is to coordinate CPU
firmware interaction with internal UDB operation.
Figure 7-6. Status and Control Registers
System Bus
7.2.2.6 Input/Output FIFOs
Each datapath contains two four-byte deep FIFOs, which can be
independently configured as an input buffer (system bus writes
to the FIFO, datapath internal reads the FIFO), or an output
buffer (datapath internal writes to the FIFO, the system bus reads
from the FIFO). The FIFOs generate status that are selectable
as datapath outputs and can therefore be driven to the routing,
to interact with sequencers, interrupts, or DMA.
Figure 7-5. Example FIFO Configurations
System Bus
System Bus
F0
D0/D1
A0/A1/ALU
A0/A1/ALU
A0/A1/ALU
F1
F0
F1
System Bus
System Bus
TX/RX
Dual Capture
Document Number: 001-58402 Rev. *G
F0
F1
D0
A0
D1
A1
Dual Buffer
8-bit Status Register
(Read Only)
8-bit Control Register
(Write/Read)
Routing Channel
The bits of the control register, which may be written to by the
system bus, are used to drive into the routing matrix, and thus
provide firmware with the opportunity to control the state of UDB
processing. The status register is read-only and it allows internal
UDB state to be read out onto the system bus directly from
internal routing. This allows firmware to monitor the state of UDB
processing. Each bit of these registers has programmable
connections to the routing matrix and routing connections are
made depending on the requirements of the application.
7.2.3.1 Usage Examples
As an example of control input, a bit in the control register can
be allocated as a function enable bit. There are multiple ways to
enable a function. In one method the control bit output would be
routed to the clock control block in one or more UDBs and serve
as a clock enable for the selected UDB blocks. A status example
is a case where a PLD or datapath block generated a condition,
such as a “compare true” condition that is captured and latched
by the status register and then read (and cleared) by CPU
firmware.
Page 44 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Each subcomponent block of a UDB including the two PLDs, the
datapath, and Status and Control, has a clock selection and
control block. This promotes a fine granularity with respect to
allocating clocking resources to UDB component blocks and
allows unused UDB resources to be used by other functions for
maximum system efficiency.
7.3 UDB Array Description
Figure 7-7 shows an example of a 16 UDB array. In addition to
the array core, there are a DSI routing interfaces at the top and
bottom of the array. Other interfaces that are not explicitly shown
include the system interfaces for bus and clock distribution. The
UDB array includes multiple horizontal and vertical routing
channels each comprised of 96 wires. The wire connections to
UDBs, at horizontal/vertical intersection and at the DSI interface
are highly permutable providing efficient automatic routing in
PSoC Creator. Additionally the routing allows wire by wire
segmentation along the vertical and horizontal routing to further
increase routing flexibility and capability.
An example of this is the 8-bit timer in the upper left corner of the
array. This function only requires one datapath in the UDB, and
therefore the PLD resources may be allocated to another
function. A function such as a Quadrature Decoder may require
more PLD logic than one UDB can supply and in this case can
utilize the unused PLD blocks in the 8-bit Timer UDB.
Programmable resources in the UDB array are generally
homogeneous so functions can be mapped to arbitrary
boundaries in the array.
Figure 7-8. Function Mapping Example in a Bank of UDBs
8-Bit
Timer
Quadrature Decoder
UDB
UDB
HV
A
HV
A
HV
B
UDB
UDB
UDB
HV
A
HV
B
UDB
8-Bit
Timer Logic
UDB
UDB
UDB
UDB
HV
A
HV
B
UDB
UDB
12-Bit SPI
UDB
HV
B
16-Bit PYRS
8-Bit SPI
I2C Slave
System Connections
16-Bit
PWM
HV
B
UDB
UDB
Figure 7-7. Digital System Interface Structure
Sequencer
7.2.3.2 Clock Generation
HV
A
HV
B
HV
A
UDB
Logic
HV
A
HV
B
HV
A
HV
B
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UART
UDB
UDB
12-Bit PWM
7.4 DSI Routing Interface Description
HV
B
UDB
HV
A
UDB
HV
A
HV
B
UDB
HV
B
HV
A
The DSI routing interface is a continuation of the horizontal and
vertical routing channels at the top and bottom of the UDB array
core. It provides general purpose programmable routing
between device peripherals, including UDBs, I/Os, analog
peripherals, interrupts, DMA and fixed function peripherals.
HV
B
Figure 7-9 illustrates the concept of the digital system
interconnect, which connects the UDB array routing matrix with
other device peripherals. Any digital core or fixed function
peripheral that needs programmable routing is connected to this
interface.
UDB
HV
A
System Connections
Signals in this category include:
 Interrupt requests from all digital peripherals in the system.
7.3.1 UDB Array Programmable Resources
 DMA requests from all digital peripherals in the system.
Figure 7-8 shows an example of how functions are mapped into
a bank of 16 UDBs. The primary programmable resources of the
UDB are two PLDs, one datapath and one status/control register.
These resources are allocated independently, because they
have independently selectable clocks, and therefore unused
blocks are allocated to other unrelated functions.
 Digital peripheral data signals that need flexible routing to I/Os.
 Digital peripheral data signals that need connections to UDBs.
 Connections to the interrupt and DMA controllers.
 Connection to I/O pins.
 Connection to analog system digital signals.
Document Number: 001-58402 Rev. *G
Page 45 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 7-9. Digital System Interconnect
Timer
Counters
CAN
Interrupt
Controller
I2C
DMA
Controller
IO Port
Pins
Global
Clocks
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the master clock (see Figure 6-1). Normally all inputs from pins
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-11. I/O Pin Synchronization Routing
Digital System Routing I/F
DO
UDB ARRAY
DI
Digital System Routing I/F
Figure 7-12. I/O Pin Output Connectivity
8 IO Data Output Connections from the
UDB Array Digital System Interface
Global
Clocks
IO Port
Pins
EMIF
Del-Sig
SAR
DAC
DACs
Comparators
Interrupt and DMA routing is very flexible in the CY8C32
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design. Figure 7-10 shows the structure of the IDMUX
(Interrupt/DMA Multiplexer).
DO
PIN 0
DO
PIN1
DO
PIN2
Fixed Function IRQs
0
1
IRQs
UDB Array
2
Edge
Detect
Interrupt
Controller
DO
PIN4
DO
PIN5
DO
PIN6
DO
PIN7
Port i
Figure 7-10. Interrupt and DMA Processing in the IDMUX
Interrupt and DMA Processing in IDMUX
DO
PIN3
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
Figure 7-13. I/O Pin Output Enable Connectivity
3
DRQs
DMA termout (IRQs)
4 IO Control Signal Connections from
UDB Array Digital System Interface
0
Fixed Function DRQs
1
Edge
Detect
DMA
Controller
2
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
Document Number: 001-58402 Rev. *G
OE
PIN 0
OE
PIN1
OE
PIN2
OE
PIN3
OE
PIN4
OE
PIN5
OE
PIN6
OE
PIN7
Port i
Page 46 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
7.5 USB
7.6 Timers, Counters, and PWMs
PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0
transceiver supporting all four USB transfer types: control,
interrupt, bulk, and isochronous. PSoC Creator provides full
configuration support. USB interfaces to hosts through two
dedicated USBIO pins, which are detailed in the “I/O System and
Routing” section on page 33.
The timer/counter/PWM peripheral is a 16-bit dedicated
peripheral providing three of the most common embedded
peripheral features. As almost all embedded systems use some
combination of timers, counters, and PWMs. Four of them have
been included on this PSoC device family. Additional and more
advanced functionality timers, counters, and PWMs can also be
instantiated in UDBs as required. PSoC Creator allows you to
choose the timer, counter, and PWM features that they require.
The tool set utilizes the most optimal resources available.
USB includes the following features:
 Eight unidirectional data endpoints
 One bidirectional control endpoint 0 (EP0)
 Shared 512-byte buffer for the eight data endpoints
 Dedicated 8-byte buffer for EP0
 Three memory modes
Manual memory management with no DMA access
Manual memory management with manual DMA access
 Automatic memory management with automatic DMA
access


 Internal 3.3-V regulator for transceiver
 Internal 48-MHz main oscillator mode that auto locks to USB
bus clock, requiring no external crystal for USB (USB equipped
parts only)
 Interrupts on bus and each endpoint event, with device wakeup
 USB reset, suspend, and resume operations
 Bus-powered and self-powered modes
Figure 7-14. USB
System Bus
Arbiter
512 X 8
SRAM
D+
SIE
(Serial Interface
Engine)
USB
I/O
Interrupts
48 MHz
IMO
Document Number: 001-58402 Rev. *G
External 22 
Resistors
The timer/counter/PWM peripheral can select from multiple clock
sources, with input and output signals connected through the
DSI routing. DSI routing allows input and output connections to
any device pin and any internal digital signal accessible through
the DSI. Each of the four instances has a compare output,
terminal count output (optional complementary compare output),
and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
Timer/Counter/PWM features include:
 16-bit Timer/Counter/PWM (down count only)
 Selectable clock source
 PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
 Period reload on start, reset, and terminal count
 Interrupt on terminal count, compare true, or capture
 Dynamic counter reads
 Timer capture mode
 Count while enable signal is asserted mode
 Free run mode
 One Shot mode (stop at end of period)
 Complementary PWM outputs with deadband
 PWM output kill
Figure 7-15. Timer/Counter/PWM
D–
Clock
Reset
Enable
Capture
Kill
Timer / Counter /
PWM 16-bit
IRQ
TC / Compare!
Compare
Page 47 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
7.7 I2C
The I2C peripheral provides a synchronous two wire interface
designed to interface the PSoC device with a two wire I2C serial
communication bus. It is compatible[11] with I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O may be implemented with GPIO or SIO in open-drain modes.
Additional I2C interfaces can be instantiated using Universal
Digital Blocks (UDBs) in PSoC Creator, as required.
To eliminate the need for excessive CPU intervention and
overhead, I2C specific support is provided for status detection
and generation of framing bits. I2C operates as a slave, a master,
or multimaster (Slave and Master).[12]. In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I2C interfaces through DSI
routing and allows direct connections to any GPIO or SIO pins.
I2C provides hardware address detect of a 7-bit address without
CPU intervention. Additionally the device can wake from
low-power modes on a 7-bit hardware address match. If wakeup
functionality is required, I2C pin connections are limited to the
two special sets of SIO pins.
I2C features include:
 Slave and master, transmitter, and receiver operation
 Byte processing for low CPU overhead
 Interrupt or polling CPU interface
 Support for bus speeds up to 1 Mbps
 7 or 10-bit addressing (10-bit addressing requires firmware
support)
 SMBus operation (through firmware support - SMBus
supported in hardware in UDBs)
 7-bit hardware address compare
 Wake from low-power modes on address match
 Glitch filtering (active and alternate-active modes only)
Data transfers follow the format shown in Figure 7-16. After the
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a ‘zero’ indicates a transmission (WRITE), a ‘one’
indicates a request for data (READ). A data transfer is always
terminated by a STOP condition (P) generated by the master.
Figure 7-16. I2C Complete Transfer Timing
SDA
1-7
SCL
START
Condition
ADDRESS
8
9
R/W
ACK
1-7
8
DATA
9
ACK
1-7
8
DATA
9
ACK
STOP
Condition
Notes
11. The I2C peripheral is non-compliant with the NXP I2C specification in the following areas: analog glitch filter, I/O VOL/IOL, I/O hysteresis. The I2C Block has a digital
glitch filter (not available in sleep mode). The Fast-mode minimum fall-time specification can be met by setting the I/Os to slow speed mode. See the I/O Electrical
Specifications in “Inputs and Outputs” section on page 71 for details.
12. Fixed-block I2C does not support undefined bus conditions, nor does it support Repeated Start in Slave mode. These conditions should be avoided, or the UDB-based
I2C component should be used instead.
Document Number: 001-58402 Rev. *G
Page 48 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
8. Analog Subsystem
 High resolution delta-sigma ADC.
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
 One 8-bit DACs that provide either voltage or current output.
 Two comparators with optional connection to configurable LUT
outputs.
 CapSense subsystem to enable capacitive touch sensing.
 Precision reference for generating an accurate analog voltage
for internal analog blocks.
 Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses.
Figure 8-1. Analog Subsystem Block Diagram
DelSig
ADC
Precision
Reference
GPIO
Port
A
N
A
L
O
G
A
N
A
L
O
G
R
O
U
T
I
N
G
R
O
U
T
I
N
G
Comparators
CMP
CMP
GPIO
Port
CapSense Subsystem
Analog
Interface
DSI
Array
Document Number: 001-58402 Rev. *G
Clock
Distribution
Config &
Status
Registers
AHB
PHUB
CPU
Decimator
Page 49 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
The PSoC Creator software program provides a user friendly
interface to configure the analog connections between the GPIO
and various analog resources and connections from one analog
resource to another. PSoC Creator also provides component
libraries that allow you to configure the various analog blocks to
perform application specific function. The tool also generates
API interface libraries that allow you to write firmware that allows
the communication between the analog peripheral and
CPU/Memory.
8.1 Analog Routing
The CY8C32 family of devices has a flexible analog routing
architecture that provides the capability to connect GPIOs and
different analog blocks, and also route signals between different
analog blocks. One of the strong points of this flexible routing
architecture is that it allows dynamic routing of input and output
connections to the different analog blocks.
For information on how to make pin selections for optimal analog
routing, refer to the application note, AN58304 - PSoC® 3 and
PSoC® 5 - Pin Selection for Analog Designs.
Document Number: 001-58402 Rev. *G
8.1.1 Features
 Flexible, configurable analog routing architecture
 16 analog globals (AG) and two analog mux buses
(AMUXBUS) to connect GPIOs and the analog blocks
 Each GPIO is connected to one analog global and one analog
mux bus
 Eight analog local buses (abus) to route signals between the
different analog blocks
 Multiplexers and switches for input and output selection of the
analog blocks
8.1.2 Functional Description
Analog globals (AGs) and analog mux buses (AMUXBUS)
provide analog connectivity between GPIOs and the various
analog blocks. There are 16 AGs in the CY8C32 family. The
analog routing architecture is divided into four quadrants as
shown in Figure 8-2. Each quadrant has four analog globals
(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is
connected to the corresponding AG through an analog switch.
The analog mux bus is a shared routing resource that connects
to every GPIO through an analog switch. There are two
AMUXBUS routes in CY8C32, one in the left half (AMUXBUSL)
and one in the right half (AMUXBUSR), as shown in Figure 8-2
on page 51.
Page 50 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 8-2. CY8C32 Analog Interconnect
*
*
*
*
*
44
GPIO
P3[5]
GPIO
P3[4]
GPIO
P3[3]
GPIO
P3[2]
GPIO
P3[1]
GPIO
P3[0]
GPXT
*P15[1]
GPXT
*P15[0]
3210 76543210
*
in0
out0
*
+ comp0
-
comp1
ExVrefR
+
1.024V
0.256V
refbufr
out
ref
in
1.024V
1.2V
Vssa
Vssa
v0
DAC0
i0
VIDAC
1.024V
*
Vssd
ABUSR0
ABUSR1
ABUSR2
ABUSR3
ABUSL0
ABUSL1
ABUSL2
ABUSL3
*
Vssio
AGR[4]
AMUXBUSR
CAPSENSE
out
ref
in refbufl
1.024V
1.2V
AGR[7]
AGR[6]
AGR[5]
vda, vda/2
Vccd
Vssd
Vddd
USB IO
USB IO
* P15[6]
+ dsm0
vpwra,
vpwra/2
0.8V
DSM
qtz_ref
Vssa
refs
0.7V
1.2V
ExVrefL
vda,
vda/4
AMUXBUSL
ExVrefR
01 23456 7 0123
3210 76543210
ANALOG ANALOG
GLOBALS
BUS
TS
ADC
AGR[3]
AGR[2]
AGR[1]
AGL[1]
AGL[2]
AGL[3]
:
AMUXBUSR
ANALOG ANALOG
BUS
GLOBALS
VBE
VSS ref
LPF
AGR[3]
AGL[3]
AGL[2]
AGL[1]
AGL[0]
AMUXBUSL
Vssd
XRES_N
*
Vio1
*
GPIO
P5[0]
GPIO
P5[1]
GPIO
P5[2]
GPIO
P5[3]
GPIO
P1[0]
GPIO
P1[1]
GPIO
P1[2]
GPIO
P1[3]
GPIO
P1[4]
GPIO
P1[5]
GPIO
P2[5]
GPIO
P2[6]
GPIO
P2[7]
SIO
P12[4]
SIO
P12[5]
GPIO
P6[4]
GPIO
P6[5]
GPIO
P6[6]
GPIO
P6[7]
*
Large (lower z)
*
Size
Small (higher z)
*
13
*
*
*
AGR[2]
AGR[1]
AGR[0]
AMUXBUSR
*
*
AGR[0]
AMUXBUSR
1.024V
AMUXBUSL
AGL[0]
GPIO
P5[7]
GPIO
P5[6]
GPIO
P5[5]
GPIO
P5[4]
SIO
P12[7]
SIO
P12[6]
GPIO
*P1[7]
GPIO
*P1[6]
*
*
Mux Group
Connection
Vssio
* P15[7]
Lower left
Quadrant
Switch Group
Vccd
Vusb
*
GPIO
P6[0]
GPIO
P6[1]
GPIO
P6[2]
GPIO
P6[3]
GPIO
P15[4]
GPIO
P15[5]
GPIO
P2[0]
GPIO
P2[1]
GPIO
P2[2]
GPIO
P2[3] *
GPIO
P2[4] *
Vio2
in1
out1
COMPARATOR
1.024V
GPIO
P4[2]
GPIO
P4[3]
GPIO
P4[4]
GPIO
P4[5]
GPIO
P4[6]
GPIO
P4[7]
Vddd
LPF
*
*
*
01 2 3 4 56 7 0123
*
*
ExVrefL2
*
*
*
AGL[6]
AGL[7]
*
*
*
AGR[6]
AGR[7]
AGL[7]
AGL[4]
AGL[5]
Upper Right
Quadrant
AGR[4]
AGR[5]
AGL[4]
AGL[5]
AGL[6]
ExVrefL
ExVrefL1
*
Vio3
GPIO
P3[6]
GPIO
P3[7]
SIO
P12[0]
SIO
P12[1]
GPIO
P15[2]
GPIO
P15[3]
AMUXBUSL
Vssd
Vcca
Vssa
Vdda
Vio0
AMUXBUSR
AMUXBUSL
*
*
GPIO
P0[4]
GPIO
P0[5]
GPIO
P0[6]
GPIO
P0[7]
SIO
P12[2]
SIO
P12[3]
GPIO
P4[0]
GPIO
P4[1]
GPIO
P0[0]
GPIO
P0[1]
GPIO
P0[2]
GPIO
P0[3]
Upper Left
Quadrant
Lower right
Quadrant
Notes:
* Denotes pins on all packages
LCD signals are not shown.
To preserve detail of this figure, this figure is best viewed with a PDF display program or printed on a 11" × 17" paper.
Document Number: 001-58402 Rev. *G
Page 51 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Analog local buses (abus) are routing resources located within
the analog subsystem and are used to route signals between
different analog blocks. There are eight abus routes in CY8C32,
four in the left half (abusl [0:3]) and four in the right half (abusr
[0:3]) as shown in Figure 8-2. Using the abus saves the analog
globals and analog mux buses from being used for
interconnecting the analog blocks.
Multiplexers and switches exist on the various buses to direct
signals into and out of the analog blocks. A multiplexer can have
only one connection on at a time, whereas a switch can have
multiple connections on simultaneously. In Figure 8-2,
multiplexers are indicated by grayed ovals and switches are
indicated by transparent ovals.
block diagram is shown in Figure 8-4. The signal from the input
muxes is delivered to the delta-sigma modulator either directly or
through the input buffer. The delta-sigma modulator performs the
actual analog to digital conversion. The modulator over-samples
the input and generates a serial data stream output. This high
speed data stream is not useful for most applications without
some type of post processing, and so is passed to the decimator
through the Analog Interface block. The decimator converts the
high speed serial data stream into parallel ADC results. The
modulator/decimator frequency response is [(sin x)/x]4.
Figure 8-4. Delta-sigma ADC Block Diagram
Positive
Input Mux
8.2 Delta-sigma ADC
The CY8C32 device contains one delta-sigma ADC. This ADC
offers differential input, high resolution and excellent linearity,
making it a good ADC choice for both audio signal processing
and measurement applications. The converter's nominal
operation is 16 bits at 48 ksps. The ADC can be configured to
output 12-bit resolution at data rates of up to 187 sps. At a fixed
clock rate, resolution can be traded for faster data rates as
shown in Table 8-1 and Figure 8-3.
Table 8-1. Delta-sigma ADC Performance
Bits
Maximum Sample Rate
(sps)
SINAD (dB)
12
192 k
66
8
384 k
43
(Analog Routing)
Input
Buffer
Negative
Input Mux
Delta
Sigma
Modulator
Decimator
12 to 20 Bit
Result
EOC
SOC
Resolution and sample rate are controlled by the Decimator.
Data is pipelined in the decimator; the output is a function of the
last four samples. When the input multiplexer is switched, the
output data is not valid until after the fourth sample after the
switch.
8.2.2 Operational Modes
Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024 V
1,000,000
The ADC can be configured by the user to operate in one of three
modes: Single Sample, Multi Sample, or Continuous. All four
modes are started by either a write to the start bit in a control
register or an assertion of the Start of Conversion (SoC) signal.
When the conversion is complete, a status bit is set and the
output signal End of Conversion (EoC) asserts high and remains
high until the value is read by either the DMA controller or the
CPU.
8.2.2.1 Single Sample
In Single Sample mode, the ADC performs one sample
conversion on a trigger. In this mode, the ADC stays in standby
state waiting for the SoC signal to be asserted. When SoC is
signaled the ADC performs four successive conversions. The
first three conversions prime the decimator. The ADC result is
valid and available after the fourth conversion, at which time the
EoC signal is generated. To detect the end of conversion, the
system may poll a control register for status or configure the
external EoC signal to generate an interrupt or invoke a DMA
request. When the transfer is done the ADC reenters the standby
state where it stays until another SoC event.
Sample rates, sps
100,000
10,000
1,000
Continuous
Multi-Sample
8.2.2.2 Continuous
Resolution, bits
100
7
8
9
10
11
12
13
8.2.1 Functional Description
Continuous sample mode is used to take multiple successive
samples of a single input signal. Multiplexing multiple inputs
should not be done with this mode. There is a latency of three
conversion times before the first conversion result is available.
This is the time required to prime the decimator. After the first
result, successive conversions are available at the selected
sample rate.
The ADC connects and configures three basic components,
input buffer, delta-sigma modulator, and decimator. The basic
Document Number: 001-58402 Rev. *G
Page 52 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
8.2.2.3 Multi Sample
8.3 Comparators
Multi sample mode is similar to continuous mode except that the
ADC is reset between samples. This mode is useful when the
input is switched between multiple signals. The decimator is
re-primed between each sample so that previous samples do not
affect the current conversion. Upon completion of a sample, the
next sample is automatically initiated. The results can be
transferred using either firmware polling, interrupt, or DMA.
The CY8C32 family of devices contains two comparators in a
device. Comparators have these features:
8.2.3 Start of Conversion Input
 Comparator outputs can be routed to lookup tables to perform
 Input offset factory trimmed to less than 5 mV
 Rail-to-rail common mode input range (VSSA to VDDA)
 Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low-power
simple logic functions and then can also be routed to digital
blocks
The SoC signal is used to start an ADC conversion. A digital
clock or UDB output can be used to drive this input. It can be
used when the sampling period must be longer than the ADC
conversion time or when the ADC must be synchronized to other
hardware. This signal is optional and does not need to be
connected if ADC is running in a continuous mode.
 The positive input of the comparators may be optionally passed
through a low pass filter. Two filters are provided
 Comparator inputs can be connections to GPIO, and DAC
outputs
8.2.4 End of Conversion Output
8.3.1 Input and Output Interface
The EoC signal goes high at the end of each ADC conversion.
This signal may be used to trigger either an interrupt or DMA
request.
The positive and negative inputs to the comparators come from
the analog global buses, the analog mux line, the analog local
bus and precision reference through multiplexers. The output
from each comparator could be routed to any of the two input
LUTs. The output of that LUT is routed to the UDB DSI.
Figure 8-5. Analog Comparator
From
Analog
Routing
ANAIF
+
comp0
_
+
comp1
4
4
LUT0
4
4
4
LUT1
4
LUT2
4
_
From
Analog
Routing
4
LUT3
UDBs
Document Number: 001-58402 Rev. *G
Page 53 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
8.3.2 LUT
The CY8C32 family of devices contains four LUTs. The LUT is a
two input, one output lookup table that is driven by any one or
two of the comparators in the chip. The output of any LUT is
routed to the digital system interface of the UDB array. From the
digital system interface of the UDB array, these signals can be
connected to UDBs, DMA controller, I/O, or the interrupt
controller.
device to meet the required specifications. This is possible
because of the programmability inherent to PSoC devices.
Key features of the PSoC LCD segment system are:
 LCD panel direct driving
 Type A (standard) and Type B (low-power) waveform support
 Wide operating voltage range support (2 V to 5 V) for LCD
panels
The LUT control word written to a register sets the logic function
on the output. The available LUT functions and the associated
control word is shown in Table 8-2.
 Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels
Table 8-2. LUT Function vs. Program Word and Inputs
 Up to 62 total common and segment outputs
Control Word
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Output (A and B are LUT inputs)
FALSE (‘0’)
A AND B
A AND (NOT B)
A
(NOT A) AND B
B
A XOR B
A OR B
A NOR B
A XNOR B
NOT B
A OR (NOT B)
NOT A
(NOT A) OR B
A NAND B
TRUE (‘1’)
The opamp has three speed modes, slow, medium, and fast. The
slow mode consumes the least amount of quiescent power and
the fast mode consumes the most power. The inputs are able to
swing rail-to-rail. The output swing is capable of rail-to-rail
operation at low current output, within 50 mV of the rails. When
driving high current loads (about 25 mA) the output voltage may
only get within 500 mV of the rails.
 Internal bias voltage generation through internal resistor ladder
 Up to 1/16 multiplex for a maximum of 16 backplane/common
outputs
 Up to 62 front plane/segment outputs for direct drive
 Drives up to 736 total segments (16 backplane × 46 front plane)
 Up to 64 levels of software controlled contrast
 Ability to move display data from memory buffer to LCD driver
through DMA (without CPU intervention)
 Adjustable LCD refresh rate from 10 Hz to 150 Hz
 Ability to invert LCD display for negative image
 Three LCD driver drive modes, allowing power optimization
Figure 8-6. LCD System
UDB
LCD Driver
Block
DMA
8.4 LCD Direct Drive
The PSoC LCD driver system is a highly configurable peripheral
designed to allow PSoC to directly drive a broad range of LCD
glass. All voltages are generated on chip, eliminating the need
for external components. With a high multiplex ratio of up to 1/16,
the CY8C32 family LCD driver system can drive a maximum of
736 segments. The PSoC LCD driver module was also designed
with the conservative power budget of portable devices in mind,
enabling different LCD drive modes and power down modes to
conserve power.
PSoC Creator provides an LCD segment drive component. The
component wizard provides easy and flexible configuration of
LCD resources. You can specify pins for segments and
commons along with other options. The software configures the
Document Number: 001-58402 Rev. *G
LCD
DAC
Global
Clock
PIN
Display
RAM
PHUB
8.4.1 LCD Segment Pin Driver
Each GPIO pin contains an LCD driver circuit. The LCD driver
buffers the appropriate output of the LCD DAC to directly drive
the glass of the LCD. A register setting determines whether the
pin is a common or segment. The pin’s LCD driver then selects
one of the six bias voltages to drive the I/O pin, as appropriate
for the display data.
Page 54 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
8.4.2 Display Data Flow
The LCD segment driver system reads display data and
generates the proper output voltages to the LCD glass to
produce the desired image. Display data resides in a memory
buffer in the system SRAM. Each time you need to change the
common and segment driver voltages, the next set of pixel data
moves from the memory buffer into the Port Data Registers
through the DMA.
8.4.3 UDB and LCD Segment Control
A UDB is configured to generate the global LCD control signals
and clocking. This set of signals is routed to each LCD pin driver
through a set of dedicated LCD global routing channels. In
addition to generating the global LCD control signals, the UDB
also produces a DMA request to initiate the transfer of the next
frame of LCD data.
8.4.4 LCD DAC
The LCD DAC generates the contrast control and bias voltage
for the LCD system. The LCD DAC produces up to five LCD drive
voltages plus ground, based on the selected bias ratio. The bias
Document Number: 001-58402 Rev. *G
voltages are driven out to GPIO pins on a dedicated LCD bias
bus, as required.
8.5 CapSense
The CapSense system provides a versatile and efficient means
for measuring capacitance in applications such as touch sense
buttons, sliders, proximity detection, etc. The CapSense system
uses a configuration of system resources, including a few
hardware functions primarily targeted for CapSense. Specific
resource usage is detailed in the CapSense component in PSoC
Creator.
A capacitive sensing method using a Delta-sigma Modulator
(CSD) is used. It provides capacitance sensing using a switched
capacitor technique with a delta-sigma modulator to convert the
sensing current to a digital code.
8.6 Temp Sensor
Die temperature is used to establish programming parameters
for writing flash. Die temperature is measured using a dedicated
sensor based on a forward biased transistor. The temperature
sensor has its own auxiliary ADC.
Page 55 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
8.7 DAC
 High and low speed / power modes
The CY8C32 parts contain a Digital to Analog Convertor (DAC).
The DAC is 8-bit and can be configured for either voltage or
current output. The DACs support CapSense, power supply
regulation, and waveform generation. Each DAC has the
following features:
 8 Msps conversion rate for current output
 Adjustable voltage or current output in 255 steps
 Programmable step size (range selection)
 1 Msps conversion rate for voltage output
 Monotonic in nature
 Data and strobe inputs can be provided by the CPU or DMA,
or routed directly from the DSI
 Dedicated low-resistance output pin for high-current mode
 Eight bits of calibration to correct ± 25 percent of gain error
 Source and sink option for current output
Figure 8-7. DAC Block Diagram
I source Range 1x , 8x , 64x
Reference Source
Scaler
Vout
R
Iout
3R
I sink Range 1x , 8x , 64x
8.7.1 Current DAC
8.7.2 Voltage DAC
The current DAC (IDAC) can be configured for the ranges 0 to
31.875 µA, 0 to 255 µA, and 0 to 2.04 mA. The IDAC can be
configured to source or sink current.
For the voltage DAC (VDAC), the current DAC output is routed
through resistors. The two ranges available for the VDAC are 0
to 1.02 V and 0 to 4.08 V. In voltage mode any load connected
to the output of a DAC should be purely capacitive (the output of
the VDAC is not buffered).
Document Number: 001-58402 Rev. *G
Page 56 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
9. Programming, Debug Interfaces,
Resources
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
Three interfaces are available: JTAG, SWD, and SWV. JTAG and
SWD support all programming and debug features of the device.
JTAG also supports standard JTAG scan chains for board level
test and chaining multiple JTAG devices to a single JTAG
connection.
For more information on PSoC 3 Programming, refer to the
PSoC® 3 Device Programming Specifications.
Complete Debug on Chip (DoC) functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV
interfaces are fully compatible with industry standard third party
tools.
All DOC circuits are disabled by default and can only be enabled
in firmware. If not enabled, the only way to reenable them is to
erase the entire device, clear flash protection, and reprogram the
device with new firmware that enables DOC. Disabling DOC
features, robust flash protection, and hiding custom analog and
digital functionality inside the PSoC device provide a level of
security not possible with multichip application solutions.
Additionally, all device interfaces can be permanently disabled
(Device Security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device. Permanently
disabling interfaces is not recommended in most applications
Document Number: 001-58402 Rev. *G
because you cannot access the device later. Because all
programming, debug, and test interfaces are disabled when
device security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
Table 9-1. Debug Configurations
Debug and Trace Configuration
All debug and trace disabled
GPIO Pins Used
0
JTAG
4 or 5
SWD
2
SWV
1
SWD + SWV
3
9.1 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four or five
pins (the nTRST pin is optional). The JTAG interface is used for
programming the flash memory, debugging, I/O scan chains, and
JTAG device chaining.
PSoC 3 has certain timing requirements to be met for entering
programming mode through the JTAG interface. Due to these
timing requirements, not all standard JTAG programmers, or
standard JTAG file formats such as SVF or STAPL, can support
PSoC 3 programming. The list of programmers that support
PSoC 3 programming is available at
http://www.cypress.com/go/programming.
The JTAG clock frequency can be up to 14 MHz, or 1/3 of the
CPU clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU
clock frequency for 32-bit transfers. By default, the JTAG pins are
enabled on new devices but the JTAG interface can be disabled,
allowing these pins to be used as GPIO instead.
Page 57 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 9-1. JTAG Interface Connections between PSoC 3 and Programmer
VDD
Host Programmer
PSoC 3
VDD
VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3, 4
TCK
TCK (P1[1]
TMS 5
TMS (P1[0]) 5
TDO
TDI (P1[4])
TDI
TDO (P1[3])
nTRST 6
nTRST (P1[5]) 6
XRES
XRES or P1[2] 4, 7
GND
VSSD, VSSA
GND
1
The voltage levels of Host Programmer and the PSoC 3 voltage domains involved in Programming should be same. The
Port 1 JTAG pins, XRES pin (XRES_N or P1[2]) are powered by VDDIO1. So, VDDIO1 of PSoC 3 should be at same voltage
level as host VDD. Rest of PSoC 3 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage level as
host Programmer.
2
Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3.
3
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external
interface circuitry to toggle power which will depend on the programming setup. The power supplies can
be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other
supplies.
4
For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by
using the TMS,TCK,TDI, TDO pins of PSoC 3, and writing to a specific register. But this requires that the DPS setting in
NVL is not equal to “Debug Ports Disabled”.
5
By default, PSoC 3 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is
unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD
Protocol has to be used for acquiring the PSoC 3 device initially. After switching from SWD to JTAG mode, the TMS pin
will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line.
6
nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 3 as
the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller.
7
If XRES pin is used by host, P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES
pin). For devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-pin
devices, but use dedicated XRES pin for rest of devices.
Document Number: 001-58402 Rev. *G
Page 58 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
9.2 Serial Wire Debug Interface
The SWD interface is the preferred alternative to the JTAG
interface. It requires only two pins instead of the four or five
needed by JTAG. SWD provides all of the programming and
debugging features of JTAG at the same speed. SWD does not
provide access to scan chains or device chaining. The SWD
clock frequency can be up to 1/3 of the CPU clock frequency.
SWD uses two pins, either two of the JTAG pins (TMS and TCK)
or the USBIO D+ and D– pins. The USBIO pins are useful for in
system programming of USB solutions that would otherwise
require a separate programming connector. One pin is used for
the data clock and the other is used for data input and output.
SWD can be enabled on only one of the pin pairs at a time. This
only happens if, within 8 µs (key window) after reset, that pin pair
(JTAG or USB) receives a predetermined sequence of 1s and 0s.
SWD is used for debugging or for programming the flash
memory.
The SWD interface can be enabled from the JTAG interface or
disabled, allowing its pins to be used as GPIO. Unlike JTAG, the
SWD interface can always be reacquired on any device during
the key window. It can then be used to reenable the JTAG
interface, if desired. When using SWD or JTAG pins as standard
GPIO, make sure that the GPIO functionality and PCB circuits do
not interfere with SWD or JTAG use.
Figure 9-2. SWD Interface Connections between PSoC 3 and Programmer
VDD
Host Programmer
VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3
VDD
SWDCK
SWDCK (P1[1] or P15[7])
SWDIO
SWDIO (P1[0] or P15[6])
XRES or P1[2] 3, 4
XRES
GND
PSoC 3
GND
VSSD, VSSA
1
The voltage levels of the Host Programmer and the PSoC 3 voltage domains involved in Programming
should be the same. XRES pin (XRES_N or P1[2]) is powered by VDDIO1. The USB SWD pins are
powered by VDDD. So for Programming using the USB SWD pins with XRES pin, the VDDD, VDDIO1 of
PSoC 3 should be at the same voltage level as Host VDD. Rest of PSoC 3 voltage domains ( VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage level as host Programmer. The Port 1 SWD pins are
powered by VDDIO1. So VDDIO1 of PSoC 3 should be at same voltage level as host VDD for Port 1 SWD
programming. Rest of PSoC 3 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same
voltage level as host Programmer.
2
Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3.
3
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external
interface circuitry to toggle power which will depend on the programming setup. The power supplies can
be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other
supplies.
4
P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES pin). For
devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48pin devices, but use dedicated XRES pin for rest of devices.
Document Number: 001-58402 Rev. *G
Page 59 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
9.3 Debug Features
Using the JTAG or SWD interface, the CY8C32 supports the
following debug features:
 Halt and single-step the CPU
 View and change CPU and peripheral registers, and RAM
addresses
 Eight program address breakpoints
 One memory access breakpoint—break on reading or writing
any memory address and data value
 Break on a sequence of breakpoints (non recursive)
 Debugging at the full speed of the CPU
 Compatible with PSoC Creator and MiniProg3 programmer and
debugger
 Standard JTAG programming and debugging interfaces make
CY8C32 compatible with other popular third-party tools (for
example, ARM / Keil)
9.4 Trace Features
The CY8C32 supports the following trace features when using
JTAG or SWD:
 Trace the 8051 program counter (PC), accumulator register
(ACC), and one SFR / 8051 core RAM register
 Trace depth up to 1000 instructions if all registers are traced,
or 2000 instructions if only the PC is traced (on devices that
include trace memory)
 Program address trigger to start tracing
 Trace windowing, that is, only trace when the PC is within a
given range
 Two modes for handling trace buffer full: continuous (overwriting
the oldest trace data) or break when trace buffer is full
9.5 Single Wire Viewer Interface
The SWV interface is closely associated with SWD but can also
be used independently. SWV data is output on the JTAG
interface’s TDO pin. If using SWV, you must configure the device
for SWD, not JTAG. SWV is not supported with the JTAG
interface.
SWV is ideal for application debug where it is helpful for the
firmware to output data similar to 'printf' debugging on PCs. The
SWV is ideal for data monitoring, because it requires only a
single pin and can output data in standard UART format or
Manchester encoded format. For example, it can be used to tune
a PID control loop in which the output and graphing of the three
error terms greatly simplifies coefficient tuning.
The following features are supported in SWV:
 32 virtual channels, each 32 bits long
 Simple, efficient packing and serializing protocol
 Supports standard UART format (N81)
9.6 Programming Features
The JTAG and SWD interfaces provide full programming
support. The entire device can be erased, programmed, and
verified. You can increase flash protection levels to protect
firmware IP. Flash protection can only be reset after a full device
Document Number: 001-58402 Rev. *G
erase. Individual flash blocks can be erased, programmed, and
verified, if block security settings permit.
9.7 Device Security
PSoC 3 offers an advanced security feature called device
security, which permanently disables all test, programming, and
debug ports, protecting your application from external access.
The device security is activated by programming a 32-bit key
(0×50536F43) to a Write Once Latch (WOL).
The Write Once Latch is a type of nonvolatile latch (NVL). The
cell itself is an NVL with additional logic wrapped around it. Each
WOL device contains four bytes (32 bits) of data. The wrapper
outputs a ‘1’ if a super-majority (28 of 32) of its bits match a
pre-determined pattern (0×50536F43); it outputs a ‘0’ if this
majority is not reached. When the output is 1, the Write Once NV
latch locks the part out of Debug and Test modes; it also
permanently gates off the ability to erase or alter the contents of
the latch. Matching all bits is intentionally not required, so that
single (or few) bit failures do not deassert the WOL output. The
state of the NVL bits after wafer processing is truly random with
no tendency toward 1 or 0.
The WOL only locks the part after the correct 32-bit key
(0×50536F43) is loaded into the NVL's volatile memory,
programmed into the NVL's nonvolatile cells, and the part is
reset. The output of the WOL is only sampled on reset and used
to disable the access. This precaution prevents anyone from
reading, erasing, or altering the contents of the internal memory.
The user can write the key into the WOL to lock out external
access only if no flash protection is set (see “Flash Security” on
page 21). However, after setting the values in the WOL, a user
still has access to the part until it is reset. Therefore, a user can
write the key into the WOL, program the flash protection data,
and then reset the part to lock it.
If the device is protected with a WOL setting, Cypress cannot
perform failure analysis and, therefore, cannot accept RMAs
from customers. The WOL can be read out through the SWD port
to electrically identify protected parts. The user can write the key
in WOL to lock out external access only if no flash protection is
set. For more information on how to take full advantage of the
security features in PSoC see the PSoC 3 TRM.
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress data sheets. Cypress believes that its family
of products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
Page 60 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
10. Development Support
The CY8C32 family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit
psoc.cypress.com/getting-started to find out more.
10.1 Documentation
A suite of documentation, supports the CY8C32 family to ensure
that you can find answers to your questions quickly. This section
contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component data sheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Document Number: 001-58402 Rev. *G
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
10.2 Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
10.3 Tools
With industry standard cores, programming, and debugging
interfaces, the CY8C32 family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Page 61 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11. Electrical Specifications
Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except
where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator
components, see the component data sheets for full AC/DC specifications of individual functions. See the Example Peripherals on
page 40 for further explanation of PSoC Creator components.
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings DC Specifications [13]
Parameter
Description
Conditions
Min
Typ
Max
Units
Recommended storage
temperature is 0 °C–50 °C.
Exposure to storage temperatures
above 125 °C for extended periods
may affect device reliability
–55
25
125
°C
Analog supply voltage relative to
Vssd
–0.5
–
6
V
Digital supply voltage relative to
Vssd
–0.5
–
6
V
Vddio
I/O supply voltage relative to Vssd
–0.5
–
6
V
Vcca
Direct analog core voltage input
–0.5
–
1.95
V
Vccd
Direct digital core voltage input
Vssa
Analog ground voltage
Vgpio[14]
DC input voltage on GPIO
Vsio
DC input voltage on SIO
Ivddio [15]
Current per Vddio supply pin
IGPIO
GPIO current
ISIO
SIO current
IUSBIO
USBIO current
Tstorag
Storage temperature
Vdda
Vddd
–0.5
–
1.95
V
Vssd – 0.5
–
Vssd +
0.5
V
Includes signals sourced by Vdda
and routed internal to the pin
Vssd – 0.5
–
Vddio +
0.5
V
Output disabled
Vssd – 0.5
–
7
V
Output enabled
Vssd – 0.5
–
6
V
–
–
100
mA
–
–
40
–30
–
41
mA
–49
–
28
mA
–56
–
59
mA
–40 °C to +85 °C
–40 °C to +125 °C
VEXTREF
ADC external reference inputs
LU
Latch up current [16]
ESDHBM
Electrostatic discharge voltage,
Human body model
ESDCDM
Electro-static discharge voltage
Pins P0[3], P3[2]
–
–
2
V
–140
–
140
mA
VSSA tied to VSSD
2200
–
–
V
VSSA not tied to VSSD
750
–
–
V
Charge Device Model
500
–
–
V
Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to
maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above
normal operating conditions the device may not operate to specification.
Notes
13. Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for
extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High
Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
14. The Vddio supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin Vddio  Vdda.
15. Maximum value 100 mA of Iddio applies only to –40 °C to +85 °C range and the limit of Iddio parameter for the –40 °C to +125 °C range is 40 mA.
16. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.
Document Number: 001-58402 Rev. *G
Page 62 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.2 Device Level Specifications
Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except
where noted.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Min
Typ
Max
Units
VDDA
Parameter
Analog supply voltage and input Analog core regulator enabled
to analog core regulator
Description
Conditions
1.8
–
5.5
V
VDDA
Analog supply voltage, analog
regulator bypassed
1.71
1.8
1.89
V
VDDD
Digital supply voltage relative to Digital core regulator enabled
VSSD
1.8
–
VDDA[17]
V
VDDD
Digital supply voltage, digital
regulator bypassed
1.71
1.8
1.89
V
VDDIO[18]
I/O supply voltage relative to
VSSIO
1.71
–
VDDA[17]
V
VCCA
Direct analog core voltage input Analog core regulator disabled
(Analog regulator bypass)
1.71
1.8
1.89
V
VCCD
Direct digital core voltage input
(Digital regulator bypass)
1.71
1.8
1.89
V
Analog core regulator disabled
Digital core regulator disabled
Digital core regulator disabled
Notes
17. VDDX = 3.3 V.
18. Based on device specifications (not production tested).
Document Number: 001-58402 Rev. *G
Page 63 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 11-2. DC Specifications (continued)
Parameter
Idd[19, 20]
Description
Conditions
Min
Typ
Max
Units
T = –40 °C
–
1.3
–
mA
T = 25 °C
–
1.6
–
mA
T = 85 °C
–
4.8
–
mA
Active Mode, VDD = 1.71 V - 5.5 V
Execute from CPU instruction
buffer, see Flash Program
Memory on page 21
CPU at 3 MHz
CPU at 6 MHz
CPU at 12 MHz
CPU at 24 MHz
CPU at 48 MHz
CPU at 62 MHz
T = 125 °C
–
4.9
–
mA
T = –40 °C
–
2.1
–
mA
T = 25 °C
–
2.3
–
mA
T = 85 °C
–
5.6
–
mA
T = 125 °C
–
5.8
–
mA
T = –40 °C
–
3.5
–
mA
T = 25 °C
–
3.8
–
mA
T = 85 °C
–
7.1
–
mA
T = 125 °C
–
9.0
–
mA
T = –40 °C
–
6.3
–
mA
T = 25 °C
–
6.6
–
mA
T = 85 °C
–
10
–
mA
T = 125 °C
–
15.8
–
mA
T = –40 °C
–
11.5
–
mA
T = 25 °C
–
12
–
mA
T = 85 °C
–
15.5
–
mA
T = 125 °C
–
21.7
–
mA
T = –40 °C
–
16
–
mA
T = 25 °C
–
16
–
mA
T = 85 °C
–
19.5
–
mA
T = 125 °C
–
27.8
–
mA
Notes
19. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective data sheets, available
in PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your
particular system from the device data sheet and component data sheets.
20. Total current for all power domains: digital (IDDD), analog (IDDA), and I/Os (IDDIO0, 1, 2, 3). All I/Os floating.
Document Number: 001-58402 Rev. *G
Page 64 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 11-2. DC Specifications (continued)
Parameter
Description
Conditions
Min
Typ
Max
Units
Sleep Mode[21]
VDD = VDDIO = 4.5 V–5.5 V
CPU OFF
RTC = ON (= ECO32K ON, in low
power mode)
Sleep timer = ON (= ILO ON at
1 kHz) [22]
VDD = VDDIO = 2.7 V–3.6 V
WDT = OFF
2
I C Wake = OFF
Comparator = OFF
POR = ON
SIO Pins in single ended input,
VCC = VDDIO =
unregulated output mode
1.71 V–1.95 V
T = –40 °C
–
1.1
–
µA
T = 25 °C
–
1.1
–
µA
T = 85 °C
–
15
–
µA
T = 125 °C
–
20.3
–
µA
T = –40 °C
–
1
–
µA
T = 25 °C
–
1
–
µA
T = 85 °C
–
12
–
µA
T = 125 °C
–
18.5
–
µA
T = 25 °C
–
2.2
–
µA
T = 125 °C
–
16.2
–
µA
Comparator = ON
CPU = OFF
RTC = OFF
Sleep timer = OFF
WDT = OFF
I2C Wake = OFF
POR = ON
SIO Pins in single ended input,
unregulated output mode
VDD = VDDIO = 2.7 V–3.6 V T = 25 °C
–
2.2
–
µA
I2C Wake = ON
CPU = OFF
RTC = OFF
Sleep timer = OFF
WDT = OFF
Comparator = OFF
POR = ON
SIO Pins in single ended input,
unregulated output mode
VDD = VDDIO = 2.7 V–3.6 V T = 25 °C
–
2.2
–
µA
Notes
21. If Vccd and Vcca are externally regulated, the voltage difference between Vccd and Vcca must be less than 50 mV.
22. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
Document Number: 001-58402 Rev. *G
Page 65 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 11-2. DC Specifications (continued)
Parameter
Description
Conditions
Min
Typ
Max
Units
VDD = VDDIO = 4.5 V–5.5 V T = –40 °C
–
0.2
–
nA
T = 25 °C
–
0.5
–
nA
T = 85 °C
–
4.1
–
nA
T = 125 °C
–
17.7
–
nA
Hibernate Mode[23]
Hibernate mode current
VDD = VDDIO = 2.7 V–3.6 V
All regulators and oscillators off.
SRAM retention
GPIO interrupts are active
SIO Pins in single ended input,
unregulated output mode
VCC = VDDIO =
1.71 V–1.95 V
IDDAR
IDDDR
IIB
T = –40 °C
–
0.2
–
nA
T = 25 °C
–
0.2
–
nA
T = 85 °C
–
3.2
–
nA
T = 125 °C
–
15.3
–
nA
T = –40 °C
–
0.2
–
nA
T = 25 °C
–
0.2
–
nA
T = 85 °C
–
3.3
–
nA
T = 125 °C
–
12.4
–
nA
VDDA < 3.6 V
–
0.3
–
mA
VDDA > 3.6 V
–
1.4
–
mA
Digital current consumption while VDDD < 3.6 V
device is reset [24]
VDDD > 3.6 V
–
1.1
–
mA
–
0.7
–
mA
–
10
–
pA
Analog current consumption
while device is reset [24]
Input bias current
[24]
T = 25 °C
Notes
23. If Vccd and Vcca are externally regulated, the voltage difference between Vccd and Vcca must be less than 50 mV.
24. Based on device characterization (not production tested). USBIO pins tied to ground (VSSD).
Document Number: 001-58402 Rev. *G
Page 66 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 11-1. Active Mode Current vs FCPU, VDD = 3.3 V, Temperature = 25 °C
Document Number: 001-58402 Rev. *G
Page 67 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 11-3. AC Specifications[25]
Parameter
FCPU
Description
CPU frequency
Conditions
Min
Typ
Max
Units
1.71 V  Vddd  5.5 V, -40°C  Ta
 85°C and Tj  100°C
DC
–
50
MHz
1.71 V  Vddd  5.5 V, -40°C  Ta
 125°C and Tj  150°C
DC
–
50
MHz
1.71 V  Vddd  5.5 V, -40°C  Ta
 85°C and Tj  100°C
DC
–
50
MHz
1.71 V  Vddd  5.5 V, -40°C  Ta
 125°C and Tj  150°C
DC
–
50
MHz
Fbusclk
Bus frequency
Svdd
Vdd ramp rate
–
–
0.066
V/µs
Tio_init
Time from Vddd/Vdda/Vccd/Vcca 
IPOR to I/O ports set to their reset
states
–
–
10
µs
Time from Vddd/Vdda/Vccd/Vcca  Vcca/Vccd = regulated from
PRES to CPU executing code at
Vdda/Vddd, no PLL used, slow
reset vector
IMO boot mode (12 MHz typ.)
–
–
66
µs
Tsleep
Wakeup from sleep mode - Occur- 1.71 V  Vddd  5.5 V, Tj  100°C
rence of LVD interrupt to beginning
of execution of next CPU instruction
–
–
15
µs
Thibernate
Wakeup from hibernate mode Application of external interrupt to
beginning of execution of next CPU
instruction
–
–
100
µs
Tstartup
Figure 11-2. Fcpu vs. Vdd
Vdd Voltage
5.5V
Valid Operating Region
3.3V
1.71V
0V
DC
1 MHz
10 MHz
50 MHz
CPU Frequency
Note
25. Based on device characterization (not production tested).
Document Number: 001-58402 Rev. *G
Page 68 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.3 Power Regulators
Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except
where noted.
11.3.1 Digital Core Regulator
Table 11-4. Digital Core Regulator DC Specifications
Parameter
Description
Vddd
Input voltage
Vccd
Output voltage
Regulator output capacitance
Conditions
Min
Typ
Max
Units
1.8
-
5.5
V
-
1.80
-
V
-
1
-
µF
Total capacitance on the two Vccd pins.
Each capacitor is ±10%, X5R ceramic or
better, see Power System on page 29
Figure 11-3. Regulators VCC vs VDD
Figure 11-4. Digital Regulator PSRR vs Frequency and VDD
Document Number: 001-58402 Rev. *G
Page 69 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.3.2 Analog Core Regulator
Table 11-5. Analog Core Regulator DC Specifications
Parameter
Description
Vdda
Input voltage
Vcca
Output voltage
Regulator output capacitor
Conditions
Min
Typ
Max
1.8
-
5.5
V
-
1.80
-
V
-
1
-
µF
±10%, X5R ceramic or better (X7R for Ta
> 85°C)
Units
Figure 11-5. Analog Regulator PSRR vs Frequency and VDD
Document Number: 001-58402 Rev. *G
Page 70 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.4 Inputs and Outputs
Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except
where noted.
11.4.1 GPIO
Table 11-6. GPIO DC Specifications
Parameter
Description
Vih
Input voltage high threshold
Vil
Input voltage low threshold
Vih
Input voltage high threshold
Vih
Input voltage high threshold
Vil
Input voltage low threshold
Vil
Input voltage low threshold
Voh
Output voltage high
Vol
Output voltage low
Rpullup
Pull up resistor
Rpulldown Pull down resistor
Iil
Input leakage current (absolute
value)[26]
CIN
Input capacitance[26]
Conditions
Min
CMOS Input, PRT[x]CTL = 0
0.7  Vddio
CMOS Input, PRT[x]CTL = 0
LVTTL Input, PRT[x]CTL = 1,Vddio 0.7 x Vddio
< 2.7 V
LVTTL Input, PRT[x]CTL = 1, Vddio
2.0
V
LVTTL Input, PRT[x]CTL = 1,Vddio
< 2.7 V
Typ
-
LVTTL Input, PRT[x]CTL = 1, Vddio
V
Ioh = 4 mA at 3.3 Vddio
Vddio - 0.6
Ioh = 1 mA at 1.8 Vddio
Vddio - 0.5
Iol = 6 mA at 3.3 Vddio
–
Iol = 3 mA at 1.8 Vddio
–
Iol = 3 mA at 3.3 Vddio
–
3.5
3.5
Max
Units
V
0.3 Vddio
V
V
-
-
V
-
0.3 x Vddio
V
-
0.8
V
–
–
–
5.6
5.6
0.6
0.6
0.4
8.5
8.5
V
V
V
V
V
k
k
25°C, Vddio = 3.0 V
-
-
2
nA
GPIOs not shared with opamp
outputs, MHz ECO or kHzECO
GPIOs shared with MHz ECO or
kHzECO[27]
–
4
7
pF
–
5
7
pF
GPIOs shared with opamp outputs
–
–
18
pF
Vh
Input voltage hysteresis
(Schmitt-Trigger)[26]
-
40
-
mV
Idiode
Current through protection diode to
Vddio and Vssio
Resistance pin to analog global bus
Resistance pin to analog mux bus
-
-
100
µA
–
–
320
220
–
–


Rglobal
Rmux
25°C, Vddio = 3.0 V
25°C, Vddio = 3.0 V
Notes
26. Based on device characterization (Not production tested).
27. For information on designing with PSoC 3 oscillators, refer to the application note, AN54439 - PSoC® 3 and PSoC 5 External Oscillator.
Document Number: 001-58402 Rev. *G
Page 71 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 11-6. GPIO Output High Voltage and Current
Figure 11-7. GPIO Output Low Voltage and Current
Document Number: 001-58402 Rev. *G
Page 72 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 11-7. GPIO AC Specifications
Parameter
TriseF
TfallF
TriseS
TfallS
Fgpioout
Fgpioin
Description
Rise time in Fast Strong Mode[25]
Fall time in Fast Strong Mode[25]
Rise time in Slow Strong Mode[25]
Fall time in Slow Strong Mode[25]
GPIO output operating frequency
3 V < Vddio < 5.5 V, fast strong drive
mode
Min
–
–
–
–
Typ
–
–
–
–
Max
12
12
60
60
Units
ns
ns
ns
ns
90/10% Vddio into 25 pF, -40°C 
Ta  85°C and Tj  100°C
90/10% Vddio into 25 pF, -40°C 
Ta  125°C and Tj  150°C
-
-
33
MHz
-
-
24
MHz
1.71 V < Vddio < 3 V, fast strong drive 90/10% Vddio into 25 pF, -40°C 
mode
Ta  85°C and Tj  100°C
-
-
20
MHz
90/10% Vddio into 25 pF, -40°C 
Ta  125°C and Tj  150°C
3 V < Vddio < 5.5 V, slow strong drive 90/10% Vddio into 25 pF, -40°C 
mode
Ta  85°C and Tj  100°C
90/10% Vddio into 25 pF, -40°C 
Ta  125°C and Tj  150°C
1.71 V < Vddio < 3 V, slow strong drive 90/10% Vddio into 25 pF, -40°C 
mode
Ta  85°C and Tj  100°C
90/10% Vddio into 25 pF, -40°C 
Ta  125°C and Tj  150°C
GPIO input operating frequency
-
-
16
MHz
-
-
7
MHz
-
-
7
MHz
-
-
3.5
MHz
-
-
3.5
MHz
90/10% better than 60/40 duty
cycle, -40°C  Ta  85°C and Tj 
100°C
90/10% better than 60/40 duty
cycle, -40°C  Ta  125°C and Tj
 150°C
-
-
66
MHz
-
-
50
MHz
1.71 V < Vddio < 5.5 V
Document Number: 001-58402 Rev. *G
Conditions
3 V Vddio Cload = 25 pF
3 V Vddio Cload = 25 pF
3 V Vddio Cload = 25 pF
3 V Vddio Cload = 25 pF
Page 73 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.4.2 SIO
Table 11-8. SIO DC Specifications
Parameter
Description
Min
Typ
Max
Units
–
–
5.5
V
0.5
-
0.52 Vddio
V
Vddio > 3.7
1
-
Vddio-1
V
Vddio < 3.7
1
-
Vddio - 0.5
V
GPIO mode
CMOS input
0.7  Vddio
-
-
V
Differential input mode
With hysteresis
SIO_ref +
0.2
–
–
V
Vinmax
Maximum input voltage
Vinref
Input voltage reference (Differential input mode)
Conditions
All allowed values of Vddio and
Vddd
Output voltage reference (Regulated output mode)
Voutref
Input voltage high threshold
Vih
Input voltage low threshold
Vil
GPIO mode
CMOS input
-
-
0.3 Vddio
V
Differential input mode
With hysteresis
–
–
SIO_ref –
0.2
V
Vddio - 0.4
-
-
V
SIO_ref 0.65
-
SIO_ref +
0.2
V
SIO_ref - 0.3
-
SIO_ref +
0.2
V
Vddio = 3.30 V, Iol = 25 mA
-
-
0.8
V
Vddio = 1.80 V, Iol = 4 mA
-
-
0.4
V
Output voltage high
Voh
Unregulated mode
Ioh = 4 mA, Vddio = 3.3 V
Regulated mode [28]
Ioh = 1 mA
Regulated mode [28]
Ioh = 0.1 mA
Output voltage low
Vol
VDDIO = 3.3 V, IOL = 20 mA
Rpullup
Rpulldown
Iil
–
–
0.4
V
Pull up resistor
3.5
5.6
8.5
k
Pull down resistor
3.5
5.6
8.5
k
Input leakage current (absolute
value)[29]
Vih < Vddsio
25°C, Vddsio = 3.0 V, Vih = 3.0 V
-
-
14
nA
Vih > Vddsio
25°C, Vddsio = 0 V, Vih = 3.0 V
-
-
10
µA
-
-
7
pF
Cin
Input Capacitance[29]
Vh
Input voltage hysteresis
(Schmitt-Trigger)[29]
Idiode
Current through protection diode
to Vssio
Single ended mode (GPIO mode)
–
40
–
mV
Differential mode
–
35
–
mV
-
-
100
µA
Notes
28. See Figure 6-8 on page 35for more information on SIO reference.
29. Based on device characterization (not production tested).
Document Number: 001-58402 Rev. *G
Page 74 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 11-8. SIO Output High Voltage and Current, Unregulated Mode
Figure 11-9. SIO Output Low Voltage and Current, Unregulated Mode
Figure 11-10. SIO Output High Voltage and Current, Regulated Mode
Document Number: 001-58402 Rev. *G
Page 75 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 11-9. SIO AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
TriseF
Rise time in Fast Strong Mode
(90/10%)[25]
Cload = 25 pF, Vddio = 3.3 V
–
–
12
ns
TfallF
Fall time in Fast Strong Mode
(90/10%)[25]
Cload = 25 pF, Vddio = 3.3 V
–
–
12
ns
TriseS
Rise time in Slow Strong Mode
(90/10%)[25]
Cload = 25 pF, Vddio = 3.0 V
–
–
80
ns
TfallS
Fall time in Slow Strong Mode
(90/10%)[25]
Cload = 25 pF, Vddio = 3.0 V
–
–
70
ns
-
-
33
MHz
-
-
24
MHz
1.71 V < Vddio < 3.3 V, Unregulated 90/10% Vddio into 25 pF
output (GPIO) mode, fast strong
drive mode
-
-
16
MHz
3.3 V < Vddio < 5.5 V, Unregulated 90/10% Vddio into 25 pF
output (GPIO) mode, slow strong
drive mode
-
-
5
MHz
1.71 V < Vddio < 3.3 V, Unregulated 90/10% Vddio into 25 pF
output (GPIO) mode, slow strong
drive mode
-
-
4
MHz
3.3 V < Vddio < 5.5 V, Regulated Output continuously switching into
output mode, fast strong drive mode 25 pF
-
-
20
MHz
1.71 V < Vddio < 3.3 V, Regulated Output continuously switching into
output mode, fast strong drive mode 25 pF
-
-
10
MHz
1.71 V < Vddio < 5.5 V, Regulated Output continuously switching into
25 pF
output mode, slow strong drive
mode
-
-
2.5
MHz
90/10% better than 60/40 duty
cycle, -40°C  Ta  85°C and Tj 
100°C
-
-
66
MHz
90/10% better than 60/40 duty
cycle, -40°C  Ta  125°C and Tj
 150°C
-
-
50
MHz
SIO output operating frequency
3.3 V < Vddio < 5.5 V, Unregulated 90/10% Vddio into 25 pF, -40°C 
Ta  85°C and Tj  100°C
output (GPIO) mode, fast strong
drive mode
90/10% Vddio into 25 pF, -40°C 
Ta  125°C and Tj  150°C
Fsioout
SIO input operating frequency
Fsioin
1.71 V < Vddio < 5.5 V
Document Number: 001-58402 Rev. *G
Page 76 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 11-11. SIO Output Rise and Fall Times, Fast Strong Mode, VDDIO = 3.3 V, 25 pF Load
Figure 11-12. SIO Output Rise and Fall Times, Slow Strong Mode, VDDIO = 3.3 V, 25 pF Load
Document Number: 001-58402 Rev. *G
Page 77 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.4.3 USBIO
Table 11-10. USBIO DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Rusbi
USB D+ pull up resistance
With idle bus
0.900
-
1.575
k
Rusba
USB D+ pull up resistance
While receiving traffic
1.425
-
3.090
k
Vohusb
Static output high
15 k ±5% to Vss, internal pull up
enabled
2.8
-
3.6
V
Volusb
Static output low
15 k ±5% to Vss, internal pull up
enabled
-
-
0.3
V
Vihgpio
Input voltage high, GPIO mode
VDDD 3 V
2
–
–
V
Vilgpio
Input voltage low, GPIO mode
VDDD 3 V
–
–
0.8
V
Vohgpio
Output voltage high, GPIO mode
Ioh = 4 mA, Vddio  3 V
2.4
-
-
V
Volgpio
Output voltage low, GPIO mode
Iol = 4 mA, Vddio  3 V
-
-
0.3
V
Vdi
Differential input sensitivity
|(D+)-(D-)|
-
-
0.2
V
Vcm
Differential input common mode
range
0.8
-
2.5
V
Vse
Single ended receiver threshold
0.8
-
2
V
Rps2
PS/2 pull up resistance
In PS/2 mode, with PS/2 pull up
enabled
3
-
7
k
External USB series resistor
In series with each USB pin
21.78
(-1%)
22
22.22
(+1%)

USB driver output impedance
Including Rext, -40°C  Ta  85°C
and Tj  100°C
28
-
44

Including Rext, -40°C  Ta  125°C
and Tj  150°C
28
-
46

-
-
20
pF
-
-
2
nA
Rext
Zo
Cin
Iil
[30]
USB transceiver input capacitance
Input leakage current (absolute
value)
25°C, Vddio = 3.0 V
Note
30. Based on device characterization (not production tested).
Document Number: 001-58402 Rev. *G
Page 78 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 11-13. USBIO Output High Voltage and Current, GPIO Mode
Figure 11-14. USBIO Output Low Voltage and Current, GPIO Mode
Document Number: 001-58402 Rev. *G
Page 79 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 11-11. USBIO AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Tdrate
Full-speed data rate average bit rate
12 - 0.25%
12
12 +
0.25%
MHz
Tdjr1
Receiver data jitter tolerance to next
transition
-8
-
8
ns
Tdjr2
Receiver data jitter tolerance to pair
transition
-5
-
5
ns
Tudj1
Driver differential jitter to next
transition
-3.5
-
3.5
ns
Tudj2
Driver differential jitter to pair transition
-4
-
4
ns
Tfdeop
Source jitter for differential transition to
SE0 transition
-2
-
5
ns
Tfeopt
Source SE0 interval of EOP
160
-
175
ns
Tfeopr
Receiver SE0 interval of EOP
82
-
-
ns
Tfst
Width of SE0 interval during differential transition
-
-
14
ns
Fgpio_out
GPIO mode output operating
frequency
3 V  Vddd  5.5 V
-
-
20
MHz
Vddd = 1.71 V
-
-
6
MHz
Tr_gpio
Rise time, GPIO mode, 10%/90%
Vddd
Vddd > 3 V, 25 pF load
–
–
12
ns
Tf_gpio
Fall time, GPIO mode, 90%/10% Vddd Vddd > 3 V, 25 pF load
Vddd = 1.71 V, 25 pF load
Vddd = 1.71 V, 25 pF load
–
–
40
ns
–
–
12
ns
–
–
40
ns
Figure 11-15. USBIO Output Rise and Fall Times, GPIO Mode, VDDD = 3.3 V, 25 pF Load
Table 11-12. USB Driver AC Specifications
Parameter
Description
Tr
Transition rise time
Tf
Transition fall time
TR
Rise/fall time matching
Vcrs
Output signal crossover voltage
Document Number: 001-58402 Rev. *G
Conditions
VUSB_5, VUSB_3.3, see
Min
Typ
Max
Units
–
–
20
ns
ns
–
–
20
90%
-
111%
1.3
-
2
V
Page 80 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.4.4 XRES
Table 11-13. XRES DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Vih
Input voltage high threshold
CMOS Input, PRT[x]CTL = 0
0.7  Vddio
-
-
V
Vil
Input voltage low threshold
CMOS Input, PRT[x]CTL = 0
-
-
0.3 Vddio
V
Rpullup
Pull up resistor
3.5
5.6
8.5
k
Cin
Input capacitance[25]
-
3
-
pF
Vh
Input voltage hysteresis
(Schmitt-Trigger)[25]
-
100
-
mV
Idiode
Current through protection diode to
Vddio and Vssio
-
-
100
µA
Min
Typ
Max
Units
1
-
-
µs
Table 11-14. XRES AC Specifications
Parameter
Treset
Description
Reset pulse width
Document Number: 001-58402 Rev. *G
Conditions
Page 81 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.5 Analog Peripherals
11.5.1 Delta-Sigma ADC
Unless otherwise specified, operating conditions are:
 Operation in continuous sample mode
 fclk = 6.144 MHz for resolution = 8 to 12 bits
 Reference = 1.024 V internal reference bypassed on P3.2 or P0.3
 Unless otherwise specified, all charts and graphs show typical values
Table 11-15. 12-bit Delta-sigma ADC DC Specifications
Parameter
Description
Conditions
Resolution
Number of channels, single ended
Min
Typ
Max
Units
8
–
12
bits
–
–
No. of
GPIO
–
Number of channels, differential
Differential pair is formed using a
pair of GPIOs.
–
–
No. of
GPIO/2
–
Monotonic
Yes
–
–
–
–
Ge
Gain error
Buffered, buffer gain = 1, Range =
±1.024 V, 16-bit mode, 25 °C
–
–
±0.2
%
Gd
Gain drift
Buffered, buffer gain = 1, Range =
±1.024 V, 16-bit mode
–
–
50
ppm/°C
Buffered, 16-bit mode,
full voltage range
–
–
±0.2
mV
Buffered, 16-bit mode,
VDDA = 1.8 V + 5%
–
–
±0.1
mV
Buffer gain = 1, 16-bit,
Range = ±1.024 V
–
–
1
µV/°C
Input voltage range, single ended[31]
VSSA
–
VDDA
V
Input voltage range, differential unbuffered[31]
VSSA
–
VDDA
V
Input voltage range, differential, buffered[31]
VSSA
–
VDDA – 1
V
Vos
TCVos
Input offset voltage
Temperature coefficient, input offset voltage
PSRRb
Power supply rejection ratio, buffered[31]
Buffer gain = 1, 16-bit,
Range = ±1.024 V
90
–
–
dB
CMRRb
Common mode rejection ratio, buffered[31]
Buffer gain = 1, 16 bit,
Range = ±1.024 V
85
–
–
dB
INL12
Integral non linearity[31]
Range = ±1.024 V, unbuffered
–
–
±1
LSB
DNL12
Differential non linearity[31]
Range = ±1.024 V, unbuffered
–
–
±1
LSB
Range = ±1.024 V, unbuffered
–
–
±1
LSB
Range = ±1.024 V, unbuffered
–
–
±1
LSB
[31]
INL8
Integral non linearity
DNL8
Differential non linearity[31]
Note
31. Based on device characterization (not production tested).
Document Number: 001-58402 Rev. *G
Page 82 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 11-15. 12-bit Delta-sigma ADC DC Specifications (continued)
Parameter
Min
Typ
Max
Units
Input buffer used
10
–
–
M
Rin_ADC12 ADC input resistance
Input buffer bypassed, 12 bit,
Range = ±1.024 V
–
148[32]
–
k
Vextref
Pins P0[3], P3[2]
0.9
–
1.3
V
–
–
1.95
mA
–
–
2.5
mA
Rin_Buff
Description
ADC input resistance
ADC external reference input voltage
Conditions
Current Consumption
IDD_12
IBUFF
IDDD + IDDA Current consumption, 12 bit [33] 192 ksps, unbuffered
Buffer current consumption
[33]
Notes
32. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional
to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.
33. Based on device characterization (Not production tested).
Document Number: 001-58402 Rev. *G
Page 83 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 11-16. Delta-sigma ADC AC Specifications
Parameter
Description
Conditions
Startup time
Total harmonic distortion[33]
THD
Min
Typ
Max
Units
–
–
4
Samples
Buffer gain = 1, 16 bit,
Range = ±1.024 V
–
–
0.0040
%
12-Bit Resolution Mode
SR12
Sample rate, continuous, high power[33]
Range = ±1.024 V, unbuffered
4
–
192
ksps
BW12
Input bandwidth at max sample rate[33]
Range = ±1.024 V, unbuffered
–
44
–
kHz
SINAD12int
Signal to noise ratio, 12-bit, internal
reference[33]
Range = ±1.024 V, unbuffered
66
–
–
dB
Range = ±1.024 V, unbuffered
8
–
384
ksps
Range = ±1.024 V, unbuffered
–
88
–
kHz
Range = ±1.024 V, unbuffered
43
–
–
dB
8-Bit Resolution Mode
Sample rate, continuous, high power[33]
SR8
rate[33]
BW8
Input bandwidth at max sample
SINAD8int
Signal to noise ratio, 8-bit, internal
reference[33]
Table 11-17. Delta-sigma ADC Sample Rates, Range = ±1.024 V
Continuous
Multi-Sample
Multi-Sample Turbo
Resolution,
Bits
Min
Max
Min
Max
Min
Max
8
8000
384000
1911
91701
1829
87771
9
6400
307200
1543
74024
1489
71441
10
5566
267130
1348
64673
1307
62693
11
4741
227555
1154
55351
1123
53894
12
4000
192000
978
46900
956
45850
Document Number: 001-58402 Rev. *G
Page 84 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 11-16. Delta-sigma ADC IDD vs sps, Range = ±1.024 V, Continuous Sample Mode, Input Buffer Bypassed
Document Number: 001-58402 Rev. *G
Page 85 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.5.2 Voltage Reference
Table 11-18. Voltage Reference Specifications
Parameter
Vref
Description
Precision reference
Conditions
Min
Typ
Max
Units
-40°C  Ta  85°C and Tj  100°C
1.021
(-0.3%)
1.024
1.027
(+0.3%)
V
-40°C  Ta  125°C and Tj  150°C
1.018
(–0.6%)
1.024
1.030
(+0.6%)
V
After typical PCB assembly, post reflow Typical (non-optimized) board
layout and 250 °C solder reflow.
Device may be calibrated after
assembly to improve performance.
–40 °C
±0.5
%
25 °C
±0.2
%
85 °C
Temperature drift[34]
Box method
±0.2
%
–
–
30
ppm/°C
Long term drift
–
100
–
ppm/khr
Thermal cycling drift (stability)[34, 35]
–
100
–
ppm
Figure 11-17. Voltage Reference vs. Temperature and VCCA
Figure 11-18. Voltage Reference Long-Term Drift
Notes
34. Based on device characterization (Not production tested).
35. After eight full cycles between –40 °C and 100 °C.
Document Number: 001-58402 Rev. *G
Page 86 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.5.3 Analog Globals
Table 11-19. Analog Globals Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Resistance pin-to-pin through P2[4],
AGL0, DSM INP, AGL1, P2[5][36]
VDDA = 3 V
–
1472
2200

Rppmuxbus Resistance pin-to-pin through P2[3],
amuxbusL, P2[4][36]
VDDA = 3 V
–
706
1100

Min
Typ
Rppag
11.5.4 Comparator
Table 11-20. Comparator DC Specifications
Parameter
VOS
Description
Conditions
Input offset voltage in fast mode
Factory trim, Vdda > 2.7 V,
Vin  0.5 V
–
Input offset voltage in slow mode
Factory trim, Vin  0.5 V
–
Input offset voltage in fast mode[37]
Custom trim
–
Input offset voltage in slow mode[37]
Custom trim
Max
Units
10
mV
9
mV
–
4
mV
–
–
4
mV
Input offset voltage in ultra low-power VDDA ≤ 4.6 V
mode
–
±12
–
mV
VHYST
Hysteresis
Hysteresis enable mode
–
10
32
mV
VICM
Input common mode voltage
High current / fast mode
VSSA
–
VDDA
V
Low current / slow mode
VSSA
–
VDDA
V
Ultra low-power mode
VDDA ≤ 4.6 V
VSSA
–
VDDA –
1.15
V
–
50
–
dB
-
-
400
µA
CMRR
Common mode rejection ratio
Icmp
High current mode/fast mode[25]
-40°C  Ta  85°C and Tj  100°C
-40°C  Ta  125°C and Tj  150°C
-
-
600
µA
Low current mode/slow mode[25]
-40°C  Ta  85°C and Tj  100°C
-
-
100
µA
-40°C  Ta  125°C and Tj  150°C
-
-
150
µA
Ultra low power mode[25]
VDDA < 4.6 V
-
6
-
µA
Table 11-21. Comparator AC Specifications
Parameter
TRESP
Min
Typ
Max
Units
Response time, high current mode[38] 50 mV overdrive, measured
pin-to-pin
Description
–
75
110
ns
Response time, low current mode[38] 50 mV overdrive, measured
pin-to-pin
–
155
200
ns
50 mV overdrive, measured
pin-to-pin, VDDA ≤ 4.6 V
–
55
–
µs
Response time, ultra low-power
mode[38]
Conditions
Note
36. The resistance of the analog global and analog mux bus is high if VDDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog
mux bus under these conditions is not recommended.
37. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM.
38. Based on device characterization (Not production tested).
Document Number: 001-58402 Rev. *G
Page 87 of 132
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11.5.5 IDAC
All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 9 for details). See the IDAC
component data sheet in PSoC Creator for full electrical specifications and APIs.
Unless otherwise specified, all charts and graphs show typical values.
Table 11-22. IDAC (Current Digital-to-Analog Converter) DC Specifications
Parameter
Description
Conditions
Resolution
IOUT
Output current at code = 255
DNL
Integral nonlinearity
Differential nonlinearity
Typ
Max
Units
-
8
-
Range = 2.04 mA, code = 255,
VDDA  2.7 V, Rload = 600 
–
2.04
–
mA
Range = 2.04 mA, high speed
mode, code = 255, VDDA  2.7 V,
Rload = 300 
–
2.04
–
mA
Range = 255 µA, code = 255, Rload
= 600 
–
255
–
µA
Range = 31.875 µA, code = 255,
Rload = 600 
–
31.875
–
µA
–
–
Yes
Sink mode, range = 255 µA, Codes
8 – 255, Rload = 2.4 k, Cload =
15 pF
–
±0.9
±1
LSB
Source mode, range = 255 µA,
Codes 8 – 255, Rload = 2.4 k,
Cload = 15 pF
–
±1.2
±1.5
LSB
Sink mode, range = 255 µA, Rload
= 2.4 k, Cload = 15 pF
–
±0.3
±1
LSB
Source mode, range = 255 µA,
Rload = 2.4 k, Cload = 15 pF
–
±0.3
±1
LSB
-
0
±1
LSB
Monotonicity
INL
Min
Ezs
Zero scale error
-40°C  Ta  85°C and Tj  100°C
-40°C  Ta  125°C and Tj  150°C
-
-
±2
LSB
Eg
Gain error
Range = 2.04 mA, 25 °C
–
–
±2.5
%
TC_Eg
Range = 255 µA, 25 ° C
–
–
±2.5
%
Range = 31.875 µA, 25 ° C
–
–
±3.5
%
–
–
0.04
% / °C
–
–
0.04
% / °C
–
–
0.05
% / °C
1
–
–
V
Temperature coefficient of gain error Range = 2.04 mA
Range = 255 µA
Range = 31.875 µA
Vcompliance Dropout voltage, source or sink mode Voltage headroom at max current,
Rload to Vdda or Rload to Vssa,
Vdiff from Vdda
Document Number: 001-58402 Rev. *G
Page 88 of 132
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Automotive Family Datasheet
Table 11-22. IDAC (Current Digital-to-Analog Converter) DC Specifications (continued)
Parameter
IDD
Description
Operating current, code = 0
Conditions
Min
Typ
Max
Units
Low speed mode, source mode,
range = 31.875 µA
–
44
100
µA
Low speed mode, source mode,
range = 255 µA,
–
33
100
µA
Low speed mode, source mode,
range = 2.04 mA
–
33
100
µA
Low speed mode, sink mode,
range = 31.875 µA
–
36
100
µA
Low speed mode, sink mode,
range = 255 µA
–
33
100
µA
Low speed mode, sink mode,
range = 2.04 mA
–
33
100
µA
High speed mode, source mode,
range = 31.875 µA
–
310
500
µA
High speed mode, source mode,
range = 255 µA
–
305
500
µA
High speed mode, source mode,
range = 2.04 mA
–
305
500
µA
High speed mode, sink mode,
range = 31.875 µA
–
310
500
µA
High speed mode, sink mode,
range = 255 µA
–
300
500
µA
High speed mode, sink mode,
range = 2.04 mA
–
300
500
µA
Figure 11-19. IDAC INL vs Input Code, Range = 255 µA, Source Mode
Document Number: 001-58402 Rev. *G
Page 89 of 132
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Automotive Family Datasheet
Figure 11-20. IDAC INL vs Input Code, Range = 255 µA, Sink Mode
Figure 11-21. IDAC DNL vs Input Code, Range = 255 µA, Source Mode
Figure 11-22. IDAC DNL vs Input Code, Range = 255 µA, Sink Mode
Document Number: 001-58402 Rev. *G
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Automotive Family Datasheet
Figure 11-23. IDAC INL vs Temperature, Range = 255 µA, High speed mode
Figure 11-24. IDAC DNL vs Temperature, Range = 255 µA, High speed mode
Figure 11-25. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode
Document Number: 001-58402 Rev. *G
Page 91 of 132
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Automotive Family Datasheet
Figure 11-26. IDAC Full Scale Error vs Temperature, Range = 255 µA, Sink Mode
Figure 11-27. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode
Figure 11-28. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Sink Mode
Document Number: 001-58402 Rev. *G
Page 92 of 132
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Automotive Family Datasheet
Table 11-23. IDAC (Current Digital-to-Analog Converter) AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Fdac
Update rate
–
–
8
Msps
TSETTLE
Settling time to 0.5 LSB
Range = 31.875 µA or 255 µA, full
scale transition, High speed mode,
600  15-pF load
–
–
125
ns
Current noise
Range = 255 µA, source mode,
High speed mode, Vdda = 5 V,
10 kHz
–
340
–
pA/sqrtHz
Figure 11-29. IDAC Step Response, Codes 0x40 - 0xC0, 255 µA Mode, Source Mode, High speed mode, Vdda = 5 V
Figure 11-30. IDAC Glitch Response, Codes 0x7F - 0x80, 255 µA Mode, Source Mode, High speed mode, Vdda = 5 V
Document Number: 001-58402 Rev. *G
Page 93 of 132
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Figure 11-31. IDAC PSRR vs Frequency
Figure 11-32. IDAC Current Noise, 255 µA Mode, Source Mode, High speed mode, Vdda = 5 V
Document Number: 001-58402 Rev. *G
Page 94 of 132
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Automotive Family Datasheet
11.5.6 VDAC
Table 11-24. VDAC (Voltage Digital-to-Analog Converter) DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
-
8
-
-
16
-
k
Resolution
Units
Output resistance[25]
Rout
High
Vout = 4 V
Vout = 1 V
-
4
-
k
Vout
Output voltage range, code = 255
Low
1 V scale
–
1.02
–
V
4 V scale, Vdda = 5 V
–
4.08
–
V
INL
Integral nonlinearity
1 V scale
–
±2.1
±2.5
LSB
DNL
Differential nonlinearity
1 V scale
–
±0.3
±1
LSB
–
–
Yes
–
Eg
Gain error
1 V scale,
–
–
±2.5
%
4 V scale
–
–
±2.5
%
TC_Eg
Temperature coefficient, gain error
1 V scale,
–
–
0.03
%FSR / °C
4 V scale
–
–
0.03
%FSR / °C
VDAC_ICC
Operating current
Low speed mode
–
–
100
µA
High speed mode
–
–
500
µA
–
0
±0.9
LSB
Monotonicity
VOS
Zero scale error
Figure 11-33. VDAC INL vs Input Code, 1 V Mode
Document Number: 001-58402 Rev. *G
Page 95 of 132
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Automotive Family Datasheet
Figure 11-34. VDAC DNL vs Input Code, 1 V Mode
Figure 11-35. VDAC INL vs Temperature, 1 V Mode
Figure 11-36. VDAC DNL vs Temperature, 1 V Mode
Document Number: 001-58402 Rev. *G
Page 96 of 132
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Automotive Family Datasheet
Figure 11-37. VDAC Full Scale Error vs Temperature, 1 V Mode
Figure 11-38. VDAC Full Scale Error vs Temperature, 4 V Mode
Figure 11-39. VDAC Operating Current vs Temperature, 1V Mode, Low speed mode
Document Number: 001-58402 Rev. *G
Page 97 of 132
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Automotive Family Datasheet
Figure 11-40. VDAC Operating Current vs Temperature, 1 V Mode, High speed mode
Document Number: 001-58402 Rev. *G
Page 98 of 132
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Automotive Family Datasheet
Table 11-25. VDAC (Voltage Digital-to-Analog Converter) AC Specifications
Parameter
Fdac
TsettleP
TsettleN
Description
Conditions
Min
Typ
-
-
Max
Units
1
Msps
250
Ksps
[25]
Update rate
1 V mode
Update rate[25]
4 V mode
Settling time to 0.1%, step 25% to
75%
1 V scale, Cload = 15 pF
–
0.45
1
µs
4 V scale, Cload = 15 pF
–
0.8
3.2
µs
Settling time to 0.1%, step 75% to
25%
1 V scale, Cload = 15 pF
–
0.45
1
µs
4 V scale, Cload = 15 pF
–
0.7
3
µs
Voltage noise
Range = 1 V, High speed mode,
Vdda = 5 V, 10 kHz
–
750
–
nV/sqrtHz
Figure 11-41. VDAC Step Response, Codes 0x40 - 0xC0, 1 V Mode, High speed mode, Vdda = 5 V
Figure 11-42. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V Mode, High speed mode, Vdda = 5 V
Document Number: 001-58402 Rev. *G
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Figure 11-43. VDAC PSRR vs Frequency
Figure 11-44. VDAC Voltage Noise, 1 V Mode, High speed mode, Vdda = 5 V
Document Number: 001-58402 Rev. *G
Page 100 of 132
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Automotive Family Datasheet
11.5.7 Temperature Sensor
Table 11-26. Temperature Sensor Specifications
Parameter
Description
Temp sensor accuracy
Conditions
Range: –40 °C to +150 °C
Min
Typ
Max
Units
-
±5
-
°C
11.5.8 LCD Direct Drive
Table 11-27. LCD Direct Drive DC Specifications
Parameter
Description
ICC
LCD system operating current
ICC_SEG
VBIAS
IOUT
Conditions
Device sleep mode with wakeup at
400-Hz rate to refresh LCDs, bus
clock = 3 Mhz, Vddio = Vdda = 3 V,
4 commons, 16 segments, 1/4 duty
cycle, 50 Hz frame rate, no glass
connected
Min
–
Typ
38
Max
–
Units
A
Current per segment driver
Strong drive mode
LCD bias range (VBIAS refers to the VDDA  3 V and VDDA  VBIAS
main output voltage(V0) of LCD DAC)
LCD bias step size
VDDA  3 V and VDDA  VBIAS
–
2
260
–
–
5
µA
V
–
–
mV
LCD capacitance per
segment/common driver
Long term segment offset
Output drive current per segment
driver)
–
9.1 ×
VDDA
500
5000
pF
–
355
–
–
20
710
mV
µA
Min
Typ
Max
Units
10
50
150
Hz
Drivers may be combined
Vddio = 5.5V, strong drive mode
Table 11-28. LCD Direct Drive AC Specifications
Parameter
fLCD
Description
LCD frame rate
Document Number: 001-58402 Rev. *G
Conditions
Page 101 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.6 Digital Peripherals
Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except
where noted.
11.6.1 Timer
Table 11-29. Timer DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit timer, at listed input clock
frequency
3 MHz
Min
Typ
Max
Units
–
–
–
µA
–
15
–
µA
12 MHz
–
60
–
µA
50 MHz
–
260
–
µA
Min
Typ
Max
Units
Table 11-30. Timer AC Specifications
Parameter
Description
Operating frequency
Capture pulse width (Internal)
Capture pulse width (external)
Timer resolution
Enable pulse width
Enable pulse width (external)
Reset pulse width
Reset pulse width (external)
Conditions
-40°C  Ta  85°C and Tj  100°C
DC
-
-40°C  Ta  125°C and Tj  150°C
DC
-
50
[39]
50
MHz
MHz
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
-40°C  Ta  85°C and Tj  100°C
30
-
-
ns
-40°C  Ta  125°C and Tj  150°C
42
-
-
ns
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
-40°C  Ta  85°C and Tj  100°C
30
-
-
ns
-40°C  Ta  125°C and Tj  150°C
42
-
-
ns
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
-40°C  Ta  85°C and Tj  100°C
30
-
-
ns
-40°C  Ta  125°C and Tj  150°C
42
-
-
ns
Note
39. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C.
Document Number: 001-58402 Rev. *G
Page 102 of 132
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Automotive Family Datasheet
11.6.2 Counter
Table 11-31. Counter DC Specifications
Parameter
Description
Block current consumption
Conditions
Min
Typ
Max
Units
16-bit counter, at listed input clock
frequency
–
–
–
µA
3 MHz
–
15
–
µA
12 MHz
–
60
–
µA
50 MHz
–
260
–
µA
Min
Typ
Max
Units
MHz
MHz
Table 11-32. Counter AC Specifications
Parameter
Description
Operating frequency
Capture pulse
Resolution
Pulse width
Pulse width (external)
Enable pulse width
Enable pulse width (external)
Reset pulse width
Reset pulse width (external)
Conditions
-40°C  Ta  85°C and Tj  100°C
DC
-
50[40]
-40°C  Ta  125°C and Tj  150°C
DC
-
50
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
-40°C  Ta  85°C and Tj  100°C
30
-
-
ns
-40°C  Ta  125°C and Tj  150°C
42
-
-
ns
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
-40°C  Ta  85°C and Tj  100°C
30
-
-
ns
-40°C  Ta  125°C and Tj  150°C
42
-
-
ns
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
-40°C  Ta  85°C and Tj  100°C
30
-
-
ns
-40°C  Ta  125°C and Tj  150°C
42
-
-
ns
Note
40. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C.
Document Number: 001-58402 Rev. *G
Page 103 of 132
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Automotive Family Datasheet
11.6.3 Pulse Width Modulation
Table 11-33. PWM DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit PWM, at listed input clock
frequency
Min
Typ
Max
Units
–
–
–
µA
3 MHz
–
15
–
µA
12 MHz
–
60
–
µA
50 MHz
–
260
–
µA
Table 11-34. Pulse Width Modulation (PWM) AC Specifications
Parameter
Conditions
Min
Typ
Max
Units
Operating frequency
Description
-40°C  Ta  85°C and Tj  100°C
DC
-
50 [41]
MHz
-40°C  Ta  125°C and Tj  150°C
DC
-
50
MHz
Pulse width
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
Pulse width (external)
-40°C  Ta  85°C and Tj  100°C
30
-
-
ns
-40°C  Ta  125°C and Tj  150°C
42
-
-
ns
Kill pulse width
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
Kill pulse width (external)
-40°C  Ta  85°C and Tj  100°C
30
-40°C  Ta  125°C and Tj  150°C
42
-
-
ns
Enable pulse width
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
Enable pulse width (external)
-40°C  Ta  85°C and Tj  100°C
30
-
-
ns
-40°C  Ta  125°C and Tj  150°C
42
-
-
ns
Reset pulse width
-40°C  Ta  85°C and Tj  100°C
15
-
-
ns
-40°C  Ta  125°C and Tj  150°C
21
-
-
ns
Reset pulse width (external)
-40°C  Ta  85°C and Tj  100°C
30
-
-
ns
-40°C  Ta  125°C and Tj  150°C
42
-
-
ns
ns
Note
41. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C.
Document Number: 001-58402 Rev. *G
Page 104 of 132
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Automotive Family Datasheet
11.6.4 I2C
Table 11-35. Fixed I2C DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Block current consumption
Enabled, configured for 100 kbps
–
–
250
µA
–
Enabled, configured for 400 kbps
–
–
260
µA
–
Wake from sleep mode
–
–
30
µA
Min
Typ
Max
Units
-
-
1
Mbps
Table 11-36. Fixed I2C AC Specifications
Parameter
Description
Bit rate
Conditions
Note
42. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C.
Document Number: 001-58402 Rev. *G
Page 105 of 132
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Automotive Family Datasheet
11.6.5 USB
Table 11-37. USB DC Specifications
Parameter
Description
Min
Typ
Max
Units
USB configured, USB regulator
enabled
4.35
–
5.25
V
VUSB_3.3
USB configured, USB regulator
bypassed
3.15
–
3.6
V
VUSB_3
USB configured, USB regulator
bypassed[43]
2.85
–
3.6
V
–
10
–
mA
–
8
–
mA
VDDD = 5 V, connected to USB
host, PICU configured to wake on
USB resume signal
–
0.5
–
mA
VDDD = 5 V, disconnected from
USB host
–
0.3
–
mA
VDDD = 3.3 V, connected to USB
host, PICU configured to wake on
USB resume signal
–
0.5
–
mA
VDDD = 3.3 V, disconnected from
USB host
–
0.3
–
mA
VUSB_5
Device supply for USB operation
IUSB_Configured
Conditions
Device supply current in device
VDDD = 5 V, FCPU = 1.5 MHz
active mode, bus clock and IMO = V
DDD = 3.3 V, FCPU = 1.5 MHz
24 MHz
IUSB_Suspended Device supply current in device
sleep mode
11.6.6 Universal Digital Blocks (UDBs)
PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,
AND, OR, and so on) that are mapped to the UDB array. See the component data sheets in PSoC Creator for full AC/DC specifications,
APIs, and example code.
Table 11-38. UDB AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Datapath Performance
Fmax_timer Maximum frequency of 16-bit timer in a -40°C  Ta  85°C and Tj  100°C
UDB pair
-40°C  Ta  125°C and Tj  150°C
-
-
50
MHz
-
-
50
MHz
Fmax_adder Maximum frequency of 16-bit adder in a -40°C  Ta  85°C and Tj  100°C
UDB pair
-40°C  Ta  125°C and Tj  150°C
-
-
50
MHz
-
-
50
MHz
Fmax_CRC Maximum frequency of 16-bit CRC/PRS -40°C  Ta  85°C and Tj  100°C
in a UDB pair
-40°C  Ta  125°C and Tj  150°C
-
-
50
MHz
-
-
50
MHz
-
-
50
MHz
-
-
50
MHz
PLD Performance
Fmax_PLD
Maximum frequency of a two-pass PLD -40°C  Ta  85°C and Tj  100°C
function in a UDB pair
-40°C  Ta  125°C and Tj  150°C
Clock to Output Performance
tclk_out
Propogation delay for clock in to data out, 25 °C, Vddd  2.7 V
see Figure 11-45.
-
20
25
ns
tclk_out
Propogation delay for clock in to data out, Worst-case placement, routing,
see Figure 11-45.
and pin selection
-
–
55
ns
Note
43. Rise/fall time matching (TR) not guaranteed, see .
Document Number: 001-58402 Rev. *G
Page 106 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 11-45. Clock to Output Performance
Document Number: 001-58402 Rev. *G
Page 107 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.7 Memory
Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except
where noted.
11.7.1 Flash
Table 11-39. Flash DC Specifications
Parameter
Description
Conditions
Erase and program voltage
Vddd pin
Min
Typ
Max
Units
1.71
-
5.5
V
Min
Typ
Max
Units
Table 11-40. Flash AC Specifications
Parameter
Twrite
Terase
Description
Conditions
Block write time (erase + program)
Block erase time
Block program time
Tbulk
Bulk erase time (16 KB to 64
KB)[44]
KB)[44]
-40°C  Ta  85°C and Tj  100°C
-
-
15
ms
-40°C  Ta  125°C and Tj  140°C
-
-
15
ms
-40°C  Ta  85°C and Tj  100°C
-
-
10
ms
-40°C  Ta  125°C and Tj  140°C
-
-
10
ms
-40°C  Ta  85°C and Tj  100°C
-
-
5
ms
-40°C  Ta  125°C and Tj  140°C
-
-
5
ms
-40°C  Ta  85°C and Tj  100°C
-
-
35
ms
-40°C  Ta  125°C and Tj  140°C
-
-
TBD
ms
-40°C  Ta  85°C and Tj  100°C
-
-
15
ms
-40°C  Ta  125°C and Tj  140°C
-
-
15
ms
Total device program time
(including JTAG, etc.)
No overhead [45]
-
-
5
seconds
Flash data retention time,
retention period measured from last
erase cycle [46]
Average ambient temp.
TA  55 °C, 100 K erase/program
cycles
20
–
–
years
Retention period measured from
last erase cycle after 100k
progra/erase cycles at TA  85 °C
10
–
–
Sector erase time (8 KB to 16
Note
44. ECC not included.
45. See PSoC® 3 Device Programming Specifications for a description of a low-overhead method of programming PSoC 3 flash. (Please take care of Foot note numbers)
46. Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +125 °C
ambient temperature range. Contact [email protected]
Document Number: 001-58402 Rev. *G
Page 108 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.7.2 EEPROM
Table 11-41. EEPROM DC Specifications
Parameter
Description
Conditions
Erase and program voltage
Min
Typ
Max
Units
1.71
-
5.5
V
Table 11-42. EEPROM AC Specifications
Parameter
TWRITE
Min
Typ
Max
Units
Single row erase/write cycle time
Description
Conditions
–
2
20
ms
EEPROM data retention time, retention Average ambient temp, TA  25 °C,
period measured from last erase cycle 1M erase/program cycles
20
–
–
years
Average ambient temp, TA  55 °C,
100 K erase/program cycles
20
–
–
Average ambient temp. TA 85 °C,
10 K erase/program cycles
10
–
–
Conditions
Min
Typ
Max
Units
1.71
-
5.5
V
11.7.3 Nonvolatile Latches (NVL)
Table 11-43. NVL DC Specifications
Parameter
Description
Erase and program voltage
Vddd pin
Table 11-44. NVL AC Specifications
Parameter
Description
NVL endurance
NVL data retention time
Min
Typ
Max
Units
Programmed at 25°C
Conditions
1K
-
-
program/
erase
cycles
Programmed at 0-70°C
100
-
-
program/
erase
cycles
Programmed at 55°C
20
-
-
years
Programmed at 0-70°C
10
-
-
years
Min
Typ
Max
Units
1.2
-
-
V
Conditions
Min
Typ
Max
Units
-40°C  Ta  85°C and Tj  100°C
DC
-
50
MHz
-40°C  Ta  125°C and Tj  150°C
DC
-
50
MHz
11.7.4 SRAM
Table 11-45. SRAM DC Specifications
Parameter
Vsram
Description
Conditions
SRAM retention voltage
Table 11-46. SRAM AC Specifications
Parameter
Fsram
Description
SRAM operating frequency
Document Number: 001-58402 Rev. *G
Page 109 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.7.5 External Memory Interface
Figure 11-46. Asynchronous Read Cycle Timing
Tcel
EM_ CEn
Taddrv
Taddrh
EM_ Addr
Address
Toel
EM_ OEn
EM_ WEn
Tdoesu
Tdoeh
EM_ Data
Data
Table 11-47. Asynchronous Read Cycle Specifications
Parameter
Description
T
EMIF clock period[47]
Tcel
EM_CEn low time
Taddrv
EM_CEn low to EM_Addr valid
Taddrh
Address hold time after EM_Wen high
Conditions
Vdda  3.3 V
Min
Typ
Max
Units
30.3
–
–
ns
2T – 5
–
2T+ 5
ns
–
–
5
ns
T
–
–
ns
Toel
EM_OEn low time
2T – 5
–
2T + 5
ns
Tdoesu
Data to EM_OEn high setup time
T + 15
–
–
ns
Tdoeh
Data hold time after EM_OEn high
3
–
–
ns
Note
47. Limited by GPIO output frequency, see .
Document Number: 001-58402 Rev. *G
Page 110 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 11-47. Asynchronous Write Cycle Timing
Taddrv
Taddrh
EM_ Addr
Address
Tcel
EM_ CEn
Twel
EM_ WEn
EM_ OEn
Tdweh
Tdcev
EM_ Data
Data
Table 11-48. Asynchronous Write Cycle Specifications
Parameter
Description
period[47]
T
EMIF clock
Tcel
EM_CEn low time
Taddrv
Conditions
Vdda 3.3 V
Min
Typ
Max
Units
30.3
–
–
ns
T–5
–
T+5
ns
EM_CEn low to EM_Addr valid
–
–
5
ns
Taddrh
Address hold time after EM_WEn high
T
–
–
ns
Twel
EM_WEn low time
T–5
–
T+5
ns
Tdcev
EM_CEn low to data valid
–
–
7
ns
Tdweh
Data hold time after EM_WEn high
T
–
–
ns
Document Number: 001-58402 Rev. *G
Page 111 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 11-48. Synchronous Read Cycle Timing
Tcp/2
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddriv
Taddrv
EM_ Addr
Address
Toeld
Toehd
EM_ OEn
Tds
Data
EM_ Data
Tadscld
Tadschd
EM_ ADSCn
Table 11-49. Synchronous Read Cycle Specifications
Parameter
Description
Min
Typ
Max
Units
30.3
–
–
ns
T/2
–
–
ns
EM_CEn low to EM_Clock high
5
–
–
ns
EM_Clock high to EM_CEn high
T/2 – 5
–
–
ns
Taddrv
EM_Addr valid to EM_Clock high
5
–
–
ns
Taddriv
EM_Clock high to EM_Addr invalid
T/2 – 5
–
–
ns
Toeld
EM_OEn low to EM_Clock high
5
–
–
ns
Toehd
EM_Clock high to EM_OEn high
T
–
–
ns
Tds
Data valid before EM_OEn high
T + 15
–
–
ns
Tadscld
EM_ADSCn low to EM_Clock high
5
–
–
ns
Tadschd
EM_Clock high to EM_ADSCn high
T/2 – 5
–
–
ns
T
EMIF clock period[48]
Tcp/2
EM_Clock pulse high
Tceld
Tcehd
Conditions
Vdda 3.3 V
Note
48. Limited by GPIO output frequency, see .
Document Number: 001-58402 Rev. *G
Page 112 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 11-49. Synchronous Write Cycle Timing
Tcp/2
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddriv
Taddrv
EM_ Addr
Address
Tweld
Twehd
EM_ WEn
Tdh
Tds
Data
EM_ Data
Tadschd
Tadscld
EM_ ADSCn
Table 11-50. Synchronous Write Cycle Specifications
Parameter
Description
Period[49]
Conditions
Vdda 3.3 V
Min
Typ
Max
Units
30.3
–
–
ns
T
EMIF clock
Tcp/2
EM_Clock pulse high
T/2
–
–
ns
Tceld
EM_CEn low to EM_Clock high
5
–
–
ns
Tcehd
EM_Clock high to EM_CEn high
T/2 – 5
–
–
ns
Taddrv
EM_Addr valid to EM_Clock high
5
–
–
ns
Taddriv
EM_Clock high to EM_Addr invalid
T/2 – 5
–
–
ns
Tweld
EM_WEn low to EM_Clock high
5
–
–
ns
Twehd
EM_Clock high to EM_WEn high
T/2 – 5
–
–
ns
Tds
Data valid before EM_Clock high
5
–
–
ns
Tdh
Data invalid after EM_Clock high
T
–
–
ns
Tadscld
EM_ADSCn low to EM_Clock high
5
–
–
ns
Tadschd
EM_Clock high to EM_ADSCn high
T/2 – 5
–
–
ns
Note
49. Limited by GPIO output frequency, see .
Document Number: 001-58402 Rev. *G
Page 113 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.8 PSoC System Resources
Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except
where noted.
11.8.1 POR with Brown Out
For brown out detect in regulated mode, Vddd and Vdda must be  2.0 V. Brown out detect is available in externally regulated mode.
Table 11-51. Precise Power On Reset (PRES) with Brown Out DC Specifications
Parameter
Description
PRESR
Rising trip voltage
PRESF
Falling trip voltage
Conditions
Factory trim
Min
1.64
1.62
Typ
–
–
Max
1.68
1.66
Units
V
V
Min
–
–
Typ
–
5
Max
0.5
–
Units
µs
V/sec
Min
Typ
Max
Units
1.68
1.89
2.14
2.38
2.62
2.87
3.11
3.35
3.59
3.84
4.08
4.32
4.56
4.83
5.05
5.30
5.57
1.73
1.95
2.20
2.45
2.71
2.95
3.21
3.46
3.70
3.95
4.20
4.45
4.70
4.98
5.21
5.47
5.75
1.77
2.01
2.27
2.53
2.79
3.04
3.31
3.56
3.81
4.07
4.33
4.59
4.84
5.13
5.37
5.63
5.92
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Min
Typ
Max
Units
–
–
1
µs
Table 11-52. Precise Power On Reset (PRES) with Brown Out AC Specifications
Parameter
Description
PRES_TR Response time
VDDD/VDDA droop rate
Conditions
Sleep mode
11.8.2 Voltage Monitors
Table 11-53. Voltage Monitors DC Specifications
Parameter
Description
LVI
Trip voltage
LVI_A/D_SEL[3:0] = 0000b
LVI_A/D_SEL[3:0] = 0001b
LVI_A/D_SEL[3:0] = 0010b
LVI_A/D_SEL[3:0] = 0011b
LVI_A/D_SEL[3:0] = 0100b
LVI_A/D_SEL[3:0] = 0101b
LVI_A/D_SEL[3:0] = 0110b
LVI_A/D_SEL[3:0] = 0111b
LVI_A/D_SEL[3:0] = 1000b
LVI_A/D_SEL[3:0] = 1001b
LVI_A/D_SEL[3:0] = 1010b
LVI_A/D_SEL[3:0] = 1011b
LVI_A/D_SEL[3:0] = 1100b
LVI_A/D_SEL[3:0] = 1101b
LVI_A/D_SEL[3:0] = 1110b
LVI_A/D_SEL[3:0] = 1111b
HVI
Trip voltage
Conditions
Table 11-54. Voltage Monitors AC Specifications
Parameter
Description
Response time[50]
Conditions
Note
50. Based on device characterization (Not production tested).
Document Number: 001-58402 Rev. *G
Page 114 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.8.3 Interrupt Controller
Table 11-55. Interrupt Controller AC Specifications
Parameter
Description
Conditions
Delay from Interrupt signal input to ISR Includes worse case completion of
code execution from ISR code
longest instruction DIV with 6
cycles
Min
-
Typ
-
Max
25
Units
Tcy CPU
11.8.4 JTAG Interface
Table 11-56. JTAG Interface AC Specifications[25]
Parameter
f_TCK
Description
TCK frequency
Conditions
3.3 V  VDDD  5 V
1.71 V  VDDD < 3.3 V
T_TDI_setup
TDI setup before TCK high
T_TMS_setup
T_TDI_hold
T_TDO_valid
T_TDO_hold
TMS setup before TCK high
TDI, TMS hold after TCK high
TCK low to TDO valid
TDO hold after TCK high
T = 1/f_TCK max
T = 1/f_TCK max
T = 1/f_TCK max
Min
–
–
(T/10) –
5
T/4
T/4
–
T/4
Typ
–
–
–
Max
14[51]
7[51]
–
–
–
–
–
–
–
2T/5
–
Units
MHz
MHz
ns
Figure 11-50. JTAG Interface Timing
(1/f_TCK)
TCK
T_TDI_setup
T_TDI_hold
TDI
T_TDO_valid
T_TDO_hold
TDO
T_TMS_setup
T_TMS_hold
TMS
Document Number: 001-58402 Rev. *G
Page 115 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.8.5 SWD Interface
Table 11-57. SWD Interface AC Specifications[25]
Parameter
f_SWDCK
Description
SWDCLK frequency
Conditions
3.3 V  VDDD  5 V
1.71 V  VDDD < 3.3 V
1.71 V  VDDD < 3.3 V,
SWD over USBIO pins
T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max
T_SWDI_hold SWDIO input hold after SWDCK high
T = 1/f_SWDCK max
T_SWDO_valid SWDCK high to SWDIO output
T = 1/f_SWDCK max
Min
–
–
–
Typ
–
–
–
Max
14[52]
7[52]
5.5[52]
T/4
T/4
–
–
–
–
–
–
2T/5
Units
MHz
MHz
MHz
Figure 11-51. SWD Interface Timing
(1 /f_S W D C K )
SW DCK
T_ S W D I_ setup T_ S W D I_hold
S W D IO
(P S oC input)
T _S W D O _valid
T_S W D O _hold
S W D IO
(P S oC output)
11.8.6 SWV Interface
Table 11-58. SWV Interface AC Specifications[25]
Parameter
Description
SWV mode SWV bit rate
Conditions
Min
Typ
Max
Units
-
-
33
Mbit
Notes
51. f_TCK must also be no more than 1/3 CPU clock frequency.
52. f_SWDCK must also be no more than 1/3 CPU clock frequency.
Document Number: 001-58402 Rev. *G
Page 116 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.9 Clocking
Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except
where noted.
11.9.1 Internal Main Oscillator
Table 11-59. IMO DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
62.6 MHz
–
–
600
µA
48 MHz
–
–
500
µA
–
–
500
µA
–
–
300
µA
Supply current
24 MHz – USB mode
With oscillator locking to USB bus
24 MHz – non USB mode
12 MHz
–
–
200
µA
6 MHz
–
–
180
µA
3 MHz
–
–
150
µA
Figure 11-52. IMO Current vs. Frequency
Document Number: 001-58402 Rev. *G
Page 117 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 11-60. IMO AC Specifications
Parameter
FIMO
Description
Conditions
IMO frequency stability (with factory trim)
62.6 MHz
48 MHz
24 MHz – Non USB mode
24 MHz – USB mode
With oscillator locking to USB bus
12 MHz
6 MHz
3 MHz
From enable (during normal system
Startup time[53]
operation)
Min
Typ
Max
Units
–7
–5
–4
–0.25
–3
–2
–2
–
–
–
–
–
–
–
–
–
7
5
4
0.25
3
2
2
13
%
%
%
%
%
%
%
µs
–
–
0.9
1.6
–
–
ns
ns
–
–
0.9
12
–
–
ns
ns
Jitter (peak to peak)[53]
Jp–p
Jperiod
F = 24 MHz
F = 3 MHz
Jitter (long term)[53]
F = 24 MHz
F = 3 MHz
Note
53. Based on device characterization (Not production tested).
Document Number: 001-58402 Rev. *G
Page 118 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 11-53. IMO Frequency Variation vs. Temperature
Figure 11-54. IMO Frequency Variation vs. VCC
Document Number: 001-58402 Rev. *G
Page 119 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.9.2 Internal Low Speed Oscillator
Table 11-61. ILO DC Specifications
Parameter
Description
Conditions
Operating current[54]
ICC
Leakage
current[54]
Min
Typ
Max
Units
FOUT = 1 kHz
–
–
1.7
µA
FOUT = 33 kHz
–
–
2.6
µA
FOUT = 100 kHz
–
–
2.6
µA
-40°C  Ta  85°C and Tj  100°C
-
2.0
15
nA
-
-
200
nA
Min
-
Typ
-
Max
2
Units
ms
45
0.5
100
1
200
2
kHz
kHz
30
0.3
100
1
300
3.5
kHz
kHz
45
0.5
-
450
5
kHz
kHz
150
0.3
-
500
6.5
kHz
kHz
Power down mode
Leakage current[54]
-40°C  Ta  125°C and Tj  150°C
Power down mode
Table 11-62. ILO AC Specifications
Parameter
Filo
Filo
Description
Startup time
ILO frequencies (trimmed)
100 kHz
1 kHz
ILO frequencies (untrimmed)
100 kHz
1 kHz
ILO frequencies (trimmed)
100 kHz
1 kHz
ILO frequencies (untrimmed)
100 kHz
1 kHz
Conditions
Turbo mode
-40°C  Ta  85°C and Tj  100°C
-40°C  Ta  85°C and Tj  100°C
-40°C  Ta  125°C and Tj  150°C
-40°C  Ta  125°C and Tj  150°C
Figure 11-55. ILO Frequency Variation vs. VDD
Note
54. This value is calculated, not measured.
55. Based on device characterization (Not production tested).
Document Number: 001-58402 Rev. *G
Page 120 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
11.9.3 External Crystal Oscillator
Table 11-63. 32 kHz External Crystal DC Specifications[56]
Conditions
Min
Typ
Max
Units
Icc
Parameter
Operating current
Description
Low power mode; CL = 6 pF;
-40°C  Ta  125°C and Tj  150°C
–
0.25
1.0
µA
DL
Drive level
Low-power mode; CL = 6 pF
–
–
1
µW
Min
Typ
Max
Units
Table 11-64. 32 kHz External Crystal AC Specifications
Parameter
Description
F
Frequency
Ton
Startup time
Conditions
–
32.768
–
kHz
–
1
–
s
Conditions
Min
4
Typ
–
Max
25
Units
MHz
Conditions
Measured at VDDIO/2
VIL to VIH
Min
0
30
0.51
Typ
–
50
–
Max
33
70
–
Units
MHz
%
V/ns
Conditions
In = 3 MHz, Out = 24 MHz
Min
–
Typ
200
Max
–
Units
µA
Conditions
Output of Prescalar
Min
1
1
24
24
-
Typ
-
Max
48
3
50
50
250
250
400
Units
MHz
MHz
MHz
MHz
µs
ps
ps
High power mode
Table 11-65. MHz ECO AC Specifications
Parameter
Description
F
Crystal frequency range
11.9.4 External Clock Reference
Table 11-66. External Clock Reference AC Specifications
Parameter
Description
External frequency range
Input duty cycle range
Input edge rate
11.9.5 Phase-Locked Loop
Table 11-67. PLL DC Specifications
Parameter
Description
IDD
PLL operating current
Table 11-68. PLL AC Specifications
Parameter
Description
Fpllin
PLL input frequency[57]
PLL intermediate frequency[58]
Fpllout
PLL output frequency[57]
Lock time at startup
Jperiod-rms Jitter (rms)[25]
-40°C  Ta  85°C and Tj  100°C
-40°C  Ta  125°C and Tj  150°C
-40°C  Ta  85°C and Tj  100°C
-40°C  Ta  125°C and Tj  150°C
Notes
56. Based on device characterization (not production tested).
57. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
58. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
Document Number: 001-58402 Rev. *G
Page 121 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
12. Ordering Information
In addition to the features listed in Table 12-1, every CY8C32 device includes: a precision on-chip voltage reference, precision
oscillators, Flash, ECC, DMA, a fixed function I2C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface,
and more. In addition to these features, the flexible UDBs and Analog Subsection support a wide range of peripherals. To assist you
in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application.
All CY8C32 derivatives incorporate device and Flash security in user-selectable security levels; see TRM for details.
Table 12-1. CY8C32 Family with Single Cycle 8051
LCD Segment Drive
DAC
Comparator
SC/CT Analog Blocks
Opamps
CapSense
UDBs
16-bit Timer/PWM
FS USB
CAN 2.0b
Total I/O
GPIO
SIO
USBIO
CY8C3244PVA-133
50
16
2
0.5
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
16
4
–
–
29
25
4
0
48-SSOP
✔
–40 to 85
0x1E085069
CY8C3244AXA-153
50
16
2
0.5
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
16
4
–
–
70
62
8
0 100-TQFP
✔
–40 to 85
0x1E099069
CY8C3245PVA-134
50
32
4
1
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
20
4
–
–
29
25
4
0
48-SSOP
✔
–40 to 85
0x1E086069
CY8C3245PVE-134
50
32
4
1
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
20
4
–
–
29
25
4
0
48-SSOP
✔
–40 to 125
0x1E086069
CY8C3245PVA-150
50
32
4
1
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
20
4
✔
–
31
25
4
2
48-SSOP
✔
–40 to 85
0x1E096069
CY8C3245AXA-158
50
32
4
1
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
20
4
–
–
70
62
8
0 100-TQFP
✔
–40 to 85
0x1E09E069
CY8C3245AXA-166
50
32
4
1
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
20
4
✔
–
72
62
8
2 100-TQFP
✔
–40 to 85
0x1E0A6069
CY8C3246PVA-122
50
64
8
2
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
24
4
–
–
29
25
4
0
48-SSOP
✔
–40 to 85
0x1E07A069
CY8C3246AXA-131
50
64
8
2
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
24
4
–
–
70
62
8
0 100-TQFP
✔
–40 to 85
0x1E083069
CY8C3246AXA-138
50
64
8
2
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
24
4
✔
–
72
62
8
2 100-TQFP
✔
–40 to 85
0x1E08A069
CY8C3246PVA-147
50
64
8
2
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
24
4
✔
–
31
25
4
2
48-SSOP
✔
–40 to 85
0x1E093069
CY8C3246PVE-147
50
64
8
2
✔ 12-bit
Del-Sig
1
2
0
0
– ✔
24
4
✔
–
31
25
4
2
48-SSOP
✔
–40 to 125
0x1E093069
DFB
EEPROM (KB)
Package
Part Number
ADC
SRAM (KB)
Digital
Flash (KB)
Analog
CPU Speed (MHz)
MCU Core
AECQ100
Temperature Range
(°C)
JTAG ID
16 KB Flash
32 KB Flash
64 KB Flash
Notes
59. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See the “Example Peripherals” section on page 40 for more information on how UDBs may be used.
60. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the ““I/O System and Routing” section on page 33” for details on the functionality
of each of these types of I/O.
61. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
Document Number: 001-58402 Rev. *G
Page 122 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
12.1 Part Numbering Conventions
PSoC 3 devices follow the part numbering convention described below. All fields are single character alphanumeric (0, 1, 2, …, 9, A,
B, …, Z) unless stated otherwise.
CY8Cabcdefg-xxx
 a: Architecture
 ef: Package Code
3: PSoC 3
 5: PSoC 5
Two character alphanumeric
AX: TQFP
 LT: QFN
 PV: SSOP



 b: Family Group within Architecture
2: CY8C32 family
4: CY8C34 family
 6: CY8C36 family
 8: CY8C38 family

 g: Temperature Range

C: commercial 0°C to 70°C
I: industrial -40°C to 85°C
 A: automotive -40°C to 85°C
 E: extended -40°C to 125°C


 c: Speed Grade

4: 50 MHz
 xxx: Peripheral Set
 d: Flash Capacity

4: 16 KB
 5: 32 KB
 6: 64 KB


Three character numeric
No meaning is associated with these three characters.
Example
CY8C
3 2 4 6 PPVV A
I -
x x x
Cypress Prefix
3: PSoC 3
2: CY8C32 Family
Architecture
Family Group within Architecture
4: 50
48 MHz
MHz
Speed Grade
6: 64 KB
Flash Capacity
PV: SSOP
Package Code
A Industrial
= Automotive; E = Extended Automotive
I:
Temperature Range
Peripheral Set
All devices in the PSoC 3 CY8C32 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free
products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress
uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.
A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package
Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the
absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other "end of
life" requirements.
Document Number: 001-58402 Rev. *G
Page 123 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
13. Packaging
Table 13-1. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
–40
25.00
125
°C
TJ
Operating junction temperature
–40
–
150
°C
TJA
Package JA (48-pin SSOP)
–
49
–
°C/W
TJA
Package JA (100-pin TQFP)
–
34
–
°C/W
TJC
Package JC (48-pin SSOP)
–
24
–
°C/W
TJC
Package JC (100-pin TQFP)
–
10
–
°C/W
Table 13-2. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at Peak
Temperature
48-pin SSOP
260 °C
30 seconds
100-pin TQFP
260 °C
30 seconds
Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
48-pin SSOP
MSL 3
100-pin TQFP
MSL 3
Figure 13-1. 48-pin (300 mil) SSOP Package Outline
51-85061 *F
Document Number: 001-58402 Rev. *G
Page 124 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Figure 13-2. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline
51-85048 *I
Document Number: 001-58402 Rev. *G
Page 125 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
14. Acronyms
Table 14-1. Acronyms Used in this Document (continued)
Table 14-1. Acronyms Used in this Document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
API
application programming interface
Acronym
Description
GPIO
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
IC
integrated circuit
IDAC
current DAC, see also DAC, VDAC
IDE
integrated development environment
I2C,
or IIC
IIR
Inter-Integrated Circuit, a communications
protocol
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
IPSR
interrupt program status register
IRQ
interrupt request
ITM
instrumentation trace macrocell
APSR
application program status register
ARM®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CMRR
common-mode rejection ratio
CPU
central processing unit
CRC
cyclic redundancy check, an error-checking
protocol
LCD
liquid crystal display
DAC
digital-to-analog converter, see also IDAC, VDAC
LIN
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
Local Interconnect Network, a communications
protocol.
LR
link register
DMA
direct memory access, see also TD
LUT
lookup table
DNL
differential nonlinearity, see also INL
LVD
low-voltage detect, see also LVI
DNU
do not use
LVI
low-voltage interrupt, see also HVI
DR
port write data registers
LVTTL
low-voltage transistor-transistor logic
DSI
digital system interconnect
MAC
multiply-accumulate
DWT
data watchpoint and trace
MCU
microcontroller unit
ECC
error correcting code
MISO
master-in slave-out
ECO
external crystal oscillator
NC
no connect
EEPROM
electrically erasable programmable read-only
memory
NMI
nonmaskable interrupt
EMI
electromagnetic interference
NRZ
non-return-to-zero
EMIF
external memory interface
NVIC
nested vectored interrupt controller
EOC
end of conversion
NVL
nonvolatile latch, see also WOL
EOF
end of frame
PAL
programmable array logic, see also PLD
EPSR
execution program status register
PC
program counter
ESD
electrostatic discharge
PCB
printed circuit board
ETM
embedded trace macrocell
PHUB
peripheral hub
FIR
finite impulse response, see also IIR
PHY
physical layer
FPB
flash patch and breakpoint
PICU
port interrupt control unit
FS
full-speed
PLA
programmable logic array
PLD
programmable logic device, see also PAL
Document Number: 001-58402 Rev. *G
Page 126 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
PLL
phase-locked loop
SR
slew rate
PMDD
package material declaration data sheet
SRAM
static random access memory
POR
power-on reset
SRES
software reset
PRES
precise low-voltage reset
SWD
serial wire debug, a test protocol
PRS
pseudo random sequence
SWV
single-wire viewer
PS
port read data register
TD
transaction descriptor, see also DMA
PSoC®
Programmable System-on-Chip™
THD
total harmonic distortion
PSRR
power supply rejection ratio
TRM
technical reference manual
PWM
pulse-width modulator
TTL
transistor-transistor logic
RAM
random-access memory
TX
transmit
RISC
reduced-instruction-set computing
UART
RMS
root-mean-square
Universal Asynchronous Transmitter Receiver, a
communications protocol
RTC
real-time clock
UDB
universal digital block
RTL
register transfer language
USB
Universal Serial Bus
RTR
remote transmission request
USBIO
RX
receive
USB input/output, PSoC pins used to connect to
a USB port
SAR
successive approximation register
VDAC
voltage DAC, see also DAC, IDAC
SCL
I2C serial clock
SDA
I2C serial data
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
Document Number: 001-58402 Rev. *G
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
15. Reference Documents
PSoC® 3, PSoC® 5 Architecture TRM
PSoC® 3 Registers TRM
Page 127 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
16. Document Conventions
16.1 Units of Measure
Table 16-1. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibels
fF
femtofarads
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohours
kHz
kilohertz
k
kilohms
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
megaohms
Msps
megasamples per second
µA
microamperes
µF
microfarads
µH
microhenrys
µs
microseconds
µV
microvolts
µW
microwatts
mA
milliamperes
ms
milliseconds
mV
millivolts
nA
nanoamperes
ns
nanoseconds
nV
nanovolts

ohms
pF
picofarads
ppm
parts per million
ps
picoseconds
s
seconds
sps
samples per second
sqrtHz
square root of hertz
V
volts
Document Number: 001-58402 Rev. *G
Page 128 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
17. Revision History
Description Title: PSoC® 3: CY8C32 Automotive Family Datasheet, Programmable System-on-Chip (PSoC®)
Document Number: 001-58402
Revision
ECN
Submission
Date
Orig. of
Change
**
2921624
04/26/2010
MKEA
New data sheet for CY8C32
*A
3347549
08/17/2011
SECA
Moved status from Preliminary to Advance.
Updated Table 12-1, “CY8C32 Family with Single Cycle 8051,” on page 122.
Updated package diagram spec 51-85048 to *E revision.
*B
3490494
01/11/2012
GIR
*C
3994954
05/08/2013
KPAT
Updated all tables in Electrical Specifications.
Updated Ordering Information (Updated part numbers, JTAG ID).
Removed all references of Vboost across the document.
*D
4040790
06/27/2013
RASB
Changed status from Preliminary to Final.
Updated General Description.
Updated Features.
Updated Architectural Overview.
Updated Pinouts.
Updated Pin Descriptions.
Updated CPU.
Updated Memory.
Updated System Integration.
Updated Digital Subsystem.
Updated Analog Subsystem.
Updated Electrical Specifications.
Document Number: 001-58402 Rev. *G
Description of Change
Updated Figure 6-7 on page 34
Page 129 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
17. Revision History (continued)
Description Title: PSoC® 3: CY8C32 Automotive Family Datasheet, Programmable System-on-Chip (PSoC®)
Document Number: 001-58402
Revision
ECN
Submission
Date
Orig. of
Change
*E
4109902
09/02/2013
NFB /
ANMD
Description of Change
Updated Features.
Updated Architectural Overview:
Added Note 3 and referred the same note in features in “The heart of the analog
subsystem is a fast, accurate, configurable delta-sigma ADC with these
features”.
Updated Pinouts:
Updated Figure 2-5.
Updated Memory:
Updated EEPROM:
Updated description.
Updated Nonvolatile Latches (NVLs):
Updated Table 5-2 and Table 5-3.
Updated Memory Map:
Updated I/O Port SFRs:
Updated xdata Space:
Updated Table 5-5.
Updated Digital Subsystem:
Updated Universal Digital Block:
Updated PLD Module:
Updated Figure 7-3.
Updated I2C:
Updated description.
Updated Electrical Specifications:
Updated Device Level Specifications:
Updated Table 11-2.
Updated Inputs and Outputs:
Updated GPIO:
Removed figure “GPIO Output Rise and Fall Times, Fast Strong Mode,
VDDIO = 3.3 V, 25 pF Load” and figure “GPIO Output Rise and Fall Times, Slow
Strong Mode, VDDIO = 3.3 V, 25 pF Load”.
Updated Analog Peripherals:
Updated Delta-Sigma ADC:
Updated Table 11-15.
Updated Table 11-16.
Updated Voltage Reference:
Updated Table 11-18.
Updated Memory:
Updated Flash:
Updated Table 11-40.
Updated Packaging:
spec 51-85048 – Changed revision from *G to *H.
Updated in new template.
Document Number: 001-58402 Rev. *G
Page 130 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
17. Revision History (continued)
Description Title: PSoC® 3: CY8C32 Automotive Family Datasheet, Programmable System-on-Chip (PSoC®)
Document Number: 001-58402
Revision
ECN
Submission
Date
Orig. of
Change
*F
4174912
10/26/2013
NFB /
ANMD
Description of Change
Updated Pinouts:
Added Note 6 and referred the same note in 100 mA in description.
Updated Electrical Specifications:
Updated Absolute Maximum Ratings:
Updated Table 11-1.
Added Note 13 and referred the same note in Table 11-1.
Added Note 15 and referred the same note in Ivddio parameter in Table 11-1.
Updated Analog Peripherals:
Updated Voltage Reference:
Updated Table 11-18.
Updated Packaging:
Updated Table 13-1.
*G
4296459
03/03/2014
ANMD
Updated Digital Subsystem:
Updated I2C:
Updated Note 12.
Updated Electrical Specifications:
Updated Analog Peripherals:
Updated Delta-Sigma ADC:
Updated Table 11-15:
Updated Conditions of Vos parameter.
Updated Memory:
Updated Flash:
Updated Table 11-40:
Added Note 46 and referred the same note in “Flash data retention time,
retention period measured from last erase cycle” in description column.
Replaced “Tjavg” with “TA” in last row in conditions column.
Updated Packaging:
spec 51-85048 – Changed revision from *H to *I.
Document Number: 001-58402 Rev. *G
Page 131 of 132
PSoC® 3: CY8C32
Automotive Family Datasheet
18. Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
cypress.com/go/automotive
Clocks & Buffers
cypress.com/go/clocks
Interface
cypress.com/go/interface
Lighting & Power Control
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/touch
USB Controllers
cypress.com/go/USB
Wireless/RF
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2010-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-58402 Rev. *G
®
®
®
®
Revised March 3, 2014
®
Page 132 of 132
CapSense , PSoC 3, PSoC 5, and PSoC Creator™ are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. ARM is a registered trademark, and Keil, and RealView
are trademarks, of ARM Limited. All other trademarks or registered trademarks referenced herein are property of the respective corporations.