Document No.001-87920 Rev. *A ECN # 4039000 Cypress Semiconductor Product Qualification Report QTP# 98462 June 2013 FAST ASYNCHRONOUS SRAM FAMILY R5D-5R TECHNOLOGY, FAB 4 CY7C106B/CY7C1006B 256K x 4 Static RAM CY7C109B/ CY7C1009B 128K x 8 Static RAM CY7C194B/ CY7C195B 32K x 8 Static RAM CY7C199C 32K x 8 Static RAM CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Zhaomin Ji Principal Reliability Engineer (408) 432-7021 Mira Ben-Tzur Quality Engineering Director (408) 943-2675 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 1 of 10 Document No.001-87920 Rev. *A ECN # 4039000 PRODUCT QUALIFICATION HISTORY Qual Report Description of Qualification Purpose Date Comp 000301 New Technology Derivative R52D-5R / New CY7C149B, 4Meg Async SRAM Product. Apr 00 98462 New CY7C109B, 1Meg Asynchronous SRAM Product and its product family. Apr 00 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 2 of 10 Document No.001-87920 Rev. *A ECN # 4039000 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: Qualifies CY7C109B and its product family in qualified R52D-5R Technology , Fab 4. Marketing Part #: CY7C106B/CY7C1006B/CY7C109B/CY7C1009B/CY7C194/5/7B/CY7C199C Device Description: 5V, Commercial, Industrial, available in 28/32-lead SOJ and28/ 32-lead TSOP, 28-lead DIP package Cypress Division: Cypress Semiconductor Corporation – Memory Product Division (MPD) Overall Die (or Mask) REV Level (pre-requisite for qualification): Rev. M What ID markings on Die: 7C109A/7C106A TECHNOLOGY/FAB PROCESS DESCRIPTION - R52D-5R Number of Metal Layers: 2 Metal Metal 1: 500Å TiW/6,000Å Al-0.5%Cu/300Å TiW Composition: Metal 2: 300Å CoTi/8,000Å Al-0.5%Cu/300Å TiW Passivation Type and Materials: 1000Å PECVD oxide / 9000Å Si2N4 Free Phosphorus contents in top glass layer(%): 0% Number of Transistors in Device 7 million Number of Gates in Device 1.5 million Generic Process Technology/Design Rule (-drawn):CMOS, Double Metal /0.25 m/0.3 FETS Gate Oxide Material/Thickness (MOS): 55 Å Name/Location of Die Fab (prime) Facility: Cypress Semiconductor -- Bloomington, MN Die Fab Line ID/Wafer Process ID: Fab4/R52D-5R PACKAGE AVAILABILITY PACKAGE ASSEMBLY SITE FACILITY 32-lead TSOP TAI WN-T 28- 32 lead SOJ AMKOR –PHIL, JCET- CHINA Note: Package Qualification details upon request Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 3 of 10 Document No.001-87920 Rev. *A ECN # 4039000 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: Mold Compound Flammability Rating: V32311 32-lead Plastic Small Outline J-Bend Package (SOJ) Hitachi CEL9200 V-O per UL94 Oxygen Rating Index: >28% Lead Frame Material: Copper Lead Finish, Composition / Thickness: Solder Plated 85%Sn, 15%Pb Die Backside Preparation Method/Metallization: N/A Die Separation Method: Wafer Saw Die Attach Supplier: Ablestik Die Attach Material: Ablestik 8361H Wire Bond Method: Thermosonic Wire Material/Size: Au, 1.0um Thermal Resistance Theta JA °C/W: 58°C/W Package Cross Section Yes/No: N/A Name/Location of Assembly (prime) facility: CML (R) ELECTRICAL TEST / FINISH DESCRIPTION Test Location: KYEC, TAIWAN Fault Coverage: 100% Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 4 of 10 Document No.001-87920 Rev. *A ECN # 4039000 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT Test Condition (Temp/Bias) Stress/Test Result P/F P Early Failure Rate Dynamic Operating Condition, Vcc Max = 3.8V, 150C Dynamic Operating Condition, Vcc Max = 5.75V, 150C High Temperature Operating Life Dynamic Operating Condition, Vcc Max = 3.8V, 150C P Latent Failure Rate Dynamic Operating Condition, Vcc Max = 5.75V, 150C High Accelerated Saturation Test (HAST) 130C, 5.5V,85%RH Precondition: JESD22 Moisture Sensitivity MSL3 192 Hrs, 30C/60%RH+3IR-Reflow, 220C+5, 0C P Temperature Cycle MIL-STD-883C, Method 1010, Condition C, -65C to 150C Precondition: JESD22 Moisture Sensitivity MSL3 192 Hrs, 30C/60%RH+3IR-Reflow, 220C+5, 0C P Pressure Cooker 121C, 100%RH Precondition:JESD22 Moisture Sensitivity MSL3 192 Hrs, 30C/60%RH+3IR-Reflow, 220C+5, 0C P High Temperature Storage 150C, No Bias P High Temperature Steady State life 150C, 5.5V, Vcc Max P Electrostatic Discharge Human Body Model (ESD-HBM) 2,200V JESD22, Method A114-B P Electrostatic Discharge Charge Device Model (ESD-CDM) 500V JESD22-C101 P Age Bond Pull MIL-STD-883, Method 883-2011 – 200C, 4hrs P Current Density Meets the Technology Device Level Reliability Specifications P Low Temperature Operating Life -30C, 6.5V, 8MHZ P Acoustic Microscopy, Level 3 J-STD-020 P SEM MIL-STD-883, Method 883-2018-2 P Static Latchup Sensitivity In accordance with JEDEC 17 (300mA) P Dynamic Latchup Sensitivity In accordance with JEDEC 17. (8.5V) P High Temperature Operating Life Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 5 of 10 Document No.001-87920 Rev. *A ECN # 4039000 RELIABILITY FAILURE RATE SUMMARY Stress/Test High Temperature Operating Life Early Failure Rate1 High Temperature Operating Life2,3 Long Term Failure Rate 1 2 3 4 Device Tested/ Device Hours # Fails Activation Energy Thermal Failure Rate AF4 4,502 1 N/A N/A 222 PPM 1,057,400 DHRs 0 0.7 170 5 FIT A production burn-in of 24 Hrs at 150C, 4.5V is required for the product. Assuming an ambient temperature of 55C and a junction temperature rise of 15C. Chi-squared 60% estimations used to calculate the failure rate. Thermal Acceleration Factor is calculated from the Arrhenius equation E 1 1 AF = exp A - k T2 T1 where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 6 of 10 Document No.001-87920 Rev. *A ECN # 4039000 Reliability Test Data QTP #:000301 Device STRESS: Fab Lot # 4919497 4919497 Failure Mechanism 619925326 CSPI-R COMP 3 0 619925326 CSPI-R COMP 3 0 STATIC LATCH-UP TESTING (125C, 11.5V, ± 300mA) CY7C1049B-VC (7C1549C) 4946002 STRESS: Samp Rej ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015 (4,400V) CY7C1049B (7C1549C) STRESS: Assy Loc Duration ESD-CHARGE DEVICE MODEL (1,000V) CY7C1049B (7C1549C) STRESS: Assy Lot # 610004242 CSPI-R COMP 3 0 CSPI-R COMP 3 0 DYNAMIC LATCH-UP TESTING (8.2V) CY7C1049B-VC (7C1549C) 4946002 610004242 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE (150C, 5.75V) CY7C1049B-VC (7C1549C) 4944781 610003706 CSPI-R 48 1000 1 CY7C1049B-VC (7C1549C) 4946002 610004242 CSPI-R 48 1000 0 CY7C1049B-VC (7C1549C) 4941240 619938804 CSPI-R 48 1000 0 Particle STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE (150C, 5.75V) CY7C1049B-VC (7C1549C) 4944781 610003706 CSPI-R 80 530 0 CY7C1049B-VC (7C1549C) 4944781 610003706 CSPI-R 500 529 0 CY7C1049B-VC (7C1549C) 4946002 610004242 CSPI-R 80 530 0 CY7C1049B-VC (7C1549C) 4946002 610004242 CSPI-R 500 529 0 CY7C1049B-VC (7C1549C) 4941240 619938804 CSPI-R 80 530 0 CY7C1049B-VC (7C1549C) 4941240 619938804 CSPI-R 500 527 0 STRESS: HIGH TEMP STEADY STATE LIFE TEST (150C, 5.5V, Vcc MAX) CY7C1049B (7C1549C) 4919497 619925326 CSPI-R 80 80 0 CY7C1049B (7C1549C) 4919497 619925326 CSPI-R 168 80 0 CSPI-R 500 46 0 STRESS:LOW TEMPERATURE OPERATING LIFE (-30C, 6.50V) CY7C1049B (7C1549C) STRESS: 4919497 619925326 HIGH TEMPERATURE STORAGE, (150C) CY7C1049B (7C1549C) 4919497 619925326 CSPI-R 336 48 0 CY7C1049B (7C1549C) 4919497 619925326 CSPI-R 500 48 0 CY7C1049B (7C1549C) 4919497 619925326 CSPI-R 1000 48 0 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 7 of 10 Document No.001-87920 Rev. *A ECN # 4039000 Reliability Test Data QTP #:000301 Device STRESS: Fab Lot # Assy Lot # Assy Loc Duration Samp Rej HI-ACCEL SATURATION TEST (130C, 85%RH, 5.5V), PRE COND 192 HR 30C/60%RH CY7C1049B (7C1549C) 4919497 619925326 CSPI-R 128 47 0 CY7C1049B (7C1549C) 4944781 610003706 CSPI-R 128 49 0 STRESS: PRESSURE COOKER TEST (121C, 100%RH), PRE COND 192 HR 30C/60%RH CY7C1049B (7C1549C) 4919497 619925326 CSPI-R 168 48 0 CY7C1049B (7C1549C) 4920692 619933105 CSPI-R 168 47 0 STRESS: Failure Mechanism TC COND. C -65C TO 150C, PRECONDITION 192 HRS 30C/60%RH (MSL3) CY7C1049B (7C1549C) 4919497 619925326 CSPI-R 300 48 0 CY7C1049B (7C1549C) 4919497 619925326 CSPI-R 500 48 0 CY7C1049B (7C1549C) 4920692 619933105 CSPI-R 300 47 0 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 8 of 10 Document No.001-87920 Rev. *A ECN # 4039000 Reliability Test Data QTP #:98462 Device Fab Lot # Assy Lot # Assy Loc Duration 4943568 619936792 CSPI-R COMP Samp Rej Failure Mechanism STRESS: ACOUSTIC-MSL3 CY7C109B-VC (7C109M) STRESS: CSPI-R COMP 5 0 4943568 619936792 CSPI-R COMP 3 0 4943568 619936792 COMP 3 0 CSPI-R HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE (150C, 3.8V, Vcc Max) CY7C109B-VC (7C109M) STRESS: 619936792 STATIC LATCH-UP TESTING (125C, 11.5V, ± 300mA) CY7C109B-VCB (7C109M) STRESS: 4943568 DYNAMIC LATCH-UP TESTING (8.5V) CY7C109B-VCB (7C109M) STRESS: 0 AGE BOND PULL TEST CY7C109B-VCB (7C109M) STRESS: 15 4943568 619936792 CSPI-R 48 1502 0 HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE (150C, 3.8V, Vcc Max) CY7C1009B-VC (7C1009M) 4943568 619936792 CSPI-R 80 529 0 CY7C1009B-VC (7C1009M) 4943568 619936792 CSPI-R 500 529 0 STRESS: HIGH TEMP STEADY STATE LIFE TEST (150C, 5.5V, Vcc MAX) CY7C1009B-VC (7C1009M) 4943568 619936792 CSPI-R 80 80 0 CY7C1009B-VC (7C1009M) 4943568 619936792 CSPI-R 168 80 0 CSPI-R COMP 3 0 8 0 STRESS: ESD-CHARGE DEVICE MODEL (1,000V) CY7C109B-VCB (7C109M) STRESS: 4943568 619936792 CSPI-R COMP HI-ACCEL SATURATION TEST (130C, 85%RH, 5.5V), PRE COND 192 HR 30C/60%RH CY7C1009B-VC (7C1009M) STRESS: 619936792 ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015 (2,200V) CY7C109B-VCB (7C109M) STRESS: 4943568 4943568 619936792 CSPI-R 128 50 0 HIGH TEMPERATURE STORAGE, PLASTIC, 150C CY7C1009B-VC (7C1009M) 4943568 619936792 CSPI-R 500 50 0 CY7C1009B-VC (7C1009M) 4943568 619936792 CSPI-R 1000 50 0 51 0 STRESS: PRESSURE COOKER TEST (121C, 100%RH), PRE COND 192 HR 30C/60%RH CY7C1009B-VC (7C1009M) STRESS: 4943568 619936792 CSPI-R 168 TC COND. C -65C TO 150C, PRECONDITION 192 HRS 30C/60%RH (MSL3) CY7C1009B-VC (7C1009M) 4943568 619936792 CSPI-R 300 50 0 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 9 of 10 Document No.001-87920 Rev. *A ECN # 4039000 Document History Page Document Title: QTP # 98462 : FAST ASYNCHRONOUS SRAM FAMILY ( CY7C106B/CY7C1006B, CY7C194B/ CY7C195B, CY7C199C ) R52D-5R TECHNOLOGY, FAB 4 Document Number: 001-87920 Rev. ECN Orig. of No. Change ** 4026944 ILZ *A 4039000 ILZ Description of Change Initial Spec Release Qualification report published on Cypress.com is not in spec format. Initiated spec for QTP 94862 and removed all Cypress reference spec and replaced with Industry standard. Updated package availability based on current qualified assembly Corrected QTP Spec title from QTP 94862 to 98462 Distribution: WEB Posting: None Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 10 of 10