Cypress Semiconductor Technology Qualification Report QTP# 042703 VERSION 2.0 October 2005 R8LD-1.8 Automotive Technology, Fab4 High Performance CMOS Static SRAM CY62126DV30 MoBL® 1-Mbit (64K x 16) Static RAM CY62127DV18 MoBL2® 1 Mb (64K x 16) Static RAM CY62127DV20 MoBL2® 1m (64K X 16) Static RAM CY62127DV30 MoBL® 1 Mb (64K x 16) Static RAM CY62128DV30 MoBL® 1 Mb (128K x 8) Static RAM CY62146DV30 4-Mbit (256K x 16) Static RAM CY62147DV18 MoBL2™ 4-Mb (256K x 16) Static RAM CY62147DV30 4-Mbit (256K x 16) Static RAM CY62148DV30 4-Mb (512K x 8) MoBL® Static RAM CY62157DV18 MoBL2™ CY62157DV20 MoBL2™ 8M (512 x 16) Static RAM CY62157DV30 MoBL® 8-Mbit (512K x 16) MoBL® Static RAM CY62157DV30 MoBL® 8 MB (512K x 16) Static RAM Die CY62158DV30 MoBL® 8-Mbit (1024K x 8) MoBL® Static RAM CY62167DV18 MoBL2™ 16M (1024K X 16) Static RAM CY62167DV20 MoBL2™ 16-Mb (1024K x 16) Static RAM CY62167DV30 MoBL® 16-Mbit (1M x 16) Static RAM CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Rene Rodgersr Staff Reliability Engineer (408) 943-2732 Sabbas Daniel Quality Engineering Director (408) 943-2685 Anca Voicu Product Engineering Manager (408) 943-2753 Cypress Semiconductor MoBL Static SRAM Device CY62157DV*, R8LD-1.8, Fab 4 QTP # 042703 V, 2.0 Page 2 of 10 October 2005 TECHNOLOGY QUALIFICATION HISTORY Qual Report 025007 042703 Description of Qualification Purpose New Device, 16Meg, MoBL Static RAM CY62167DV* device family on RAM8NLD-1.8 Technology New Automotive Technology R8LD-1.8V / New Device, Static RAM CY62157DV* device family Date Comp Jul 03 Nov 04 Cypress Semiconductor MoBL Static SRAM Device CY62157DV*, R8LD-1.8, Fab 4 QTP # 042703 V, 2.0 Page 3 of 10 October 2005 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: Qualify R8LD-1.8 Automotive Technology, Fab 4 on CY62157DV* device family. Marketing Part #: CY62126DV30, CY62127DV18/DV20/DV30, CY62128DV30, CY62146DV30, CY62147DV18/DV30, CY62148DV30, CY62157DV18/DV20/DV30, CY62158DV30, CY62167DV18/DV20/DV30 Device Description: 1.65V, 2.2V, 3.6V, Industrial available in 48-ball FBGA package. Cypress Division: Cypress Semiconductor Corporation –Memory Product Division (MPD) Overall Die (or Mask) REV Level (pre-requisite for qualification): Rev. D What ID markings on Die: 7C62155D TECHNOLOGY/FAB PROCESS DESCRIPTION – RAM8LD-1.8 Number of Metal Layers: 2 Metal Metal 1: Ti 150 Å, Al 300 Å, Cu 300 Å Composition: Metal 2: Ti 300 Å, Al 8000 Å Passivation Type and Materials: 1000Å TEOS / 9000Å Si3N4 Free Phosphorus contents in top glass layer(%): N/A Number of Transistors in Device ~74 million Number of Gates in Device ~19 million Generic Process Technology/Design Rule (µ-drawn): CMOS Double Metal/0.13 µm Gate Oxide Material/Thickness (MOS): 26 Å Name/Location of Die Fab (prime) Facility: Cypress Semiconductor -- Bloomington, MN Die Fab Line ID/Wafer Process ID: Fab4/RAM8NLD-1.8 PACKAGE AVAILABILITY PACKAGE 44-Lead TSOP II ASSEMBLY SITE FACILITY CML-R Note: Package Qualification details upon request Cypress Semiconductor MoBL Static SRAM Device CY62157DV*, R8LD-1.8, Fab 4 QTP # 042703 V, 2.0 Page 4 of 10 October 2005 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: Mold Compound Flammability Rating: ZW44 44-Lead Thin Small Outlined Packages (Type II) Hitachi CEL9200CYR/U UL 94 V0 Oxygen Rating Index: N/A Substrate Material: N/A Lead Finish, Composition / Thickness: Ni-90um, Pd-0.8um, Au-0.1-0.6um Die Backside Preparation Method/Metallization: Grinding Die Separation Method: 100% Wafer Saw Die Attach Supplier: Dexter Die Attach Material: QMI 509 Die Attach Method: Silver Epoxy through Dispensing Bond Diagram Designation: 10-05852 Wire Bond Method: Thermosonic Wire Material/Size: Au, 1.0 mil Thermal Resistance Theta JA °C/W: 73°C/W Package Cross Section Yes/No: N/A Assembly Process Flow: 11-20047 Name/Location of Assembly (prime) facility: CML-R ELECTRICAL TEST / FINISH DESCRIPTION Test Location: CML-R Fault Coverage: 100% Cypress Semiconductor MoBL Static SRAM Device CY62157DV*, R8LD-1.8, Fab 4 QTP # 042703 V, 2.0 Page 5 of 10 October 2005 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT Stress/Test High Temperature Operating Life Test Condition (Temp/Bias) Result P/F Dynamic Operating Condition, Vcc Max = 2.4V, 150°C P Dynamic Operating Condition, Vcc Max = 2.4V, 150°C P 130°C, 3.63V,85%RH Precondition: JESD22 Moisture Sensitivity MSL 3 P Early Failure Rate High Temperature Operating Life Latent Failure Rate High Accelerated Saturation Test (HAST) 192 Hrs, 30C/60%RH+3IR-Reflow, 260°C+0, -5°C Temperature Cycle MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C Precondition: JESD22 Moisture Sensitivity MSL3 P 192 Hrs, 30C/60%RH+3IR-Reflow, 260°C+0, -5°C Pressure Cooker 121°C, 100%RH Precondition: JESD22 Moisture Sensitivity MSL 3 P 192 Hrs, 30C/60%RH+3IR-Reflow, 260°C+0, -5°C High Temperature Storage 150°C ± 5°C no bias P Electrostatic Discharge Human Body Model (ESD-HBM) 500V/1000V/1500V/2000V JESD22, Method A114-B P Electrostatic Discharge Charge Device Model (ESD-CDM) 250V/500V/750V (corner pins only) Cypress Spec. 25-00020 P Acoustic Microscopy Cypress Spec. 25-00104 P Ball Shear Cypress Spec 24-00018 P Bond Pull Cypress Spec 24-00002 P Physical Dimensions Cypress Spec. 25-00031 P External Visual Cypress Spec 25-00038 P Electrical Distribution AEC-Q100-009 P Solderability Cypress Spec. 25-00018 P Static Latch-up 125C, 10V/5.85V, ± 300mA P In accordance with JEDEC 17. Cypress Spec. 01-00081 Cypress Semiconductor MoBL Static SRAM Device CY62157DV*, R8LD-1.8, Fab 4 QTP # 042703 V, 2.0 Page 6 of 10 October 2005 RELIABILITY FAILURE RATE SUMMARY Stress/Test Device Tested/ Device Hours # Fails Activation Energy Thermal AF4 Failure Rate High Temperature Operating Life Early Failure Rate 2,531 Devices 0 N/A N/A 0 PPM High Temperature Operating Life1,2, Long Term Failure Rate 431,520 DHRs 0 0.7 170 12 FIT 1 2 3 Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C. Chi-squared 60% estimations used to calculate the failure rate. Thermal Acceleration Factor is calculated from the Arrhenius equation E 1 1 AF = exp A - k T 2 T1 where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. Cypress Semiconductor MoBL Static SRAM Device CY62157DV*, R8LD-1.8, Fab 4 QTP # 042703 V, 2.0 Page 7 of 10 October 2005 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 025007 Ass Loc Duration Samp Rej STRESS: ACOUSTIC-MSL3 CY62167DV30L (7C62167D) 4309094 610316588 TAIWN-G COMP 15 0 CY62167DV30L (7C62167D) 4309094 610316809 TAIWN-G COMP 15 0 CY62167DV30L (7C62167D) 4310393 610318262 TAIWN-G COMP 45 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 2.4V, Vcc Max CY62167DV30L (7C62167D) 4309094 610316958N TAIWN-G 96 741 0 CY62167DV30L (7C62167D) 4306632 610311763 TAIWN-G 96 784 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 2.4V, Vcc Max CY62167DV30L (7C62167D) 4309094 610316958N TAIWN-G 80 410 0 CY62167DV30L (7C62167D) 4309094 610316958N TAIWN-G 500 410 0 CY62167DV30L (7C62167D) 4306632 610311763 TAIWN-G 80 409 0 CY62167DV3L0 (7C62167D) 4306632 610311763 TAIWN-G 500 408 0 STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V CY62167DV30L (7C62167D) 4306632 610311763 TAIWN-G COMP 9 0 CY62167DV30L (7C62167D) 4309094 610316958 TAIWN-G COMP 9 0 CY62167DV18L (7C62367D) 4306632 610313591 TAIWN-G COMP 9 0 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY62167DV30L (7C62167D) 4306632 610311763 TAIWN-G COMP 9 0 CY62167DV30L (7C62167D) 4309094 610316958 TAIWN-G COMP 9 0 CY62167DV18L (7C62367D) 4306632 610313591 TAIWN-G COMP 9 0 STRESS: STATIC LATCH-UP TESTING, 125C, 10V, ±300mA CY62167DV30L (7C62167D) 4306632 610311763 TAIWN-G COMP 3 0 CY62167DV30L (7C62167D) 4309094 610316958 TAIWN-G COMP 3 0 CY62167DV18L (7C62367D) 4306632 610313591 TAIWN-G COMP 3 0 STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRE COND 192 HR 30C/60%RH, MSL3 CY62167DV30L (7C62167D) 4309094 610316588 TAIWN-G 168 40 0 CY62167DV30L (7C62167D) 4309094 610316958 TAIWN-G 168 45 0 STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 1.98V, PRE COND 192 HR 30C/60%RH, MSL3 CY62167DV30L (7C62167D) 4309094 610316588 TAIWN-G 128 44 0 Failure Mechanism Cypress Semiconductor MoBL Static SRAM Device CY62157DV*, R8LD-1.8, Fab 4 QTP # 042703 V, 2.0 Page 8 of 10 October 2005 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # Ass Loc 025007 Duration Samp Rej STRESS: TC COND. C -65C TO 150C, PRE COND 192 HRS 30C/60%RH, MSL3 CY62167DV30L (7C62167D) 4309094 610316588 TAIWN-G 300 45 0 CY62167DV30L (7C62167D) 4309094 610316588 TAIWN-G 500 45 0 CY62167DV30L (7C62167D) 4309094 610316588 TAIWN-G 1000 43 0 CY62167DV30L (7C62167D) 4309094 610316809 TAIWN-G 300 44 0 CY62167DV30L (7C62167D) 4309094 610316809 TAIWN-G 500 44 0 CY62167DV30L (7C62167D) 4309094 610316809 TAIWN-G 1000 44 0 CY62167DV30L (7C62167D) 4310393 610318262 TAIWN-G 300 45 0 CY62167DV30L (7C62167D) 4310393 610318262 TAIWN-G 500 45 0 CY62167DV30L (7C62167D) 4310393 610318262 TAIWN-G 1000 45 0 Failure Mechanism Cypress Semiconductor MoBL Static SRAM Device CY62157DV*, R8LD-1.8, Fab 4 QTP # 042703 V, 2.0 Page 9 of 10 October 2005 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # Ass Loc 042703 Duration Samp Rej STRESS: BALL SHEAR CY62157DV30L (7C62157D) 4419708 610445720 CML-R COMP 5 0 4419708 610445720 CML-R COMP 5 0 STRESS: BOND PULL CY62157DV30L (7C62157D) STRESS: ELECTRICAL DISTRIBUTION CY62157DV30L (7C62157D) 4419708 610445720 CML-R COMP 45 0 CY62157DV30L (7C62157D) 4413985 610445718 CML-R COMP 45 0 CY62157DV30L (7C62157D) 4422506 610445719 CML-R COMP 45 0 CML-R COMP 3 0 CML-R COMP 3 0 COMP 6 0 3 0 3 0 3 0 STRESS: ESD-CHARGE DEVICE MODEL, 250V CY62157DV30L (7C62157D) 4419708 610445720 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY62157DV30L (7C62157D) 4419708 610445720 STRESS: ESD-CHARGE DEVICE MODEL, 750V (corner pins only) CY62157DV30L (7C62157D) 4419708 610445720 CML-R STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, 500V CY62157DV30L (7C62157D) 4419708 610445720 CML-R COMP STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, 1000V CY62157DV30L (7C62157D) 4419708 610445720 CML-R COMP STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, 1500V CY62157DV30L (7C62157D) 4419708 610445720 CML-R COMP STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, 2000V 4419708 610445720 CML-R COMP 3 0 CY62157DV30L (7C62157D) 4419708 610445720 CML-R COMP 1140 0 CY62157DV30L (7C62157D) 4413985 610445718 CML-R COMP 912 0 CY62157DV30L (7C62157D) 4422506 610445719 CML-R COMP 915 0 CY62157DV30L (7C62157D) STRESS: EXTERNAL VISUAL STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, PRE COND 192 HR 30C/60%RH, MSL3 CY62157DV30L (7C62157D) 4419708 610445720 CML-R 96 50 0 CY62157DV30L (7C62157D) 4419708 610445720 CML-R 128 50 0 Failure Mechanism Cypress Semiconductor MoBL Static SRAM Device CY62157DV*, R8LD-1.8, Fab 4 QTP # 042703 V, 2.0 Page 10 of 10 October 2005 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # Ass Loc 042703 Duration Samp Rej STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 2.4V, Vcc Max CY62157DV30L (7C62157D) 4419708 610445720 CML-R 48 844 0 CY62157DV30L (7C62157D) 4413985 610445718 CML-R 48 842 0 CY62157DV30L (7C62157D) 4422506 610445719 CML-R 48 845 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 2.4V, Vcc Max CY62157DV30L (7C62157D) 4419708 610445720 CML-R 408 55 0 610445720 CML-R 1000 50 0 STRESS: HIGH TEMPERATURE STORAGE, no bias CY62157DV30L (7C62157D) 4419708 STRESS: PHYSICAL DIMENSION CY62157DV30L (7C62157D) 4419708 610445720 CML-R COMP 10 0 CY62157DV30L (7C62157D) 4413985 610445718 CML-R COMP 10 0 CY62157DV30L (7C62157D) 4422506 610445719 CML-R COMP 10 0 STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRE COND 192 HR 30C/60%RH, MSL3 CY62157DV30L (7C62157D) 4419708 610445720 CML-R 96 50 0 CY62157DV30L (7C62157D) 4419708 610445720 CML-R 176 50 0 CY62157DV30L (7C62157D) 4419708 610445720 CML-R COMP 15 0 CY62157DV30L (7C62157D) 4413985 610445718 CML-R COMP 15 0 CY62157DV30L (7C62157D) 4422506 610445719 CML-R COMP 15 0 COMP 6 0 STRESS: SOLDERABILITY STRESS: STATIC LATCH-UP TESTING, 125C, 5.85V, ±300mA CY62157DV30L (7C62157D) STRESS: 4419708 610445720 CML-R TC COND. C -65C TO 150C, PRE COND 192 HR 30C/60%RH, MSL3 CY62157DV30L (7C62157D) 4419708 610445720 CML-R 500 50 0 CY62157DV30L (7C62157D) 4419708 610445720 CML-R 1000 45 0 Failure Mechanism