Cypress Semiconductor Product Qualification Report QTP# 042501 VERSION 1.0 May 2005 PSoC Mixed Signal Array Family S4AD-5 Technology, Fab 2 CY8C21123 CY8C21223 CY8C21323 PSoCTM Mixed Signal Array with On-Chip Controller CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Sabbas Daniel Quality Engineering Director (408) 943-2685 Fredrick Whitwer Principal Reliability Engineer (408) 943-2722 Cypress Semiconductor PSoC Mixed-Signal Array Family, S4AD-5, Fab 2 Device: CY8C21xxx QTP# 042501, V, 1.0 Page 2 of 11 May 2005 PRODUCT QUALIFICATION HISTORY Qual Report Description of Qualification Purpose Date Comp 010702 New Technology S4AD-5 / New Product, Programmable Clock Generator, CY2414ZC, its product family and bond option. Apr 01 022505 Three layer mask change to enhance functionality Jul 02 042501 PSoC 8C21xxxA Proton Device on Product Family on S4AD-5 Technology Mar 05 Cypress Semiconductor PSoC Mixed-Signal Array Family, S4AD-5, Fab 2 Device: CY8C21xxx QTP# 042501, V, 1.0 Page 3 of 11 May 2005 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: Qualify New device CY8C21xxx and its product family in S4D-5 Technology in Fab 2 Marketing Part #: CY8C21123, CY8C21223, CY8C21323 Device Description: 3.3V and 5.5V, Industrial, available in 8/16-lead SOIC, 20-lead SSOP and 24-lead MLF package Cypress Division: Cypress Microsystems Inc Subsidiary– (CMS) WA Overall Die (or Mask) REV Level (pre-requisite for qualification): What ID markings on Die: Rev. A 8C21000A TECHNOLOGY/FAB PROCESS DESCRIPTION S4AD-5 Number of Metal Layers: 2 Metal Composition: Metal 1: 500A Ti/6,000A Al 0.5% Cu /1,200A TiW Metal 2: 500A Ti/8,000A Al 0.5% Cu/300A TiW Passivation Type and Materials: 3,000A TeOs / 6,000A Si3N4 Free Phosphorus contents in top glass layer(%): 0% Number of Transistors in Device: 90,000 Number of Gates in Device 9,000 Generic Process Technology/Design Rule ( -drawn): Single Poly, Double Metal, 0.35 um Gate Oxide Material/Thickness (MOS): SiO2 / 110A Name/Location of Die Fab (prime) Facility: Cypress Semiconductor - Round Rock, TX Die Fab Line ID/Wafer Process ID: Fab2, S4AD-5CTI SONOS PACKAGE AVAILABILITY PACKAGE ASSEMBLY SITE FACILITY 8/16-lead SOIC CML-RA, Anam-Manila Phil. 20-lead SSOP OSE Taiwan 44-pin MLF Amkor-Seoul Korea Note: Package Qualification details upon request. Cypress Semiconductor PSoC Mixed-Signal Array Family, S4AD-5, Fab 2 Device: CY8C21xxx QTP# 042501, V, 1.0 Page 4 of 11 May 2005 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: Mold Compound Flammability Rating: SP20 20-Lead Shrunk Small Outline Package (SSOP) CEL9220HF - Ablestik V-O per UL94 Oxygen Rating Index: >28% Lead Frame Material: Copper Lead Finish, Composition / Thickness: Matte Sn (Tin) 300~800uinch Die Backside Preparation Method/Metallization: Backgrind Die Separation Method: 100% Saw Die Attach Supplier: Ablestik Die Attach Material: 8340 Die Attach Method: Dispensing Bond Diagram Designation: 10-05882 Wire Bond Method: Thermosonic Wire Material/Size: Au, 1.0mil Thermal Resistance Theta JA °C/W: 119°C/W Package Cross Section Yes/No: No Assembly Process Flow: 49-35032 Name/Location of Assembly (prime) facility: OSE Taiwan (T) ELECTRICAL TEST / FINISH DESCRIPTION Test Location: CML Fault Coverage: 100% Note: Please contact a Cypress Representative for other packages availability. Cypress Semiconductor PSoC Mixed-Signal Array Family, S4AD-5, Fab 2 Device: CY8C21xxx QTP# 042501, V, 1.0 Page 5 of 11 May 2005 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT Stress/Test Test Condition (Temp/Bias) High Temperature Operating Life Early Failure Rate Dynamic Operating Condition, Vcc Max=5.5V, 125°C Result P/F P Dynamic Operating Condition, Vcc Max=5.75V, 125°C Dynamic Operating Condition, Vcc Max=5.75V, 150°C High Temperature Operating Life Latent Failure Rate Dynamic Operating Condition, Vcc Max=5.75V, 125°C P Temperature Cycle MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C P Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85C/85%RH+3IR-Reflow, 235°C+5, 0°C Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85C/85%RH+3IR-Reflow, 260°C+5, 0°C Pressure Cooker 121°C, 100%RH P MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85C/85%RH+3IR-Reflow, 235°C+5, 0°C Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85C/85%RH+3IR-Reflow, 260°C+5, 0°C High Accelerated Saturation Test (HAST) 130°C, 85%RH P Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85C/85%RH+3IR-Reflow, 235°C+5, 0°C Data Retention 150°C ± 5°C no bias P High Temperature Steady State Life 150°C, 363V, Vcc Max P Electrostatic Discharge Human Body Model (ESD-HBM) 2,200V JESD22, Method A114-B P Electrostatic Discharge Body Model (ESD-HM) 2,000V, 2,200V MIL-STD-883, Method 3015.7 P P Age Bond Strength 500V Cypress Spec. 25-00020 MIL-STD-883C, Method 2011 Acoustic Microscopy Cypress Spec. 25-00104 P Current Density Cypress Spec. 22-00029 P Low Temperature Operating Life -30C, 4.3V, 8MHZ P Sem X-Section MIL-STD-883C, Method 2018-2 P Endurance Test MIL-STD-883C, Method 1033 P Dynamic Latchup Sensitivity Cypress Spec. 01-00081 P Static Latchup Sensitivity 125°C, ± 300mA In accordance with JEDEC 17. Cypress Spec. 01-00081 P Human Electrostatic Discharge Charge Device Model (ESD-CDM) P Cypress Semiconductor PSoC Mixed-Signal Array Family, S4AD-5, Fab 2 Device: CY8C21xxx QTP# 042501, V, 1.0 Page 6 of 11 May 2005 RELIABILITY FAILURE RATE SUMMARY Device Tested/ Device Hours # Fails Activation Energy Thermal3 A.F Failure Rate High Temperature Operating Life Early Failure Rate 1,024 Devices 0 N/A N/A 0 PPM High Temperature Operating Life1,2 Long Term Failure Rate 180,000 DHRs 0 0 .7 170 30 FITs Stress/Test 1 2 3 Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C. Chi-squared 60% estimations used to calculate the failure rate. Thermal Acceleration Factor is calculated from the Arrhenius equation E 1 1 AF = exp A - k T 2 T1 where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. Cypress Semiconductor PSoC Mixed-Signal Array Family, S4AD-5, Fab 2 Device: CY8C21xxx QTP# 042501, V, 1.0 Page 7 of 11 May 2005 Reliability Test Data QTP #: Device Fab Lot # 010702 Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: ACOUSTIC-MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 15 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 3.8V, Vcc Max CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 48 1005 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 48 1004 1 NON VISUAL CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 48 1005 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 3.8V, Vcc Max CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 500 120 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 500 120 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 500 120 0 STRESS: AGE BOND STRENGTH CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 15 0 TAIWN-T COMP 3 0 TAIWN-T 500 48 0 STRESS: DYNAMIC LATCH-UP TESTING, 11.5V CY2414ZC (7C841400A) 2101502 610106170/1/2 STRESS: LOW TEMPERATURE OPERATING LIFE, -30C, 4.3V CY2414ZC (7C841400A) 2101502 610106170/1/2 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 9 0 Cypress Semiconductor PSoC Mixed-Signal Array Family, S4AD-5, Fab 2 Device: CY8C21xxx QTP# 042501, V, 1.0 Page 8 of 11 May 2005 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 010702 Assy Loc Duration Samp Rej Failure Mechanism STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,000V CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2103764 610106177 TAIWN-T COMP 10 0 STRESS: STATIC LATCH-UP TESTING, 125C, 10V, ±300mA CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 3 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 3 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 3 0 STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 3.63V, PRE COND 168 HR 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 128 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 256 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 128 48 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 128 48 0 STRESS: HIGH TEMP STEADY STATE LIFE TEST, 150C, 3.63V CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 80 80 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 80 0 610106170/1/2 TAIWN-T COMP 45 0 STRESS: ENDURANCE TEST CY2414ZC (7C841400A) 2101502 STRESS: DATA RETENTION, PLASTIC, 150C CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 552 80 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 552 80 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 552 80 0 Cypress Semiconductor PSoC Mixed-Signal Array Family, S4AD-5, Fab 2 Device: CY8C21xxx QTP# 042501, V, 1.0 Page 9 of 11 May 2005 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 010702 Assy Loc Duration Samp Rej STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRE COND 168 HR 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 168 49 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 168 51 0 STRESS: TC COND. C -65C TO 150C, PRECONDITION 168 HRS 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 500 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 1000 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 500 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 1000 50 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 500 50 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 1000 49 0 Failure Mechanism Cypress Semiconductor PSoC Mixed-Signal Array Family, S4AD-5, Fab 2 Device: CY8C21xxx QTP# 042501, V, 1.0 Page 10 of 11 May 2005 Reliability Test Data QTP #: Device Fab Lot # Assembly Lot # 022505 Assy Loc Duration Samp Rej STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 5.75V, Vcc Max CY8C26443 (8C26443D) 2215932 510205367 INDNS-0 96 890 0 CY8C26443 (8C26443D) 2215932 510205368 INDNS-0 96 900 0 CY8C26443 (8C26443D) 2215932 510205407 INDNS-0 96 200 0 INDNS-0 COMP 9 0 INDNS-0 COMP 9 0 510205367/8 INDNS-0 COMP 3 0 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY8C26443 (8C26443D) 2215932 510205367/8 STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V CY8C26443 (8C26443D) 2215932 510205367/8 STRESS: STATIC LATCH-UP TESTING, 125C, 12V, ±300mA CY8C26443 (8C26443D) 2215932 STRESS: TC COND. C -65C TO 150C CY8C26443 (8C26443D) 2215932 510205367/8 INDNS-0 300 48 0 CY8C26443 (8C26443D) 2215932 510205367/8 INDNS-0 500 48 0 Failure Mechanism Cypress Semiconductor PSoC Mixed-Signal Array Family, S4AD-5, Fab 2 Device: CY8C21xxx QTP# 042501, V, 1.0 Page 11 of 11 May 2005 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 042501 Assy Loc Duration Samp Rej STRESS: ESD-CHARGE DEVICE MODEL, 500V CY8C21323 (8C21323A) 2444989 610464715N3 TAIWN-T COMP 9 0 9 0 3 0 STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, 2200V CY8C21323 (8C21323A) 2444989 610464715N3 TAIWN-T COMP STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2200V CY8C21323 (8C21323A) 2444989 610464715N3 TAIWN-T COMP STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 5.5V, Vcc Max CY8C21323 (8C21323A) 2444989 610464715 TAIWN-T 96 1024 0 STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRE COND 168 HR 85C/85%RH, MSL1 CY8C21323 (8C21323A) 2444989 610464715 TAIWN-T 168 50 0 COMP 3 0 STRESS: STATIC LATCH-UP TESTING, 125C, 11.5V, ±300mA CY8C21323 (8C21323A) 2444989 610464715N3 TAIWN-T STRESS: TC COND. C -65C TO 150C, PRECONDITION 168 HRS 85C/85%RH, MSL1 CY8C21323 (8C21323A) 2444989 610464715 TAIWN-T 300 50 0 CY8C21323 (8C21323A) 2444989 610464715 TAIWN-T 500 50 0 Failure Mechanism