Cypress Semiconductor Product Qualification Report QTP# 030702 VERSION 3.0 March 2008 PSoC™ Mixed Signal Array Family S4AD-5CTI Technology, Fab 2 CTI CY8C27143 PSoC ™ Mixed Signal Array CY8C27243 PSoC ™ Mixed Signal Array CY8C27443 PSoC ™ Mixed Signal Array CY8C27543 PSoC ™ Mixed Signal Array CY8C27643 PSoC ™ Mixed Signal Array CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Fredrick Whitwer Principal Reliability Engineer (408) 943-2722 Mira Ben-Tzur Quality Engineering Director (408) 943-2675 Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 2 of 15 March 2008 PRODUCT QUALIFICATION HISTORY Qual Report Description of Qualification Purpose Date Comp 010702 New Technology S4AD-5 / New Product, Programmable Clock Generator, CY2414ZC, product family and bond option. Apr 01 003605 Technology Derivative S4D-5 /New Neuron Devices, CY7C53150 and CY7C53120 Jul 01 030702 New PSoC™ CY8C27xxx device and product family in smaller die Nov 03 043105 5-Layer Mask change for ALL CY8C27xxxB product family Nov 04 074504 3 Layer Mask change (M1, Via, and M2) for PSoC Diamond Device (CY8C27x43) Jan 08 Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 3 of 15 March 2008 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: New device CY8C27xxx and product family in S4D-5CTI Technology in Fab 2 Marketing Part #: CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643 Device Description: 3.3V and 5V, Industrial, available in 8/20/28/48 lead PDIP, 20/28-lead SOIC, 20/28/48-lead SSOP and 44-lead TQFP package respectively. Cypress Division: Cypress Microsystems Inc Subsidiary– (CMS) WA Overall Die (or Mask) REV Level (pre-requisite for qualification): SONOS Flash: 16 Kbytes What ID markings on Die: 8C27002 Rev. B SRAM: 256 bytes TECHNOLOGY/FAB PROCESS DESCRIPTION S4AD-5CTI Number of Metal Layers: 2 Metal Composition: Metal 1: 500A Ti/6,000A Al 0.5% Cu /1,200A TiW Metal 2: 500A Ti/8,000A Al 0.5% Cu/300A TiW Passivation Type and Materials: 3,000A TEOS / 6,000A Si3N4 Free Phosphorus contents in top glass layer (%): 0% Number of Transistors in Device: 600,000 Number of Gates in Device 100,000 Generic Process Technology/Design Rule ( -drawn): 1Poly/2Metal, 0.35 µm Gate Oxide Material/Thickness (MOS): SiO2 / 110Å Name/Location of Die Fab (prime) Facility: Cypress Semiconductor - Round Rock, TX (CTI) Die Fab Line ID/Wafer Process ID: Fab2 SONOS, S4AD-5 CTI PACKAGE AVAILABILITY PACKAGE ASSEMBLY/TEST SITE FACILITY 20/28-lead PDIP IDNS-O 20/28-lead SOIC CML-R 20/28-lead SSOP OSE-T, PHIL-M, CML-RA 48/56-lead SSOP CML-R 48-lead MLF SEUOL-L 44-pin TQFP CML-R Note: Package Qualification details available upon request. Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 4 of 15 March 2008 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: Mold Compound Flammability Rating: SP28 28-Lead Shrunk Samll Outline Packages (SSOP) Hitachi Cel9220HF V-O per UL94 Oxygen Rating Index: >28% Lead Frame Material: Copper Lead Finish, Composition / Thickness: Sn Matte (100% Sn) Die Backside Preparation Method/Metallization: N/A Die Separation Method: 100% Saw Die Attach Supplier: Ablestik Die Attach Material: 8340 Bond Diagram Designation: 10-05762 Wire Bond Method: Thermosonic Wire Material/Size: Au, 1.0mil Thermal Resistance Theta JA °C/W: 95°C/W Package Cross Section Yes/No: N/A Assembly Process Flow: 49-35026M Name/Location of Assembly (prime) facility: OSE-Taiwan (T) ELECTRICAL TEST / FINISH DESCRIPTION Test Location: Cypress Philippines (CML-R) Fault Coverage: 100% Note: Please contact a Cypress Representative for the availability of other packages. Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 5 of 15 March 2008 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT Stress/Test Test Condition (Temp/Bias) Result P/F High Temperature Operating Life Dynamic Operating Condition, Vcc Max=5.75V, 125°C Early Failure Rate Dynamic Operating Condition, Vcc Max=5.75V, 150°C High Temperature Operating Life Dynamic Operating Condition, Vcc Max=5.75V, 125°C P MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C P P Latent Failure Rate Temperature Cycle Precondition: JESD22 Moisture Sensitivity MSL 3 192 Hrs., 30°C/60%RH+3IR-Reflow, 235°C+5, -0°C Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85°C/85%RH+3IR-Reflow, 235°C+5, -0°C Pressure Cooker 121°C, 100%RH P MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C Precondition: JESD22 Moisture Sensitivity MSL 3 192 Hrs., 30°C/60%RH+3IR-Reflow, 235°C+5, -0°C Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85°C/85%RH+3IR-Reflow, 235°C+5, - 0°C High Accelerated Saturation Test (HAST) 130°C, 5.5V, 85%RH P Precondition: JESD22 Moisture Sensitivity MSL 3 192 Hrs., 30°C/60%RH+3IR-Reflow, 235°C+5, -0°C 130°C, 3.63V, 85%RH Precondition: JESD22 Moisture Sensitivity MSL 1 168 Hrs, 85°C/85%RH+3IR-Reflow, 235°C+5, -0°C Data Retention 150°C ± 5°C no bias P High Temperature Steady State Life 150°C, 363V, Vcc Max P Electrostatic Discharge 2,200V, 2,000V P Human Body Model (ESD-HMB) MIL-STD-883, Method 3015.7 Electrostatic Discharge P Charge Device Model (ESD-CDM) 500V Cypress Spec. 25-00020 Age Bond Strength MIL-STD-883C, Method 2011 P Acoustic Microscopy Cypress Spec. 25-00104 P Low Temperature Operating Life -30C, 4.3V, 8MHZ P Dynamic Latchup Sensitivity Cypress Spec. 01-00081 P Static Latchup Sensitivity 125°C, ± 300mA P In accordance with JEDEC 17. Cypress Spec. 01-00081 Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 6 of 15 March 2008 RELIABILITY FAILURE RATE SUMMARY Device Tested/ Device Hours # Fails Activation Energy Thermal3 A.F Failure Rate High Temperature Operating Life Early Failure Rate 1,605 Devices (043105) 0 N/A N/A 0 PPM High Temperature Operating Life1,2 Long Term Failure Rate 593,000 DHRs (030702) 0 0 .7 55 28 FITs Stress/Test 1 2 3 Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C. Chi-squared 60% estimations used to calculate the failure rate. Thermal Acceleration Factor is calculated from the Arrhenius equation ⎡E ⎡ 1 1 ⎤ ⎤ AF = exp ⎢ A ⎢ - ⎥ ⎥ ⎣ k ⎣ T 2 T1 ⎦ ⎦ where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 7 of 15 March 2008 Reliability Test Data QTP #: Device Fab Lot # 010702 Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: ACOUSTIC-MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 15 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 3.8V, Vcc Max CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 48 1005 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 48 1004 1 NON VISUAL CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 48 1005 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 3.8V, Vcc Max CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 500 120 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 500 120 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 500 120 0 STRESS: AGE BOND STRENGTH CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 15 0 TAIWN-T COMP 3 0 TAIWN-T 500 48 0 STRESS: DYNAMIC LATCH-UP TESTING, 11.5V CY2414ZC (7C841400A) 2101502 610106170/1/2 STRESS: LOW TEMPERATURE OPERATING LIFE, -30C, 4.3V CY2414ZC (7C841400A) 2101502 610106170/1/2 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 9 0 Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 8 of 15 March 2008 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 010702 Assy Loc Duration Samp Rej Failure Mechanism STRESS: STATIC LATCH-UP TESTING, 125C, 10V, ±300mA CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 3 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 3 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 3 0 STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 3.63V, PRE COND 168 HR 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 128 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 256 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 128 48 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 128 48 0 STRESS: HIGH TEMP STEADY STATE LIFE TEST, 150C, 3.63V CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 80 80 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 80 0 610106170/1/2 TAIWN-T COMP 45 0 STRESS: ENDURANCE TEST CY2414ZC (7C841400A) 2101502 STRESS: DATA RETENTION, PLASTIC, 150C CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 552 80 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 552 80 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 552 80 0 STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRE COND 168 HR 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 168 49 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 168 51 0 Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 9 of 15 March 2008 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 010702 Assy Loc Duration Samp Rej STRESS: TC COND. C -65C TO 150C, PRECONDITION 168 HRS 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 500 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 1000 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 500 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 1000 50 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 500 50 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 1000 49 0 Failure Mechanism Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 10 of 15 March 2008 Reliability Test Data QTP #: Device Fab Lot # 003605 Assy Lot # Assy Loc Duration Samp Rej CY7C53150-AI (7C53150A) 2104858 610109389/90 TAIWN-G COMP 15 0 CY7C53150-AI(7C53150B) 2110601 610115306 TAIWN-G COMP 15 0 CY7C53150-AI (7C53150B) 2113874 340100160/1 TAIWN-G COMP 15 0 Failure Mechanism STRESS: ACOUSTIC-MSL3 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 5.75V, Vcc Max CY7C53120-SI (7C53120B) 2110601 610119962 CSPI-R 80 394 0 CY7C53120-SI (7C53120B) 2113874 610119334 CSPI-R 80 591 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 5.75V, Vcc Max CY7C53120-SI (7C53120B) 2110601 610119962 CSPI-R 96 609 1 CY7C53120-SI (7C53120B) 2113874 610119334/7707 CSPI-R 96 414 0 MISSING LICON STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 5.75V, Vcc Max CY7C53120-SI (7C53120B) 2110601 610119962 CSPI-R 197 393 0 CY7C53120-SI (7C53120B) 2110601 610119962 CSPI-R 500 393 0 CY7C53120-SI (7C53120B) 2113874 610119334 CSPI-R 197 400 1 CY7C53120-SI (7C53120B) 2113874 610119334 CSPI-R 500 399 0 COMP 9 0 UNKNOWN STRESS: ESD-CHARGE DEVICE MODEL, 500V CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 5.5V, PRE COND 192 Hrs., 30ºC/60%RH, MSL3 CY7C53150-AI (7C53150A) 2104858 610109389/90 TAIWN-G 128 48 0 CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G 128 46 0 CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G 256 46 0 COMP 9 0 STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,000V CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G STRESS: STATIC LATCH-UP TESTING, 125C, 12V, ±300mA CY7C53150-AI (7C53150A) 2104858 610109389/90 TAIWN-G COMP 3 0 CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G COMP 3 0 TAIWN-G 1000 48 0 STRESS: ENDURANCE TEST, -25C/+85 CY7C53150-AI (7C53150B) 2110601 610115306 Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 11 of 15 March 2008 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 003605 Assy Loc Duration Samp Rej STRESS: DATA RETENTION, PLASTIC, 150C CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G 500 266 0 CY7C53150-AI (7C53150B) 2113874 340100160/1 TAIWN-G 500 266 0 STRESS: PRESSURE COOKER TEST, 121C, 100%RH), PRE COND 192 HR 30ºC/60%RH, MSL3 CY7C53150-AI (7C53150A) 2104858 610109389/90 TAIWN-G 168 50 0 CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G 168 48 0 STRESS: TC COND. C -65C TO 150C, PRECONDITION 192 HR 30ºC/60%RH, MSL3 CY7C53150-AI (7C53150A) 2104858 610109389/90 TAIWN-G 300 50 0 CY7C53150-AI (7C53150A) 2104858 610109389/90 TAIWN-G 500 50 0 CY7C53150-AI (7C53150A) 2104858 610109389/90 TAIWN-G 1000 50 0 CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G 300 48 0 CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G 500 47 0 CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G 1000 47 0 CY7C53150-AI (7C53150B) 2113874 340100180/1 TAIWN-G 300 48 0 CY7C53150-AI (7C53150B) 2113874 340100180/1 TAIWN-G 500 48 0 CY7C53150-AI (7C53150B) 2113874 340100180/1 TAIWN-G 1000 48 0 Failure Mechanism Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 12 of 15 March 2008 Reliability Test Data QTP #: Device 030702 Fab Lot # Assembly Lot # Assy Loc Duration Samp Rej CY8C27443 (8C27443A) 2315276 510304158 INDNS-0 COMP 15 0 CY8C27443 (8C27443A) 2324841 510305472 INDNS-0 COMP 15 0 CY8C27443 (8C27443A) 2323812 510305917 INDNS-0 COMP 15 0 STRESS: ACOUSTIC STRESS: DATA RETENTION, PLASTIC, NO BIAS, 125C CY8C27443 (8C27443A) 2324841 510305472 INDNS-0 250 164 0 CY8C27443 (8C27443A) 2324841 510305472 INDNS-0 500 164 0 CY8C27443 (8C27443A) 2323812 510305917 INDNS-0 250 159 0 CY8C27443 (8C27443A) 2323812 510305917 INDNS-0 500 159 0 INDNS-0 COMP 9 0 INDNS-0 COMP 9 0 INDNS-0 128 45 0 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY8C27443 (8C27443A) 2315276 510304158 STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V CY8C27443 (8C27443A) 2315276 510304158 STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 5.5V CY8C27443 (8C27443A) 2315276 510304158 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 5.75V, Vcc Max CY8C27443 (8C27443A) 2315276 510304158 INDNS-0 96 822 0 CY8C27443 (8C27443A) 2324841 510305472 INDNS-0 96 697 0 CY8C27443 (8C27443A) 2323812 510305917 INDNS-0 96 700 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 125C, 5.75V, Vcc Max CY8C27443 (8C27443A) 2315276 510304158 INDNS-0 200 593 0 CY8C27443 (8C27443A) 2315276 510304158 INDNS-0 1000 593 0 INDNS-0 128 50 0 INDNS-0 COMP 3 0 STRESS: PRESSURE COOKER TEST 121C, 100%RH CY8C27443 (8C27443A) 2315276 510304158 STRESS: STATIC LATCH-UP TESTING, 125C, 12V, ±300mA CY8C27443 (8C27443A) 2315276 510304158 Failure Mechanism Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 13 of 15 March 2008 Reliability Test Data QTP #: Device Fab Lot # Assembly Lot # 030702 Assy Loc Duration Samp Rej STRESS: TC COND. C -65C TO 150C CY8C27443 (8C27443A) 2315276 510304158 INDNS-0 300 50 0 CY8C27443 (8C27443A) 2315276 510304158 INDNS-0 500 50 0 CY8C27443 (8C27443A) 2315276 510304158 INDNS-0 1000 50 0 CY8C27443 (8C27443A) 2324841 510305472 INDNS-0 300 50 0 CY8C27443 (8C27443A) 2324841 510305472 INDNS-0 500 50 0 CY8C27443 (8C27443A) 2324841 510305472 INDNS-0 1000 50 0 CY8C27443 (8C27443A) 2323812 510305917 INDNS-0 300 50 0 CY8C27443 (8C27443A) 2323812 510305917 INDNS-0 500 50 0 CY8C27443 (8C27443A) 2323812 510305917 INDNS-0 1000 50 0 Failure Mechanism Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 14 of 15 March 2008 Reliability Test Data QTP #: Device Fab Lot # Assembly Lot # 043105 Assy Loc Duration Samp Rej COMP 9 0 COMP 9 0 COMP 3 0 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY8C27443 (8C27443B) 2403330 510403166 INDNS-0 STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22, METHOD A114-B, 2,200V CY8C27443 (8C27443B) 2403330 510403166 INDNS-0 STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,200V CY8C27443 (8C27443B) 2403330 510403166 INDNS-0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 5.5V, Vcc Max CY8C27443 (8C27443B) 2400030 610438921 INDNS-0 96 847 0 CY8C27443 (8C27443B) 2414285 610438918 INDNS-0 96 758 0 STRESS: PRESSURE COOKER TEST, 121C, 100%RH, PRE COND 168HRS 85C/85%RH, MSL1 CY8C27443 (8C27443B) 2400030 610438921 INDNS-0 96 85 0 CY8C27443 (8C27443B) 2400030 610438921 INDNS-0 168 85 0 INDNS-0 COMP 3 0 STRESS: STATIC LATCH-UP TESTING, 125C, 11.1V, ±300mA CY8C27443 (8C27443B) 2403330 510403166 Failure Mechanism Cypress Semiconductor PSoC™ Mixed Signal Array Family, S4AD-5CTI, Fab 2 Device: CY8C27xxx 030702 V.3.0 Page 15 of 15 March 2008 Reliability Test Data QTP #: Device Fab Lot # Assembly Lot # 074504 Assy Loc Duration Samp Rej Failure Mechanism STRESS: ETEST YIELD CY8C27443 (8C27443B) 2739935 COMP COMPARABLE 2739935 COMP COMPARABLE STRESS: SORT YIELD CY8C27443 (8C27443B)