Qualification Report January 1992 QTP 91094 64K SRAM FAMILY MARKETIN G DEVICE PART NBR DESCRIPTION CY7C161 16K x 4 (SIO) CY7C162 16K x 4 (SIO) CY7C164 16K x 4 CY7C166 (OE) CY7C185 8K x 8 CY7C186 8K x 8 (.6 DIP) CY7C187 64K x 1 Version 1.2 PRODUCT DESCRIPTION (for qualification) Information provided in this document is intended for generic qualification and technically describes the Cypress part supplied: Marketing Part #: CY7C185 Device Description: 8K x 8 SRAM Cypress Division: Cypress Semiconductor Corporation Overall Die (or Mask) REV Level (pre-requisite for qualification): Die Size (stepping): 154 mils x 214 mils Rev. D What ID markings on Die: Cypress Qualification completion/Marketing Availability Dates (Current REV): 7C185A 8/1991 Now TECHNOLOGY/FAB PROCESS DESCRIPTION Number of Metal Layers: 1 Metal Composition: Passivation Type and Materials: 500Å Ti,1200Å TiW,8500Å SiAl,500Å Ti 4,000A 2%P LTO + 15,000A Oxynitride Free Phosphorus contents in top glass layer(%): Die Coating(s), if used: None Plastic : Silicone Gel Generic Process Technology/Design Rule (µ-drawn): CMOS, Double Poly, Single Metal / 0.8µm Gate Oxide Material/Thickness (MOS): SiO2 / 195A Name/Location of Die Fab (prime) Facility: Cypress Semiconductor, Bloomington, MN (Fab 3) Die Fab Line ID/Wafer Process ID: Fab 3 / R21 PLASTIC PACKAGE/ASSEMBLY DESCRIPTION Package Outline, Type, or Name: 22-pin, 300-mil Plastic DIP (7C164, 7C187) 24-pin, 300 mil Plastic DIP (7C166) 28-pin, 300-mil Plastic DIP (7C161, 7C162, 7C185); 600-mil (7C186) Die to Package edge clearance: 48 mils per side (300-mil); 188 mils per side (600-mil) Mold Compound Name/Manufacturer: Lead Frame material: Sumitomo EME-6300H(R) Copper Lead Finish, composition: Solder Dipped, 63%Sn, 37%Pb Die Attach Area Plating: Silver Die Attach Pad Dim: 300 mil: 160 x 286 mils 600 mil: 220 x 320 mils Die Attach Method: Epoxy Die Attach Material: Silver Epoxy Wire Bond Method: Thermocompression Wire Material/Size: Gold / 1.3 mil Name/Location of Assembly (prime) facility: Cypress Semiconductor, San Jose, CA Assembly Line ID and Process ID: Cypress Semiconductor / P33 PAGE 3 CYPRESS SEMICONDUCTOR PLASTIC PACKAGE/ASSEMBLY DESCRIPTION Package Outline, Type, or Name: 24-pin, 300-mil Plastic SOIC/SOJ (7C164, 7C166, 7C187) 28-pin, 300-mil Plastic SOIC/SOJ (7C161, 7C162, 7C185) Die to Package edge clearance: 48 mils per side (300-mil) Mold Compound Name/Manufacturer: Lead Frame material: Sumitomo EME-6300H(R) Copper Lead Finish, composition: Solder Plate, 80%Sn, 20%Pb Die Attach Area Plating: Silver Die Attach Pad Dim: 24 pin: 160 x 286 mils 28 pin: 190 x 300 mils Die Attach Method: Epoxy Die Attach Material: Silver Epoxy Wire Bond Method: Thermocompression Wire Material/Size: Gold / 1.3 mil Name/Location of Assembly (prime) facility: Cypress Semiconductor, San Jose, CA Assembly Line ID and Process ID: Cypress Semiconductor / S31 PAGE 4 CYPRESS SEMICONDUCTOR OTHER INFORMATION For approval by similarity, identify other devices using the same basic die with bonding or metal mask options or test selections and explain: CY7C161, CY7C162, CY7C164, CY7C166, CY7C187 - Metal Mask Option CY7C186 - Package Option for 7C185 die (600-mil DIP only) If Cypress is planning any changes in the near future, identify change (Qtr/Yr) in: Die Design Rev./Shrink/Date: Rev. B/Q491 Fab/Assembly site change/Date: Die Process Change/Date: None Cross Licensee/Licensor/Date: Other Devices to be qualified in this technology: MHS France/1988 256K SRAM family Other Packages to be qualified for this device: CerDIP, LCC, CerPack ESD Voltage Rating (per MIL STD-008, Method 3018): Flammability Classification (UL-94V): Alternate Fab/Assembly Locations: None >2,000V UL-94V0, 1/8 Fabs: 1-2 / Assembly : Omedata, Indonesia (PDIP); Hyundai, Korea (SO) Please attach the following Qualification / Reliability data for the die revision and Package type, for the fab and assembly sites identified above (mark [X] if included): 1 X HAST (5.5V, 130°C, 85%RH, 15psig) 7 X Operating Life at (temp): 2 X Temperature Cycle (-65°C to 150°C) 8 X Latchup Testing 3 Data Retention Bake, Plastic (165°C) 9 X Steady State Life (HTSSL, 5.75V, 150°C) 4 Data Retention Bake, Hermetic (250°C) 10 X Other: SEM Analysis X Other: Aged Bond Strength Other: Alpha Particle Sensitivity 5 X Autoclave (PCT, 121°C, 100%RH) 11 6 X ESD Tests (MIL-STD 883, method 3015) 12 150°C PAGE 5 CYPRESS SEMICONDUCTOR PRODUCT INFORMATION FOR QUALIFICATION BY SIMILARITY Product Family: 64K SRAM Family Mfg Division: Cypress Semiconductor Supplier's Part Number Rated Speed (all pkgs) Pkg Size/ Type (all fabs) Die ID Die Size mil x mil (stepping) Design Rule (µ µ) Fabrication Process ID Line ID Passivation Mold Primary ESD Volt Availability Type Compound Assembly Rating (mm/yy) (all Line pkgs) Location CY7C161 -xxPC -xxSC -xxVC 15ns to 45ns 28.3 PDIP 28.3 SOIC 28.3 SOJ 7C161A 154 x 215 (3) 145 x 213* (2) 0.8µ µ CMOS, R21 3 2** LTO + Oxynitride Sumitomo San Jose, CA >2,000V HBM Now CY7C162 -xxPC -xxSC -xxVC 15ns to 45ns 28.3 PDIP 28.3 SOIC 28.3 SOJ 7C162A 154 x 215 145 x 213 0.8µ µ CMOS, R21 3 2 LTO + Oxynitride Sumitomo San Jose, CA >2,000V HBM Now CY7C164 -xxPC -xxSC -xxVC 15ns to 45ns 22.3 PDIP 24.3 SOIC 24.3 SOJ 7C164AA 154 x 215 145 x 213 0.8µ µ CMOS, R21 3 2 LTO + Oxynitride Sumitomo San Jose, CA >2,000V HBM Now CY7C166 -xxPC -xxSC -xxVC 15ns to 45ns 24.3 PDIP 24.3 SOIC 24.3 SOJ 7C166A 154 x 215 145 x 213 0.8µ µ CMOS, R21 3 2 LTO + Oxynitride Sumitomo San Jose, CA >2,000V HBM Now NOTES: "xx" covers all rated speeds, in this case, 15ns, 20ns, 25ns, 35ns, 45ns *Difference in stepping dimensions are due to the difference in equipment at the two locations. Design is unchanged. **Fab 2 previously qualified. Fab 3 qualified using plastic DIP packages for plastic only. SOIC/SOJ previously qualified, Quals 87041, 89048, and 89343. PAGE 6 CYPRESS SEMICONDUCTOR PRODUCT INFORMATION FOR QUALIFICATION BY SIMILARITY Product Family: 64K SRAM Family Mfg Division: Cypress Semiconductor Supplier's Part Number Rated Speed (all pkgs) Pkg Size/ Type (all fabs) Die ID Die Size mil x mil (stepping) Design Rule (µ µ) Fabrication Passivation Mold Primary ESD Volt Type Compound Assembly Rating (all Line pkgs) Location Availability (mm/yy) Process Line ID ID CY7C185 -xxPC -xxSC -xxVC 15ns to 45ns 28.3 PDIP 28.3 SOIC 28.3 SOJ 7C185A 154 x 215 (3) 145 x 213* (2) 0.8µ µ CMOS, R21 3 2** LTO + Oxynitride Sumitomo San Jose, CA >2,000V HBM Now CY7C186 -xxPC -xxSC -xxVC 15ns to 45ns 28.6 PDIP 7C185A 154 x 215 145 x 213 0.8µ µ CMOS, R21 3 2 LTO + Oxynitride Sumitomo San Jose, CA >2,000V HBM Now CY7C187 -xxPC -xxSC -xxVC 15ns to 45ns 22.3 PDIP 24.3 SOIC 24.3 SOJ 7C187A 154 x 215 145 x 213 0.8µ µ CMOS, R21 3 2 LTO + Oxynitride Sumitomo San Jose, CA >2,000V HBM Now NOTE: "xx" covers all rated speeds, in this case, 15ns, 20ns, 25ns, 35ns, 45ns *Difference in stepping dimensions are due to the difference in equipment at the two locations. Design is unchanged. **Fab 2 previously qualified. Fab 3 qualified using plastic DIP packages for plastic only. SOIC/SOJ previously qualified, Quals 87041, 89048, and 89343. PAGE 7 CYPRESS SEMICONDUCTOR Marketing Part: Pkg Description: DEVICE RELIABILITY SUMMARY CY7C185 28-pin, 300-mil PDIP Wafer Fab: Assembly: Fab 3 - Bloomington, MN Cypress - San Jose, CA High Temperature Dynamic Operating Life (HTOL, 5.75V, 150°C) - Early Failure Rate Device Lot# 48 Hours Cumulative CY7C185 CY7C185 CY7C185 3102004 3103006 3105009 1/700 0/1320 0/599 1/2619 Functional Failure High Temperature Dynamic Operating Life (HTOL, 5.75V, 150°C) - Latent Failure Rate Device Lot# 80 Hours 500 Hours Cumulative CY7C185 CY7C185 CY7C185 3102004 3103006 3105009 1/346 0/346 0/345 2/334 1/346 0/343 4/1023 1 Functional, 1 Oxide 2 Particle Defect High Temperature Steady State Life Test (HTSSL, 5.75V, 150°C) Device Lot# 80 Hours 168 Hours Cumulative CY7C185 CY7C185 CY7C185 3102004 3103006 3105009 0/129 0/129 0/129 0/128 1/128 1/129 2/385 Particle Defect Temperature Cycle (Condition C, -65°C to 150°C) Device Lot# CY7C185 CY7C185 CY7C185 CY7C185 100 Cycles 300 Cycles Cumulative 3102004 0/73 0/326 3103006 3103006 3105009 0/75 0/103 0/75 0/105 PAGE 8 CYPRESS SEMICONDUCTOR Marketing Part: Pkg Description: DEVICE RELIABILITY SUMMARY CY7C185 28-pin, 300-mil PDIP Wafer Fab: Assembly: Fab 3 - Bloomington, MN Cypress - San Jose, CA Autoclave (PCT, No bias, 121°C, 100%RH, 15psig) Device Lot# 96 Hours 288 Hours Cumulative CY7C185 CY7C185 3102004 3103006 0/75 0/76 0/75 0/76 0/151 High Accelerated Saturation Test (HAST, 5.5V, 130°C, 85%RH, 15psig) Device Lot# 100 Hours 200 Hours Cumulative CY7C185 3102004 0/76 0/76 0/150 CY7C185 3103006 0/74 0/74 PAGE 9 CYPRESS SEMICONDUCTOR Device Reliability Summary 64K SRAM FAMILY, Fab 3 (Minnesota) CY7C161/162/164/166/185/186/187 Electrostatic Discharge Human Body Model Circuit per Mil Std 883, Method 3015 >+2,000V Unit 1 >-2,000V >+2,000V Unit 2 >-2,000V >+2,000V Unit 3 >-2,000V (Highest passing voltage, +10% Guard-banded) Latchup Testing to Cypress Internal Latch-up Procedure 3 Tests: (2 lots) 0/10 Current Injection = 200mA Trigger Hot Socket = VCC 0 - 7V VCC Oscillation VCC = 3.5 - 7.5V at 1MHz Temp = 150°C Other miscellaneous tests Aged Bond Strength: Passed (5g) Wafer SEM Analysis: Passed PAGE 10 CYPRESS SEMICONDUCTOR CYPRESS PREVIOUS QUALIFICATION Device ID: Status: Process ID: 7C185A Prod. Family: Production R21 7C18xA, 7C16xA Passed Complete Date: Process Technology: CMOS Process Loc: San Jose (Fab 1 [F1]) Texas (Fab 2 [F2]) (Plastic only) Sumitomo Lead Frame: Copper (PlasticP Alloy 42 (Ceramic) Plastic DIP,SO,PLCC CerDIP,LCC,FPACK Mold Compound: Die Attach Mat: Silver Epoxy (Plastic) Silver Glass (Ceramic) Package Loc: Stress/Test Mask ID: Results: Package: Cypress Test No. 64K SRAM Family Reference Method San Jose (All) Omedata (PDIP) Anam (SO) Test Loc: Actual Conditions Status * 1988 (Fab 1) 1989 (Fab 2) San Jose, CA Qualification Data Reference Test Result Temp/Bias Hrs/Cyc SS/Fail 22A HTOL - EFR 150°C/5.75V 80 Hr F1: 16617/8 F2: 4571/0 C C Pass X X 22 HTOL - LFR 150°C/5.75V 336 Hr F1: 3298/2 F2: 995/2 C C X X 37 HTSSL - Static Life 150°C/6.5V 336 Hr F1: 515/0 F2: 519/3 C C X X Temp/Humidity Bias 85°-85%RH 1000 Hr F1: 112/0 C X 23 HAST 121°-85%RH 200 Hr F2: 219/0 C X 24 Steam Test/Autoclave/PCT 121°-100%RH 288 Hr F1: 332/1 F2: 219/0 C C X X 12 Temperature Cycle Cond. C 1000 Cy F1: 507/1 F2: 220/0 C C X X 13 Thermal Shock Cond. B 200 Cy F2: 275/0 C X 34 Accelerated Soft Error Rate Corner Pins Internal Pins F1: 30/0 C X Corner Pins Internal Pins 200mA F1: 10/0 C X 2 gm F1: 5/0 C X M1010 System Soft Error Rate 20 Mechanical Sequence 26 X-Ray 6 ESD-HBM 6 ESD-CDM 33 Latch-up 50 Flammability & Oxygen Index 14 Moisture Resistance 9 Internal Water Vapor 2 Solvent Resistance 4 Internal Visual 1 Physical Dimensions 3 Solderability 7 Lead Integrity 5 Bond Strength 29 Die Shear Strength 11 Lid Torque * I - Interim, C - Complete M3015 Fail