CY2300 Phase-Aligned Clock Multiplier Phase-Aligned Clock Multiplier Features Functional Description ■ 10 MHz to 166.67 MHz output operating range The CY2300 is a four output 3.3 V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. ■ Four-multiplier configuration ■ Single PLL architecture ■ Phase aligned outputs ■ Low jitter, high accuracy outputs ■ Output enable pin ■ 3.3 V operation ■ 5 V tolerant input ■ Internal loop filter ■ 8-pin 150-mil small-outline integrated circuit (SOIC) package ■ Commercial temperature The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN output frequencies on respective output pins. The part has an on-chip PLL which locks to an input clock presented on the REFIN pin. The input-to-output skew is guaranteed to be less than 200 ps, and output-to-output skew is guaranteed to be less than 200 ps. Multiple CY2300 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 400 ps. The CY2300 is available in commercial temperature range. For a complete list of related documentation, click here. Logic Block Diagram FBK 1/2xREF REFIN PLL /2 Divider Logic REF REF 2xREF OE Cypress Semiconductor Corporation Document Number: 38-07252 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 25, 2016 CY2300 Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Maximum Ratings ............................................................. 4 Operating Conditions ....................................................... 4 Electrical Characteristics ................................................. 4 Thermal Resistance .......................................................... 4 Test Circuits ...................................................................... 5 Switching Characteristics ................................................ 5 Switching Waveforms ...................................................... 6 Ordering Information ........................................................ 7 Ordering Code Definitions ........................................... 7 Package Drawing and Dimensions ................................. 8 Reference Documents ...................................................... 9 Acronyms .......................................................................... 9 Document Number: 38-07252 Rev. *H Document Conventions ................................................... 9 Units of Measure ......................................................... 9 Errata ............................................................................... 10 Part Numbers Affected .............................................. 10 CY2300 Errata Summary .......................................... 10 CY2300 Qualification Status of fixed silicon .............. 10 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC®Solutions ....................................................... 13 Cypress Developer Community ................................. 13 Technical Support ..................................................... 13 Page 2 of 13 CY2300 Pinouts Figure 1. 8-pin SOIC pinout (Top View) 1/2xREF GND REFIN REF 1 2 3 4 8 7 6 5 OE VDD 2xREF REF Pin Definitions Pin Signal [1] 1 1/2xREF Description Clock output, 1/2x reference 2 GND 3 REFIN Ground 4 REF Clock output reference 5 REF Clock output reference 6 2xREF 7 VDD 3.3 V Supply 8 OE Output enable (weak pull-up) Input reference frequency, 5 V tolerant input Clock output, 2x reference Note 1. Weak pull-down on all outputs. Document Number: 38-07252 Rev. *H Page 3 of 13 CY2300 Maximum Ratings Storage temperature ................................ –65 °C to +150 °C Supply voltage to ground potential ..............–0.5 V to +7.0 V DC input voltage (except ref) .............. –0.5 V to VDD + 0.5 V Junction temperature ................................................ 150 °C Static discharge voltage (per MIL-STD-883, method 3015) .......................... > 2000 V DC input voltage REF .......................................–0.5 V to 7 V Operating Conditions Parameter Description Min Max Unit VDD Supply voltage 3.0 3.6 V TA Operating temperature (ambient temperature) 0 70 °C CL Load capacitance, 10 MHz < FOUT < 133.33 MHz – 18 pF Load capacitance,133.33 MHz < FOUT < 166.67 MHz – 12 pF CIN Input capacitance tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) – 7 pF 0.05 50 ms Min Max Unit Electrical Characteristics Parameter Description Test Conditions VIL Input LOW voltage – 0.8 V VIH Input HIGH voltage 2.0 – V IIL Input LOW current VIN = 0 V – 100 µA IIH Input HIGH current VIN = VDD – 50 µA [2] VOL Output LOW voltage VOH Output HIGH voltage [2] IOL = 8 mA IOH = –8 mA – 0.4 V 2.4 – V IDD Supply current Unloaded outputs, REFIN = 66 MHz – 45 mA Unloaded outputs, REFIN = 33 MHz – 32 mA Unloaded outputs, REFIN = 20 MHz – 18 mA Thermal Resistance Parameter [3] Description θJA Thermal resistance (junction to ambient) θJC Thermal resistance (junction to case) Test Conditions 8-pin SOIC Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 140 °C/W 54 °C/W Notes 2. Parameter is guaranteed by design and characterization. It is not 100% tested in production. 3. These parameters are guaranteed by design and are not tested. Document Number: 38-07252 Rev. *H Page 4 of 13 CY2300 Test Circuits Figure 2. Test Circuit #1 VDD 0.1 F OUTPUTS CLK OUT C LOAD GND Switching Characteristics Parameter 1/t1 Description Output frequency Duty t3 cycle[4] = t2 t1 Rise time[4] time[4] Test Conditions 18 pF load Min Typ Max Unit 10 – 133.33 MHz 12 pF load – – 166.67 MHz Measured at VDD/2 40 50 60 % Measured between 0.8 V and 2.0 V – – 1.20 ns Measured between 0.8 V and 2.0 V – – 1.20 ns t4 Fall t5 Output to output skew on rising edges[4] All outputs equally loaded Measured at VDD/2 – – 200 ps t6 Delay, REFIN rising edge to output rising edge[4] Measured at VDD/2 from REFIN to any output – – 200 ps t7 Device to device skew[4] Measured at VDD/2 on the 1/2xREF pin of devices (pin 1) – – 400 ps tJ Period jitter[4] Measured at Fout = 133.33 MHz, loaded outputs, 18 pF load – – 175 ps tLOCK PLL lock time[4] Stable power supply, valid clocks presented on REFIN – – 1.0 ms Note 4. All parameters are specified with equally loaded outputs. Document Number: 38-07252 Rev. *H Page 5 of 13 CY2300 Switching Waveforms Figure 3. Duty Cycle Timing t1 t2 VDD/2 Figure 4. All Outputs Rise/Fall Time 2.0V 0.8V OUTPUT 2.0V 0.8V 3.3V 0V t4 t3 Figure 5. Output to Output Skew OUTPUT VDD/2 VDD/2 OUTPUT t5 Figure 6. Input to Output Propagation Delay REFIN VDD/2 VDD/2 OUTPUT t6 Figure 7. Device to Device Skew 1/2xREF, Device1 VDD/2 VDD/2 1/2xREF, Device2 t7 Document Number: 38-07252 Rev. *H Page 6 of 13 CY2300 Ordering Information Ordering Code Package Type Operating Range Pb-free CY2300SXC 8-pin SOIC Commercial (0 °C to 70 °C) CY2300SXCT 8-pin SOIC - Tape and Reel Commercial (0 °C to 70 °C) Ordering Code Definitions CY 2300 S X C X X = blank or T blank = Tube; T = Tape and Reel Temperature Grade: C = Commercial Pb-free Package Type: S = 8-pin SOIC Part Identifier Company ID: CY = Cypress Document Number: 38-07252 Rev. *H Page 7 of 13 CY2300 Package Drawing and Dimensions Figure 8. 8-pin SOIC (150 Mils) Package Outline, 51-85066 51-85066 *H Document Number: 38-07252 Rev. *H Page 8 of 13 CY2300 Reference Documents Reference documents are available through your local Cypress sales representative. You can also direct your requests to [email protected]. Document Number NA Document Title NA Acronyms Acronym Description NA Document Conventions Description Units of Measure FBK Feedback OE Output Enable °C degree Celsius PLL Phase Locked Loop Hz hertz Reference Input kHz kilohertz MHz megahertz µA microampere REFIN Document Number: 38-07252 Rev. *H Symbol Unit of Measure µF microfarad µs microsecond µV microvolt mA milliampere mm millimeter ms millisecond mV millivolt ns nanosecond pA picoampere pF picofarad ps picosecond V volt Page 9 of 13 CY2300 Errata This section describes the errors, workaround solution and silicon design fixes for Cypress zero delay clock buffers belonging to the families CY2300. Details include errata trigger conditions, scope of impact, available workaround and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number Device Characteristics CY2300SXC All Variants CY2300SXCT All Variants CY2300 Errata Summary Items Part Number Fix Status Start up lock time issue [CY2300] All Silicon fixed. New silicon available from WW 10 of 2013 CY2300 Qualification Status of fixed silicon Product Status: In production Qualification report last updated on 11/27/2012 http://www.cypress.com/?rID=72595 1. Start up lock time issue ■ Problem Definition Output of CY2300 fails to locks within 1 ms upon power up (as per datasheet spec). ■ Parameters Affected PLL lock time (tLOCK) ■ Trigger Condition(S) Start up ■ Scope of Impact It can impact the performance of system and its throughput. ■ Workaround Apply reference input (RefClk) before power up (VDD). If RefClk is applied after power up, noise gets coupled on the output and propagates back to the PLL causing it to take higher time to acquire lock. If reference input is present during power up, noise will not propagate to the PLL and device will start up normally without problems. ■ Fix Status This issue is due to design marginality. Two minor design modifications have been made to address this problem. a. Addition of VCO bias detector block as shown in the following figure keeps comparator power down till VCO bias is present and thereby eliminating the propagation of noise to feedback. b. Bias generator enhancement for successful initialization. Document Number: 38-07252 Rev. *H Page 10 of 13 CY2300 Document Number: 38-07252 Rev. *H Page 11 of 13 CY2300 Document History Page Document Title: CY2300, Phase-Aligned Clock Multiplier Document Number: 38-07252 Rev. ECN Orig. of Change Submission Date ** 110517 SZV 01/07/02 Changed from spec number 38-01039 to spec number 38-07252. *A 121854 RBI 12/14/02 Updated Operating Conditions: Added tPU parameter and its details. *B 246829 RGL 08/02/04 Updated Ordering Information: Added Lead Free Devices. *C 2568533 AESA 09/23/08 Removed Selector Guide. Removed Operating Conditions (for CY2300SI Industrial Temperature Devices). Removed Electrical Characteristics (for CY2300SI Industrial Temperature Devices). Removed Switching Characteristics (for CY2300SI Industrial Temperature Devices). Updated Ordering Information: Removed part numbers CY2300SC, CY2300SC, CY2300SI, CY2300SI, CY2300SXI and CY2300SXIT. Updated to new template. *D 3026183 BASH 09/01/2010 Removed Benefits. Updated Operating Conditions: Updated details in “Description” column corresponding to CL parameter (Added lower limit of 10 MHz for 18pF load capacitance). Added Ordering Code Definitions. Added Reference Documents, Acronyms and Units of Measure. *E 4126294 CINM 11/25/2013 Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *D to *F. Added Errata. Updated to new template. Completing Sunset Review. Description of Change *F 4325140 CINM 03/28/2014 Updated Errata. *G 4578443 TAVA 11/25/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *H 5240894 PSR 04/25/2016 Updated Features: Added “10 MHz to 166.67 MHz output operating range”. Added Thermal Resistance. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *F to *H. Updated to new template. Document Number: 38-07252 Rev. *H Page 12 of 13 CY2300 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-07252 Rev. *H Revised April 25, 2016 Page 13 of 13