CY23EP09
2.5 V or 3.3 V, 10 MHz–220 MHz, Low Jitter,
Nine-Output Zero Delay Buffer
2.5 V or 3.3 V, 10 MHz–220 MHz, Low Jitter, Nine-Output Zero Delay Buffer
Features
Functional Description
■
10 MHz to 220 MHz maximum operating range
■
Zero input-output propagation delay, adjustable by loading on
CLKOUT pin
■
Multiple low-skew outputs
❐ 45 ps typical output-output skew
❐ One input drives nine outputs, grouped as 4 + 4 + 1
■
25 ps typical cycle-to-cycle jitter
■
15 ps typical period jitter
■
Standard and High drive strength options
■
Available in space-saving 16-pin 150-mil small outline
integrated circuit (SOIC) or 4.4 mm thin shrunk small outline
package (TSSOP) packages
■
3.3 V or 2.5 V operation
■
Industrial temperature available
The CY23EP09 is a 2.5 V or 3.3 V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC or
TSSOP package. The -1H version operates up to 220 (200) MHz
frequencies at 3.3 V (2.5 V), and has higher drive than the -1
devices. All parts have on-chip PLLs that lock to an input clock
on the REF pin. The phase-locked loop (PLL) feedback is
on-chip and is obtained from the CLKOUT pad.
There are two banks of four outputs each, which can be
controlled by the Select inputs as shown in the Select Input
Decoding on page 4. If all output clocks are not required, BankB
can be three-stated. The select inputs also allow the input clock
to be directly applied to the outputs for chip and system testing
purposes.
The PLL enters a power-down mode when there are no rising
edges on the REF input (less than ~2 MHz). In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25 A of current draw.
In the special case when S2:S1 is 1:0, the PLL is bypassed and
REF is output from DC to the maximum allowable frequency. The
part behaves like a non-zero delay buffer in this mode, and the
outputs are not tri-stated.
The CY23EP09 is available in different configurations, as shown
in the Ordering Information table. The CY23EP09-1 is the base
part. The CY23EP09-1H is the high-drive version of the -1, and
its rise and fall times are much faster than the -1.
These parts are not intended for 5 V input-tolerant applications
For a complete list of related documentation, click here.
Block Diagram
PLL
MUX
REF
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
S2
Select Input
Decoding
CLKB2
CLKB3
S1
CLKB4
Cypress Semiconductor Corporation
Document Number: 38-07760 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 26, 2016
CY23EP09
Contents
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 3
Select Input Decoding ...................................................... 4
Zero Delay and Skew Control .......................................... 4
Absolute Maximum Conditions ....................................... 5
Operating Conditions ....................................................... 5
Electrical Specifications .................................................. 6
Electrical Specifications .................................................. 6
Thermal Resistance .......................................................... 7
Test Circuits ...................................................................... 7
Electrical Specifications .................................................. 8
Switching Waveforms .................................................... 10
Supplemental Parametric Information .......................... 11
Document Number: 38-07760 Rev. *F
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC®Solutions ....................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 2 of 19
CY23EP09
Pin Configuration
Figure 1. 16-pin SOIC or TSSOP pinout (Top View)
Top View
REF
CLKA1
1
16
2
15
CLKA2
VDD
3
14
4
13
GND
CLKB1
CLKB2
S2
5
12
6
11
7
10
8
9
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Pin Definitions
Pin No.
1
Signal
REF
Description
[1]
Input reference frequency
2
CLKA1
[2]
Buffered clock output, Bank A
3
CLKA2 [2]
Buffered clock output, Bank A
4
VDD
5
GND
3.3 V or 2.5 V supply
Ground
6
CLKB1
[2]
Buffered clock output, Bank B
7
CLKB2 [2]
Buffered clock output, Bank B
8
9
S2
[3]
S1
[3]
Select input, bit 2
Select input, bit 1
10
CLKB3
[2]
Buffered clock output, Bank B
11
CLKB4 [2]
Buffered clock output, Bank B
12
GND
13
VDD
Ground
3.3 V or 2.5 V supply
14
CLKA3
[2]
Buffered clock output, Bank A
15
CLKA4 [2]
Buffered clock output, Bank A
16
CLKOUT
[2]
Buffered output, internal feedback on this pin
Notes
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
Document Number: 38-07760 Rev. *F
Page 3 of 19
CY23EP09
Select Input Decoding
S2
S1
CLOCK A1–A4
CLOCK B1–B4
CLKOUT [4]
Output Source
PLL Shutdown
0
0
Three-state
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay.
The output driving the CLKOUT pin will be driving a total load of
5 pF (internal load) plus any additional load externally connected
to this pin. For applications requiring zero input-output delay, the
total load on each output pin (including CLKOUT) must be the
same. For example, if there is no external load on CLKOUT pin,
add 5 pF to each of the remaining outputs to match the internal
load on CLKOUT pin. If input-output delay adjustments are
required, the CLKOUT load may be changed to vary the delay
between the REF input and remaining outputs.
For zero output-output skew, be sure to load all outputs equally.
For further information refer to the application note titled
“AN1234 – Understanding Cypress’s Zero Delay Buffers”.
Note
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document Number: 38-07760 Rev. *F
Page 4 of 19
CY23EP09
Absolute Maximum Conditions
Storage temperature .................................. –65 °C to 150 °C
Supply voltage to ground potential ................–0.5 V to 4.6 V
DC input voltage ....................................VSS – 0.5 V to 4.6 V
Junction temperature ................................................. 150 °C
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2000 V
Operating Conditions
Parameter
Description
Min
Max
Unit
V
VDD3.3
3.3 V supply voltage
3.0
3.6
VDD2.5
2.5 V supply voltage
2.3
2.7
V
TA
Operating temperature (ambient temperature) – Commercial
0
70
°C
–40
85
°C
Load capacitance, <100 MHz, 3.3 V
–
30
pF
Load capacitance, <100 MHz, 2.5 V with High drive
–
30
pF
Load capacitance, <133.3 MHz, 3.3 V
–
22
pF
Load capacitance, <133.3 MHz, 2.5 V with High drive
–
22
pF
Load capacitance, <133.3 MHz, 2.5 V with Standard drive
–
15
pF
Operating temperature (ambient temperature) – Industrial
CL[5]
Load capacitance, >133.3 MHz, 3.3 V
–
15
pF
Load capacitance, >133.3 MHz, 2.5 V with High drive
–
15
pF
CIN
Input capacitance[6]
–
5
pF
BW
Closed-loop bandwidth (typical), 3.3 V
1–1.5
MHz
Closed-loop bandwidth (typical), 2.5 V
0.8
MHz
Output impedance (typical), 3.3 V High drive
29
Output impedance (typical), 3.3 V Standard drive
41
Output impedance (typical), 2.5 V High drive
37
ROUT
Output impedance (typical), 2.5 V Standard drive
tPU
Power-up time for all VDD’s to reach minimum specified voltage (power ramps must
be monotonic)
41
0.01
50
ms
Notes
5. Applies to Test Circuit #1.
6. Applies to both REF Clock and internal feedback path on CLKOUT.
Document Number: 38-07760 Rev. *F
Page 5 of 19
CY23EP09
Electrical Specifications
3.3 V DC
Parameter
Description
Min
Max
Unit
3.0
3.6
V
Input LOW voltage
–
0.8
V
VIH
Input HIGH voltage
2.0
VDD + 0.3
V
IIL
Input leakage current
0 < VIN < VIL
–
±10
A
IIH
Input HIGH current
VIN = VDD
–
100
A
VOL
Output LOW voltage
IOL = 8 mA (standard drive)
–
0.4
V
IOL = 12 mA (High drive)
–
0.4
V
IOH = –8 mA (standard drive)
2.4
–
V
IOH = –12 mA (High drive)
2.4
–
V
REF = 0 MHz (Commercial)
–
12
A
REF = 0 MHz (Industrial)
–
25
A
Unloaded outputs, 66-MHz REF
–
30
mA
Min
Max
Unit
2.3
2.7
V
VDD
Supply voltage
VIL
VOH
Output HIGH voltage
IDD (PD mode) Power down supply current
IDD
Supply current
Test Conditions
Electrical Specifications
2.5 V DC
Parameter
Description
Test Conditions
VDD
Supply voltage
VIL
Input LOW voltage
–
0.7
V
VIH
Input HIGH voltage
1.7
VDD + 0.3
V
IIL
Input leakage current
0<VIN < VDD
–
10
A
IIH
Input HIGH current
VIN = VDD
–
100
A
VOL
Output LOW voltage
IOL = 8 mA (Standard drive)
–
0.5
V
IOL = 12 mA (High drive)
–
0.5
V
IOH = –8 mA (Standard drive)
VDD – 0.6
–
V
IOH = –12 mA (High drive)
VDD – 0.6
–
V
REF = 0 MHz (Commercial)
–
12
A
REF = 0 MHz (Industrial)
–
25
A
Unloaded outputs, 66-MHz REF
–
45
mA
VOH
Output HIGH voltage
IDD (PD mode) Power down supply current
IDD
Supply current
Document Number: 38-07760 Rev. *F
Page 6 of 19
CY23EP09
Thermal Resistance
Parameter [7]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
16-pin SOIC
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, in accordance with
EIA/JESD51.
121
16-pin TSSOP Unit
111
°C/W
53
26
°C/W
Test Circuits
Figure 2. Test Circuit
Test Circuit # 1
V DD
CLK
0.1 F
OUTPUTS
C LOAD
V DD
0.1 F
GND
GND
Note
7. These parameters are guaranteed by design and are not tested.
Document Number: 38-07760 Rev. *F
Page 7 of 19
CY23EP09
Electrical Specifications
3.3 V and 2.5 V AC
Parameter
1/t1
Description
Maximum frequency
(input/output)
TIDC
Input duty cycle
t2 t1
Output duty cycle [9]
t3, t4
t3, t4
t5
t6
t7
tLOCK
Rise, fall time (3.3 V)
[8]
[9]
Rise, fall time (2.5 V) [9]
Output to output skew [9]
Delay,
REF rising edge to CLKOUT
rising edge [9]
Part to part skew
[9]
PLL lock time [9]
Test Conditions
Min
Typ
Max
Unit
3.3 V High drive
10
–
220
MHz
3.3 V Standard drive
10
–
167
MHz
2.5 V High drive
10
–
200
MHz
2.5 V Standard drive
10
–
133
MHz
<133.3 MHz
25
–
75
%
>133.3 MHz
40
–
60
%
<133.3 MHz
47
–
53
%
>133.3 MHz
45
–
55
%
Std drive, CL = 30 pF, <100 MHz
–
–
1.6
ns
Std drive, CL = 22 pF, <133.3 MHz
–
–
1.6
ns
Std drive, CL = 15 pF, <167 MHz
–
–
0.6
ns
High drive, CL = 30 pF, <100 MHz
–
–
1.2
ns
High drive, CL = 22 pF, <133.3 MHz
–
–
1.2
ns
High drive, CL = 15 pF, >133.3 MHz
–
–
0.5
ns
Std drive, CL = 15 pF, <133.33 MHz
–
–
1.5
ns
High drive, CL = 30 pF, <100 MHz
–
–
2.1
ns
High drive, CL = 22 pF, <133.3 MHz
–
–
1.3
ns
High drive, CL = 15 pF, >133.3 MHz
–
–
1.2
ns
All outputs equally loaded,
3.3 V supply,
2.5 supply standard drive
–
45
100
ps
All outputs equally loaded,
2.5 V supply high drive
–
–
110
ps
1.5
–
4.4
ns
PLL enabled @ 3.3 V
–100
–
100
ps
PLL enabled @2.5 V
–200
–
200
ps
Measured at VDD/2.
Any output to any output, 3.3 V supply
–
–
±150
ps
Measured at VDD/2.
Any output to any output, 2.5 V supply
–
–
±300
ps
Stable power supply, valid clocks
presented on REF and CLKOUT
pins
–
–
1.0
ms
PLL Bypass mode
Notes
8. For the given maximum loading conditions. See CL in Operating Conditions Table.
9. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07760 Rev. *F
Page 8 of 19
CY23EP09
Electrical Specifications (continued)
3.3 V and 2.5 V AC
Parameter
TJCC[10, 11]
TPER[10, 11]
Description
Cycle-to-cycle jitter, peak
Period jitter, peak
Test Conditions
Min
Typ
Max
Unit
3.3 V supply, >66 MHz, <15 pF
–
3.3 V supply, >66 MHz, <30 pF,
standard drive
–
25
55
ps
65
125
ps
3.3 V supply, >66 MHz, <30 pF,
high drive
–
53
100
ps
2.5 V supply, >66 MHz, <15 pF,
standard drive
–
35
95
ps
2.5 V supply, >66 MHz, <15 pF,
high drive
–
30
65
ps
2.5 V supply, >66 MHz, <30 pF,
high drive
–
75
145
ps
S2:S1 = 1:0 mode, 3.3 V, <15 pF,
standard drive
–
16
–
ps
S2:S1 = 1:0 mode, 3.3 V, <15 pF,
high drive
–
14
–
ps
S2:S1 = 1:0 mode, 2.5 V, <15 pF,
standard drive
–
23
–
ps
S2:S1 = 1:0 mode, 2.5 V, <15 pF,
high drive
–
22
–
ps
3.3 V supply, 66–100 MHz, <15 pF
–
20
75
ps
3.3 V supply, >100 MHz, <15 pF
–
15
45
ps
3.3 V supply, >66 MHz, <30 pF,
standard drive
–
40
100
ps
3.3 V supply, >66 MHz, <30 pF,
high drive
–
30
70
ps
2.5 V supply, >66 MHz, <15 pF,
standard drive
–
25
60
ps
2.5 V supply, 66–100 MHz, <15 pF,
high drive
–
25
60
ps
2.5 V supply, >100 MHz, <15 pF,
high drive
–
15
45
ps
S2:S1 = 1:0 mode, 3.3 V, <15 pF,
standard drive
–
28
–
ps
S2:S1 = 1:0 mode, 3.3 V, <15 pF,
high drive
–
24
–
ps
S2:S1 = 1:0 mode, 2.5 V, <15 pF,
standard drive
–
40
–
ps
S2:S1 = 1:0 mode, 2.5 V, <15 pF,
high drive
–
37
–
ps
Notes
10. Parameter is guaranteed by design and characterization. Not 100% tested in production.
11. Typical jitter is measured at 3.3 V or 2.5 V, 29 °C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be
found in the application note “Understanding Data Sheet Jitter Specifications for Cypress Clock Products.”
Document Number: 38-07760 Rev. *F
Page 9 of 19
CY23EP09
Switching Waveforms
Figure 3. Duty Cycle Timing
t1
t2
VDD/2
VDD/2
VDD/2
Figure 4. All Outputs Rise/Fall Time
2.0V(1.8V)
0.8V(0.6V)
OUTPUT 2.0V(1.8V)
0.8V(0.6V)
3.3V(2.5V)
0V
t4
t3
Figure 5. Output-Output Skew
OUTPUT
VDD/2
VDD/2
OUTPUT
t5
Figure 6. Input-Output Propagation Delay
INPUT
VDD/2
VDD/2
CLKOUT
t6
Figure 7. Part-Part Skew
VDD/2
Any output, Part 1 or 2
VDD/2
Any output, Part 1 or 2
t7
Document Number: 38-07760 Rev. *F
Page 10 of 19
CY23EP09
Supplemental Parametric Information
Delay REF Input to CLKA/B (ps)
Figure 8. 2.5 V Typical Room Temperature Graph for REF Input to CLKA/CLKB Delay Versus Loading Difference between
CLKOUT and CLKA/CLKB
1200
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
-1200
Standard D rive
H igh D rive
-20
-10
0
10
20
Load C LK O U T- Load C LK A/B (pF)
Data is shown for 66 MHz. Delay is a weak function of frequency.
Figure 9. 3.3 V Typical Room Temperature Graph for REF Input to CLKA/CLKB Delay Versus Loading Difference between
CLKOUT and CLKA/CLKB
1200
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
-1200
S tandard D rive
H igh D rive
-20
-10
0
10
20
Load C LK O U T- Load C LK A /B (pF)
Data is shown for 66 MHz. Delay is a weak function of frequency.
Document Number: 38-07760 Rev. *F
Page 11 of 19
CY23EP09
Supplemental Parametric Information (continued)
Figure 10. 3.6 V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature
200
175
150
125
100
15pF, -45C, Standard Drive
15pF, 90C, Standard Drive
30pF, -45C, Standard Drive
30pF, 90C, Standard Drive
15pF, -45C, High Drive
15pF, 90C, High Drive
30pF, -45C, High Drive
30pF, 90C, High Drive
75
50
25
33
66
100
133
166
200
233
Frequency (MHz)
Note that the 30-pF data above 100 MHz is beyond the data sheet specification of 22 pF.
Figure 11. 2.7 V Measured Supply Current Versus Frequency, Drive Strength, Loading, and Temperature
120
100
80
15pF, -45C, Standard Drive
60
15pF, 90C, Standard Drive
15pF, -45C, High Drive
40
15pF, 90C, High Drive
30pF, -45C, High Drive
30pF, 90C, High Drive
20
33
66
100
133
166
200
Frequency (MHz)
Note that the 30-pF high-drive data above 100bMHz is beyond the data sheet specification of 22 pF.
Document Number: 38-07760 Rev. *F
Page 12 of 19
CY23EP09
Supplemental Parametric Information (continued)
Figure 12. Typical 3.3 V Measured Cycle-to-cycle Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
350
15
15
30
30
300
250
pF,
pF,
pF,
pF,
S ta n d a rd D riv e
H ig h D riv e
S ta n d a rd D riv e
H ig h D riv e
200
150
100
50
0
0
50
100
150
200
250
F r e q u e n c y (M H z )
Figure 13. Typical 2.5 V Measured Cycle-to-cycle Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
350
1 5 p F , S t a n d a r d D r iv e
1 5 p F , H ig h D r iv e
3 0 p F , H ig h D r iv e
300
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
180
200
F re q u e n c y (M H z )
Figure 14. Typical 3.3 V Measured Period Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
250
15
15
30
30
200
pF,
pF,
pF,
pF,
S t a n d a r d D r iv e
H ig h D r iv e
S t a n d a r d D r iv e
H ig h D r iv e
150
100
50
0
0
50
100
150
200
250
F re q u e n c y (M H z )
Figure 15. Typical 2.5 V Measured Period Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
250
1 5 p F , S t a n d a r d D r iv e
1 5 p F , H ig h D r iv e
3 0 p F , H ig h D r iv e
200
150
100
50
0
0
50
100
150
200
250
F re q u e n c y (M H z )
Document Number: 38-07760 Rev. *F
Page 13 of 19
CY23EP09
Supplemental Parametric Information (continued)
Figure 16. Typical Phase-noise Data at 100 MHz (top) and 156.25 MHz (bottom) across VDD and Drive Strength [12]
SSB Phase Noise (dBc/Hz)
-90
2.5V, Standard Drive
2.5V, High Drive
-100
3.3V, Standard Drive
3.3V, High Drive
-110
-120
2.5V, Standard Drive
2.5V, High Drive
-130
100 MHz
-140
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
Offset Frequency (Hz)
1.E+06
1.E+07
1.E+08
SSB Phase Noise (dBc/Hz)
-90
2.5V, High Drive
3.3V, High Drive
-100
-110
3.3V, Standard Drive
2.5V, Standard Drive
-120
-130
156.25 MHz
-140
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
Offset Frequency (Hz)
1.E+06
1.E+07
1.E+08
Note
12. Typical jitter is measured at 3.3 V or 2.5 V, 29 °C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be
found in the application note “Understanding Data Sheet Jitter Specifications for Cypress Clock Products.”
Document Number: 38-07760 Rev. *F
Page 14 of 19
CY23EP09
Ordering Information
Ordering Code
Package Type
Operating Range
Pb-free
CY23EP09SXC-1
16-pin SOIC
Commercial
CY23EP09SXC-1T
16-pin SOIC – Tape and Reel
Commercial
CY23EP09SXI-1
16-pin SOIC
Industrial
CY23EP09SXI-1T
16-pin SOIC – Tape and Reel
Industrial
CY23EP09SXC-1H
16-pin SOIC
Commercial
CY23EP09SXC-1HT
16-pin SOIC – Tape and Reel
Commercial
CY23EP09SXI-1H
16-pin SOIC
Industrial
CY23EP09SXI-1HT
16-pin SOIC – Tape and Reel
Industrial
CY23EP09ZXC-1H
16-pin TSSOP
Commercial
CY23EP09ZXC-1HT
16-pin TSSOP – Tape and Reel
Commercial
CY23EP09ZXI-1H
16-pin TSSOP
Industrial
CY23EP09ZXI-1HT
16-pin TSSOP – Tape and Reel
Industrial
Ordering Code Definitions
CY 23EP09 S(X) C 1 (H) (T)
Tape and reel
Output Drive: 1=standard drive, 1H=high drive
Temperature Grade: I = Industrial, C = Commercial
Package:
S=SOIC, leaded
Z=TSSOP, leaded
SX=SOIC, Pb-free
ZX=TSSOP, Pb-free
Base device part number
CY23EP09 = 9-output zero delay buffer
Company ID: CY=Cypress
Document Number: 38-07760 Rev. *F
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CY23EP09
Package Diagrams
Figure 17. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *E
Figure 18. 16-pin TSSOP (4.40 mm Body) Z16.173/ZZ16.173 Package Outline, 51-85091
51-85091 *E
Document Number: 38-07760 Rev. *F
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CY23EP09
Acronyms
Acronym
Document Conventions
Description
Units of Measure
PCI
Personal Computer Interconnect
PLL
Phase Locked Loop
°C
degree Celsius
SDRAM
Synchronous Dynamic Random Access Memory
MHz
megahertz
SOIC
Small Outline Integrated Circuit
µA
microampere
TSSOP
Thin-Shrink Small Outline Package
mA
milliampere
ZDB
Zero Delay Buffer
ms
millisecond
ns
nanosecond
Document Number: 38-07760 Rev. *F
Symbol
Units of Measure
pF
picofarad
ps
picosecond
V
volt
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CY23EP09
Document History Page
Document Title: CY23EP09, 2.5 V or 3.3 V, 10 MHz–220 MHz, Low Jitter, Nine-Output Zero Delay Buffer
Document Number: 38-07760
Rev.
ECN No.
Issue Date
Orig. of
Change
**
345446
See ECN
RGL
New data sheet.
*A
355777
See ECN
RGL
Updated Electrical Specifications:
Updated values of t7 parameter (to agree with latest char results).
*B
401036
See ECN
RGL
Changed status from Preliminary to Final.
Updated Electrical Specifications:
Updated details in “Test Conditions” column corresponding to TJCC and TPER
parameters.
Updated Supplemental Parametric Information:
Added Figure 8.
Added Figure 16.
*C
3270178
06/01/2011
BASH
*D
4400992
06/10/2014
AJU
Updated Operating Conditions:
Updated values of Theta Ja and Theta Jc parameters (corresponding to 16-pin
TSSOP package).
Updated Package Diagrams:
spec 51-85068 – Changed revision from *C to *E.
spec 51-85091 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*E
4580603
11/26/2014
AJU
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams.
*F
5243008
04/26/2016
PSR
Updated Zero Delay and Skew Control:
Updated description.
Updated Operating Conditions:
Removed “Theta Ja”, “Theta Jc” parameters and their details.
Removed Note “Theta Ja, EIA JEDEC 51 test board conditions, 2S2P;
Theta Jc Mil-Spec 883E Method 1012.1.” and its reference.
Added Thermal Resistance.
Updated to new template.
Completing Sunset Review.
Document Number: 38-07760 Rev. *F
Description of Change
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated to new template.
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CY23EP09
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2010-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
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Document Number: 38-07760 Rev. *F
Revised April 26, 2016
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