CYWB0124AB CYWB0125AB ® West Bridge Antioch™ USB/Mass Storage Peripheral Controller West Bridge® Antioch™ USB/Mass Storage Peripheral Controller Features Applications ■ ■ Cellular phones ■ Portable media players ■ Personal digital assistants ■ Digital cameras ■ Portable video recorder SLIM™ architecture, enabling simultaneous and independent data paths between processor and USB, and between USB and mass storage ■ High speed USB at 480 Mbps ❐ USB-2.0 compliant ❐ Integrated USB 2.0 transceiver, smart serial interface engine ❐ 16 programmable endpoints ■ Mass storage device support ❐ MMC/MMC+/SD/CE-ATA ❐ NAND flash: x8 or x16, SLC ❐ Full NAND management (ECC, wear leveling) ■ Memory mapped interface to main processor ■ DMA slave support Supports Microsoft® media transfer protocol (MTP) with optimized data throughput ■ Ultra low power, 1.8 V core operation ■ Low power modes ■ Small footprint, 6 × 6 mm VFBGA, and less than 4 × 4 mm WLCSP ■ Selectable clock input frequencies ❐ 19.2 MHz, 24 MHz, 26 MHz, and 48 MHz ■ Logic Block Diagram West Bridge Antioch Processor Interface P 8051 MCU High-Speed USB 2.0 XCVR Control Registers U SLIMTM Mass Storage Interface SD/MMC+/CE-ATA NAND S Cypress Semiconductor Corporation Document Number: 001-07978 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 20, 2013 CYWB0124AB CYWB0125AB Contents Functional Overview ........................................................ 3 SLIM™ Architecture .................................................... 3 Turbo-MTP Support ..................................................... 3 8051 Microprocessor ................................................... 3 Configuration and Status Registers ............................. 3 Processor Interface (P-port) ........................................ 3 USB Interface (U-Port) ................................................ 3 Mass Storage Support (S-Port) ................................... 3 Clocking ....................................................................... 4 Power Domains ........................................................... 5 Power Modes .............................................................. 5 Antioch in WLCSP ....................................................... 6 Absolute Maximum Ratings .......................................... 12 Operating Conditions ..................................................... 12 DC Characteristics ......................................................... 12 USB Transceiver ....................................................... 14 Capacitance .................................................................... 14 AC Test Loads and Waveforms ..................................... 14 Document Number: 001-07978 Rev. *M AC Characteristics ......................................................... 15 USB Transceiver ....................................................... 15 P-Port Interface ......................................................... 15 SD/MMC Parameters ................................................ 23 Reset and Standby Timing Parameters .................... 24 Ordering Information ...................................................... 25 Ordering Code Definitions ......................................... 25 Package Diagrams .......................................................... 26 Acronyms ........................................................................ 27 Document Conventions ................................................. 27 Units of Measure ....................................................... 27 Document History Page ................................................. 28 Sales, Solutions, and Legal Information ...................... 31 Worldwide Sales and Design Support ....................... 31 Products .................................................................... 31 PSoC® Solutions ...................................................... 31 Cypress Developer Community ................................. 31 Technical Support ..................................................... 31 Page 2 of 31 CYWB0124AB CYWB0125AB Functional Overview SLIM™ Architecture The Simultaneous Link to Independent Multimedia (SLIM) architecture allows three different interfaces (the P-port, the S-port, and the U-port) to connect to one another independently. With this architecture, using Antioch™ to connect a device to a PC through an USB does not disturb the functions of the device. It still accesses mass storage at the same time the PC is synchronizing with the main processor. Processor Interface (P-port) Communication with the external processor is realized through a dedicated processor interface. This interface supports both synchronous and asynchronous SRAM mapped memory accesses. This ensures straightforward electrical communications with the processor that also has other devices connected on a shared memory bus. Asynchronous accesses reach a bandwidth of up to 66.7 MBps. Synchronous accesses are performed at 33 MHz across 16 bits for up to 66.7 MBps bandwidth. The SLIM architecture enables new usage models, in which a PC accesses a mass storage device independent of the main processor, or enumerates access to both the mass storage and the main processor at the same time. The memory address is decoded to access any of the multiple endpoint buffers inside Antioch. These endpoints serve as buffers for data between each pair of ports, for example, between the processor port and the USB port. The processor writes and reads into these buffers through the memory interface. In a handset, this typically enables the user to use the phone as a thumb drive or download media files to the phone while still having full functionality available on the phone. The same phone even functions as a modem to connect the PC to the web. Access to these buffers is controlled by using either a DMA protocol or an interrupt to the main processor. These two modes are configured by the external processor. Turbo-MTP Support Turbo-MTP is an implementation of Microsoft’s Media Transfer Protocol (MTP) enabled by West Bridge® Antioch™. In the current generation of MTP-enabled mobile phones, all protocol packets need to be handled by the main processor. West Bridge Turbo-MTP switches these packet types and sends only control packets to the processor, while data payloads are written directly to mass storage. This brings the high performance of West Bridge to MTP. For more information on Turbo-MTP, refer to the application note AN48864 “Performance Optimization by West Bridge Controllers with Turbo-MTP”. 8051 Microprocessor The 8051 microprocessor embedded in Antioch does basic transaction management for all the transactions between the P-port, the S-port, and the U-port. The 8051 does not reside in the data path; it manages the path. The data path is optimized for performance. The 8051 executes firmware that supports NAND, SD, and MMC devices at the S-port. For the NAND device, the 8051 firmware follows the Smart Media algorithm to support: ■ Physical to Logical Management ■ ECC Correction ■ Wear Leveling ■ NAND Flash Bad Block Handling Configuration and Status Registers The West Bridge Antioch device includes Configuration and Status registers that are accessible as memory mapped registers through the processor interface. The Configuration registers allow the system to specify certain behavior from Antioch. For example, it masks certain Status registers from raising an interrupt. The Status registers convey the status of different parameters of Antioch, such as the addresses of buffers for read operations. Document Number: 001-07978 Rev. *M As a DMA slave, Antioch generates a DMA request signal to signify to the main processor that it is ready to read from or write to a specific buffer. The external processor monitors this signal and polls Antioch for the specific buffers ready for read or write. It then performs the appropriate read or write operations on the buffer through the processor interface. This way, the external processor only deals with the buffers to access a multitude of storage devices connected to Antioch. In the Interrupt mode, Antioch communicates important buffer status changes to the external processor using an interrupt signal. The external processor then polls Antioch for the specific buffers ready for read or write and performs the appropriate read or write operations through the processor interface. USB Interface (U-Port) In accordance with the USB 2.0 specification, Antioch operates in Full Speed USB mode in addition to High Speed USB mode. The USB interface consists of the USB transceiver. The USB interface accesses and also is accessed by both the P-port and the S-port. The Antioch USB interface supports programmable CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints. Mass Storage Support (S-Port) The S-port is configured in two different modes, either simultaneously supporting an SD/MMC+ port and a x8 NAND port or supporting a unique x16 NAND access port. The NANDCFG Ball is used to set the configuration of the S-port as either 16-bit NAND or 8-bit NAND and SD/MMC. The 16-bit interface is only used when there is no other mass storage device connected to the S-port. Note that in the WLCSP option, the S-port is not configurable; it only supports a single SD/MMC+ port with no NAND port. Antioch also includes two chip enables, NAND_CE# and NAND_CE2#, that enable to access two different NANDs alternately. Page 3 of 31 CYWB0124AB CYWB0125AB NAND Port (S-Port) Clocking Antioch, as part of its mass storage management functions, fully manages a NAND device. The embedded 8051 manages the actual reading and writing of the NAND along with its required protocols. It performs standard NAND management functions such as ECC and wear leveling. Antioch allows either to connect a crystal between the XTALIN and XTALOUT balls or connect an external clock at the XTALIN ball. The power supply level at the crystal supply XVDDQ determines whether a crystal or a clock is provided. If XVDDQ is detected as 1.8 V, Antioch assumes that a clock input is provided. This clock input must be a 1.8 V square wave. To connect a crystal, XVDDQ must be 3.3 V. Note that the clock inputs at 3.3 V level are not supported. SLC NAND devices are supported on all devices in the Antioch family. The write performance for connecting to a single SLC NAND is up to 9 MBps, while read performance is up to 13 MBps. SD/MMC/CE-ATA Port (S-Port) When Antioch is configured through NANDCFG to support MMC/SD/CE-ATA, this interface supports: ■ The MultiMediaCard System Specification, MMCA Technical Committee, Version 4.1 ■ SD Memory Card Specification - Part 1, Physical Layer Specification, SD Group, Version 1.10, October 15, 2004, and Version 2.0, November 9, 2005 ■ CE-ATA Digital Protocol, Rev 1.1, 28 September, 2005 and CE-ATA Host Design Guidance, Rev 1.0, 29 September, 2005 West Bridge Antioch provides support for 1-bit and 4-bit SD cards: 1-bit, 4-bit, and 8-bit MMC, and MMC+. For the SD, MMC/MMC Plus card, this block supports one card for one physical bus interface. Antioch supports SD commands including the multisector program command that is handled by the API. Compatibility with specific CE-ATA HDD is subject to confirmation with drive vendors. CYWB0124AB supports crystals only at 19.2, 24, and 26 MHz. At 48 MHz, only clock inputs are supported. Clock inputs are supported at all frequencies. Antioch has an on-chip oscillator circuit that uses an external 19.2/24/26 MHz (±150 ppm) crystal with the following characteristics: ■ Parallel resonant ■ Fundamental mode ■ 1 mW drive level ■ 12 pF (5% tolerance) load capacitors  Figure 1. Capacitor C1 24 MHz 12 pF C2 12 pF PLL 12 pF capacitor values assumes a trace capacitance of 3 pF per side on a four-layer FR4 PCA Table 1. External Clock Requirements Parameter Description Specification Min Max Unit PN_100Hz Input Phase Noise at 100 Hz Offset – –75 dBc/Hz PN_1k Input Phase Noise at 1 kHz Offset – –104 dBc/Hz PN_10k Input Phase Noise at 10 kHz Offset – –120 dBc/Hz PN_100k Input Phase Noise at 100 kHz Offset – –128 dBc/Hz PN_1M Input Phase Noise at 1 MHz Offset – –130 dBc/Hz Duty Cycle 30 70 % Maximum Frequency Deviation – 150 ppm Overshoot – 3 % Undershoot – -3 % Note 1. Specified as typical for 24 MHz frequency. Load capacitance varies with crystal vendor specifications and frequency used. Document Number: 001-07978 Rev. *M Page 4 of 31 CYWB0124AB CYWB0125AB This on-chip PLL multiplies the 19.2/24/26/48 MHz frequency up to 480 MHz, as required by the transceiver/PHY. The internal counters divide it down for use as the 8051 clock. The 8051 clock frequency is 48 MHz. The XTALIN frequency is independent of the clock/data rate of the 8051 microprocessor or any of the device interfaces (including P-port and S-port). The internal PLL applies the proper clock multiply option depending on the input frequency. Noise guideline for all supplies except AVDDQ is a maximum of 100 mV p-p. All I/O supplies of Antioch are ON when a system is active, even if Antioch is not used. The core VDD is also deactivated at any time to preserve power, provided that there is a minimum impedance of 1 k between the VDD Ball and ground. All I/Os tri-state when the core is disabled. For applications that use an external clock source to drive XTALIN, the XTALOUT Ball is left floating. The external clock is a square wave that conforms to high and low voltage levels mentioned in Table 3 on page 12 and the rise and fall time specifications in Figure 5 on page 14. The external clock source also stops high or low and is not toggling to achieve the lowest possible current consumption. The requirements for an external clock source are shown in Capacitance on page 14. The power supplies are independently sequenced without damaging the part. All power supplies are up and stable before the device operates. If all supplies are not stable, the remaining domains are in low power (standby) mode. Power Supply Sequence Flexible I/Os Power Domains Each of Antioch’s ports operate between 1.8 V and 3.3 V with adjustable slew rate for each port and adjustable drive strength for each port for the I/Os. The slew rate and drive strength are controlled by registers. Antioch has multiple power domains that serve different purposes within the chip. Power Modes *VDDQ. This refers to a group of five independent supply domains for the digital I/Os. The nominal voltage level on these supplies are 1.8 V, 2.5 V, or 3.3 V. Specifically, the four separate I/O power domains are: In addition to the normal operating mode, Antioch contains several low power modes when normal operation is not required. Normal Mode ■ PVDDQ – P-port processor interface I/O ■ SNVDDQ – S-port NAND interface I/O In this mode, Antioch is fully functional. This is the mode in which the data transfer functions described in this datasheet are performed. ■ SSVDDQ – S-port SD interface I/O Suspend Mode ■ GVDDQ – Other miscellaneous I/O This mode is entered internally by 8051 (external processor only initiates entry into this mode through Mailbox commands). This mode is exited by the D+ bus going low, GPIO going to a predetermined state, or by asserting CE# LOW. UVDDQ. This is the 3.3 V nominal supply for the USB I/O and some analog circuits. It also supplies power to the USB transceiver. VDD33. This supply is required for the power sequence control circuits. For more information, see Table 2 on page 7. In Suspend mode of Antioch: ■ The clocks are shut off. VDD. This is the supply voltage for the logic core. The nominal supply voltage level is 1.8 V. This supplies the core logic circuits. The same supply is also used for AVDDQ. ■ All I/Os maintain their previous state. ■ Core power supply are retained. AVDDQ. This is the 1.8 V supply for PLL and USB serializer analog components. The same supply is also used for VDD. Maximum permitted noise on AVDDQ is 20 mV p-p. ■ The states of the Configuration registers, endpoint buffers, and the program RAM are maintained. All transactions are completed before Antioch enters Suspend mode (state of outstanding transactions are not preserved). ■ The firmware resumes its operation from where it has suspended, because the program counter is not reset. ■ The only inputs that are sensed are RESET#, GPIO, D+, and CE#. The last three are wakeup sources (each is individually enabled or disabled). ■ Hard reset is performed by asserting the RESET# input and Antioch performs initialization. XVDDQ. This is the clock I/O supply. 3.3 V for XTAL or 1.8 V for an external clock. Figure 2. Antioch Power Supply Domains *VDDQ VDD UVDDQ D+ I/O D-CORE USB-IO D- Document Number: 001-07978 Rev. *M Page 5 of 31 CYWB0124AB CYWB0125AB Standby Mode Standby mode is a low power state. This is the lowest power mode of Antioch while still maintaining external supply levels. This mode is entered through the deassertion of the WAKEUP input ball or through internal register settings. It is exited by asserting the WAKEUP Ball if the mode is entered by deasserting the WAKEUP Ball. Exiting Standby mode is also accomplished by asserting CE# LOW or processor writes to Internal registers. requirement of a minimum impedance of 1 k between the VDD ball and ground remains unchanged. In the WLCSP option, AVDDQ is internally tied to XVDDQ. As a result, the clock input at XTALIN must be brought to a steady LOW level before entry into Core Power Down mode. Antioch in WLCSP In this mode, the following characteristics apply: Antioch is available in a Wafer Level Chip Scale Package (WLCSP) with 81 balls. The WLCSP differs from the VFBGA in the following ways: ■ ■ The XTALIN input only accepts clock inputs and no crystals. The XTALOUT ball and the XVDDQ power domain do not exist in this package. The XVDDQ power domain is internally combined with AVDDQ. ■ Since AVDDQ and as a result, XVDDQ, are OFF in the Core Power Down mode, the clock input at XTALIN must be brought to a steady LOW level before entry into Core Power Down mode. ■ NAND functionality is not available. SNVDDQ does not exist as a separate power domain. It is internally combined with SSVDDQ. ■ The P-port CLK ball and the P-port synchronous mode operation are not available. The P-port is operated only in asynchronous mode. ■ GVDDQ is not a separate power domain in the WLCSP package. It is internally combined with PVDDQ. ■ Availability of specific signals on the WLCSP option is detailed in Table 2 on page 7. All Configuration register settings and program RAM contents are preserved. However, data in the buffers or other parts of the data path, if any, is not guaranteed in values. Therefore, the external processor ensures that the required data is read before Antioch is moved into this Standby mode. ❐ The program counter is reset upon waking up from Standby mode. ❐ All outputs are tri-stated (except UVALID), and I/O is placed in input only configuration. Values of I/Os in Standby mode are listed in the Table 2 on page 7. ❐ Core power supply is retained. ❐ Hard reset is performed by asserting the RESET# input, and Antioch performs initialization. ❐ PLL is disabled. Core Power Down Mode The core power supply VDD is powered down in this mode. AVDDQ is tied to the same supply as VDD and as a result, is also powered down. The endpoint buffers, configuration registers, and the program RAM do not maintain state. It is necessary to reload the firmware upon exiting from this mode. It is required that all VDDQ power supplies (except AVDDQ) are on and not powered down in this mode. VDD33 must remain ON and the Document Number: 001-07978 Rev. *M Page 6 of 31 CYWB0124AB CYWB0125AB The Ball Assignment table for CYWB0124AB, CYWB0125AB follows. Table 2. Ball Assignment [2, 3, 4] VFBGA WLCSP P Port Ball Name I/O Ball Description I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Clock for P-port Chip Select for P-port. Active LOW Bit 7 of Address Bus for P-port Bit 6 of Address Bus for P-port Bit 5 of Address Bus for P-port Bit 4 of Address Bus for P-port Bit 3 of Address Bus for P-port Bit 2 of Address Bus for P-port Bit 1 of Address Bus for P-port Bit 0 of Address Bus for P-port Bit 15 of Data Bus for P-port Bit 14 of Data Bus for P-port Bit 13 of Data Bus for P-port Bit 12 of Data Bus for P-port Bit 11 of Data Bus for P-port Bit 10 of Data Bus for P-port Bit 9 of Data Bus for P-port Bit 8 of Data Bus for P-port Bit 7 of Data Bus for P-port Bit 6 of Data Bus for P-port Bit 5 of Data Bus for P-port Bit 4 of Data Bus for P-port Bit 3 of Data Bus for P-port Bit 2 of Data Bus for P-port Bit 1 of Data Bus for P-port Bit 0 of Data Bus for P-port Address Valid for P-port. Valid during asynchronous mode. ADV# deassertion causes to latch the address. Output Enable. Controls the data bus output drive. Ignored during write cycle. Active LOW. Write Enable. Signals a read (HIGH) or write (LOW) access cycle. Interrupt Request. Assertion indicates that an interrupt event has occurred. Active LOW. DMA Request. Assertion indicates to Processor that it is ready to read or write one or more endpoints. It reflects register CY_AN_MEM_P0_DRQ EPnDRQ assertions. Active LOW or HIGH (programmable). DMA Acknowledgement. Assertion indicates DMA acknowledgement from processor. Is configured in ACK mode (asserted throughout DMA transfer) or EOB mode (pulsed at end of DMA transfer). Active LOW or HIGH (programmable). J2 G1 H3 H2 H1 J3 J1 K3 K2 K1 G2 G3 F1 F2 F3 E1 E2 E3 D1 D2 D3 C1 C2 C3 B1 B2 A1 N/A G8 J6 J7 J8 H6 H7 J9 H8 H9 G9 G7 F8 F9 F7 E9 E8 E7 D9 D8 D7 C9 C8 C7 B9 B8 A9 CLK CE# A A A A A A A A DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ ADV# B3 A8 OE# I A2 B7 WE# I A3 A7 INT# O A4 C6 DRQ# O B4 C5 DACK# I Standby Reset Power Domain Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z PVDDQ VGND Z Z Z Z Z Z Z Z Z Z - - - - Z Z Z Z - - Notes 2. Unused inputs: Must be connected to HIGH/VDD or LOW/GND (negligible difference in current drawn) logic level, through a single 10 K pull-up resistor. The only exceptions are WAKEUP, NANDCFG and CLK. WAKEUP is tied HIGH for normal operation and NANDCFG is tied LOW for unused NAND with SD or tied HIGH for 16-bit NAND with no SD. CLK is tied LOW for asynchronous P-port operation. 3. Unused I/Os: For lowest leakage, unused I/Os must be connected to a HIGH logic level. It is recommended that connection to the power supply is through a single 10k ohm pull-up resistor for all unused I/Os. 4. No Antioch balls have internal pull-up or pull-down resistors. Input/output balls may require external pull-up or pull-down resistors depending on the application. The pull-up resistors used to indicate speed capability on the USB are included in Antioch and need not be connected externally. 5. The Reset column indicates the state of signals during reset (RESET# asserted). The Standby column indicates signal state during Standby (low power operating mode through WAKEUP deassertion) or core VDD deactivation. Document Number: 001-07978 Rev. *M Page 7 of 31 CYWB0124AB CYWB0125AB Table 2. Ball Assignment [2, 3, 4] (continued) VFBGA WLCSP Ball Name I/O Ball Description I/O Serve as SD_D for SD port or NAND_IO for NAND Upper I/O port depending on NANDCFG selection. NAND configuration is not available in WLCSP. Serve as SD_D for SD port or NAND_IO for NAND Upper I/O port depending on NANDCFG selection. NAND configuration is not available in WLCSP. Serve as SD_D for SD port or NAND_IO for NAND Upper I/O port depending on NANDCFG selection. NAND configuration is not available in WLCSP. Serve as SD_D for SD port or NAND_IO for NAND Upper I/O port depending on NANDCFG selection. NAND configuration is not available in WLCSP. Serve as SD_D for SD port or NAND_IO for NAND Upper I/O port depending on NANDCFG selection. NAND configuration is not available in WLCSP. Serve as SD_D for SD port or NAND_IO for NAND Upper I/O port depending on NANDCFG selection. NAND configuration is not available in WLCSP. Serve as SD_D for SD port or NAND_IO for NAND Upper I/O port depending on NANDCFG selection. NAND configuration is not available in WLCSP. Serve as SD_D for SD port or NAND_IO for NAND Upper I/O port depending on NANDCFG selection. NAND configuration is not available in WLCSP. Clock output for the SD interface. Frequency is changed and clock is disabled through firmware control. SD Command/Response Ball. SD Power Control. This GPIO is used to control SD/MMC card power FET if present. HIGH indicates on, LOW indicates off. SD Write Protection Detection. Connected to GPIO for firmware detection. HIGH indicates that the device connected to the SD port has write protect enabled. NAND_IO for NAND Upper I/O port NAND_IO for NAND Upper I/O port NAND_IO for NAND Upper I/O port NAND_IO for NAND Upper I/O port NAND_IO for NAND Upper I/O port NAND_IO for NAND Upper I/O port NAND_IO for NAND Upper I/O port NAND_IO for NAND Upper I/O port G9 H2 SD and 8-bit NAND 16-bit NAND Configuration Configuration SD_D NAND_IO G10 H1 SD_D NAND_IO I/O F9 G3 SD_D NAND_IO I/O F10 G2 SD_D NAND_IO I/O E9 F2 SD_D NAND_IO I/O E10 E3 SD_D NAND_IO I/O D9 E2 SD_D NAND_IO I/O D10 E1 SD_D NAND_IO I/O F8 G1 SD_CLK N/A O G8 H8 H3 G4 SD_CMD SD_POW N/A N/A I/O O H10 D1 SD_WP N/A I K7 K8 J8 K9 J9 H9 K10 J10 K6 N/A N/A N/A N/A N/A N/A N/A N/A N/A NAND_IO NAND_IO NAND_IO NAND_IO NAND_IO NAND_IO NAND_IO NAND_IO NAND_CLE NAND_IO NAND_IO NAND_IO NAND_IO NAND_IO NAND_IO NAND_IO NAND_IO NAND_CLE I/O I/O I/O I/O I/O I/O I/O I/O O J6 J5 N/A N/A NAND_ALE NAND_CE# NAND_ALE NAND_CE# O O K4 H6 J7 N/A N/A N/A NAND_RE# NAND_WE# NAND_WP# NAND_RE# NAND_WE# NAND_WP# O O O J4 N/A NAND_R/B# NAND_R/B# I K5 N/A NAND_CE2# NAND_CE2# O S Port NAND Command Latch Enable NAND Address Latch Enable  NAND Chip Enable. Active LOW.  NAND Read Enable. Active LOW. NAND Write Enable. Active LOW. NAND Write Protect. Active LOW. NAND Ready/Busy. NAND output is Open Drain. Active LOW. NAND Chip Enable 2. Allows to access the second NAND device. Active LOW.  Standby Reset Power Domain Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z - - Z Z Z Z Z Z Z Z Z Z Z Z Z Z - - Z Z SSVDDQ VGND SNVDDQ VGND Note 6. The NAND_CE#, NAND_CE2#,NAND_WP#, NAND_CLE, and NAND_ALE pins are used as General Purpose Outputs if NAND functionality is not used. Document Number: 001-07978 Rev. *M Page 8 of 31 CYWB0124AB CYWB0125AB Table 2. Ball Assignment [2, 3, 4] (continued) VFBGA WLCSP U-port Ball Name Standby Reset Power Domain I/O Ball Description A5 A6 A7 A4 A5 B4 D+ D– UVALID I/O/Z I/O/Z O Z Z Low Z Z Low A8 A2 XTALIN I - - B8 N/A XTALOUT O Z Z C10 C2 RESET# I - - B10 N/A RESETOUT O Z Low C9 D8 D3 D2 GPIO GPIO I/O I/O Z Z Z Z C7 C1 WAKEUP I - - C5 C3 XTALSLC I - - C4 C4 XTALSLC i - - C6 N/A NANDCFG I - - E8 B1 TEST I - - C8 D4 TEST I - - D7 A1 TEST I - - D4, H4 H5 E5, A6 N/A PVDDQ SNVDDQ Power Power - - B5 H7 UVDDQ SSVDDQ Power Power - - D6 B5 F1, F3, F4, G5, H4, H5, J2, J3, J4, J5 N/A USB D+ USB D– External USB Switch Control. Reflects value of register CY_AN_MEM_PMU_UPDATE.UVALID. Input for either crystal or clock signal. XVDDQ is 3.3 V for crystal input; XVDDQ is 1.8 V for clock input. Output to connect to feedback input of crystal. Is left floating when external clock at XTALIN. Reset. Asserted to place Antioch into reset mode and subsequent initialization. Active LOW. Reset Out. Deasserted LOW when RESET# is asserted LOW. Asserted HIGH after RESET# is deasserted and initialization is complete. Reflects value of RSTCMPT bit. General purpose input/output. General purpose input/output.GPIO is used for SD Card Detect with firmware detection. LOW indicates card is inserted. Wake Up Signal. 1 = normal operation, 0 = low power “sleep” mode. Is asserted for Antioch to initialize. Clock Select. For CYWB0124AB, XTALSLC[1:0] is decoded as: 00 = 19.2 MHz, 01 = 24 MHz, 10 = 48 MHz, 11 = 26 MHz. Clock Select. For CYWB0124AB, XTALSLC[1:0] is decoded as: 00 = 19.2 MHz, 01 = 24 MHz, 10 = 48 MHz, 11 = 26 MHz. S-port Configuration. ‘0’ selects 8-bit NAND and SD/MMC configuration. ‘1’ selects 16-bit NAND configuration. Test mode selection. Is tied to VGND for normal operation (CMOS level inputs). Test mode selection. Is tied to VGND for normal operation (CMOS level inputs). Test mode selection. Is tied to VGND for normal operation (CMOS level inputs). Power for P-port I/O. 1.8 V, 2.5 V, or 3.3 V nominal. Power for NAND port I/O. 1.8 V, 2.5 V, or 3.3 V nominal. Power for USB I/O. 3.3 V nominal. Power for SD port, is connected to SNVDDQ if using 16-bit NAND. 1.8 V, 2.5 V, or 3.3 V nominal. GVDDQ Power - - B9 B3 AVDDQ Power - - B7 N/A XVDDQ Power - - D5, G4, G5, G6, G7, F7 A10 D6, F6, G6, J1 VDD Power Power for miscellaneous I/O. 1.8 V, 2.5 V, or 3.3 V nominal. Power for internal PLL and USB serializer. 1.8 V nominal. Power for crystal or clock I/O. 1.8 V (clock) or 3.3 V (crystal) nominal. Power for core. 1.8 V nominal. - - Power sequence control supply. 3.3 V nominal. - - A3 B2 B6, D5, E4, E6, F5 VDD33 UVSSQ AVSSQ VGND Power B6 A9 E4, E5, E6, E7, F4, F5, F6 Power Power Power Ground for all USB. Ground for PLL. Ground for core. - - Others Config Power N/A UVDDQ UVSSQ XVDDQ VGND GVDDQ VGND Notes 7. XTALOUT is driven HIGH during Standby mode. XTALOUT operates the same during RESET# assertion and Normal mode: fixed HIGH when XVDDQ is 1.8 V (ext clock) and actively toggles when XVDDQ is 3.3 V (crystal). 8. When RESET# is asserted, the device enters reset state and WAKEUP is ignored. 9. VDD33: In CYWB0124AB, the Ball is no-connect internally. It handles power sequence control in future West Bridge products. When migrating to Astoria, it is connected to the highest supply to the device. If USB is used, for example, then VDD33 is connected to nominal 3.3 V (because 3.3 V is required for USB). VDD33 is always supplied in Astoria. Document Number: 001-07978 Rev. *M Page 9 of 31 CYWB0124AB CYWB0125AB Figure 3. CYWB0124AB 100-ball VFBGA – Top View Top View 1 2 3 4 5 6 7 8 9 10 A ADV# WE# INT# DRQ# D+ D- UVALID XTALIN AVSSQ VDD33 A B DQ DQ OE# DACK# UVDDQ UVSSQ XVDDQ XTALOUT AVDDQ RESETOUT B C DQ DQ DQ XTALSLC XTALSLC NANDCFG WAKEUP TEST GPIO RESET# C D DQ DQ DQ PVDDQ VDD GVDDQ TEST GPIO SD_D SD_D D E DQ DQ DQ VGND VGND VGND VGND TEST SD_D SD_D E F DQ DQ DQ VGND VGND VGND VDD SD_CLK SD_D SD_D F G CE# DQ DQ VDD VDD VDD VDD SD_CMD SD_D SD_D G H A A A PVDDQ SNVDDQ NAND_WE# SSVDDQ SD_POW NAND_IO SD_WP H J A CLK A NAND_R/B# NAND_CE# NAND_ALE NAND_WP# NAND_IO NAND_IO NAND_IO J K A A A NAND_RE# NAND_CE2# NAND_CLE NAND_IO NAND_IO NAND_IO NAND_IO K 1 2 3 4 5 6 7 8 9 10 POWER DOMAIN KEY UVDDQ GVDDQ SSVDDQ VGND PVDDQ SNVDDQ Document Number: 001-07978 Rev. *M Page 10 of 31 CYWB0124AB CYWB0125AB Figure 4. CYWB0124AB 81-ball WLCSP – Top View 1 2 3 4 5 6 7 8 9 A TEST XTALIN UVSSQ D+ D- PVDDQ INT# OE# ADV# A B TEST AVSSQ AVDDQ UVALID UVDDQ VGND WE# DQ DQ B C WAKEUP RESET# DACK# DRQ# DQ DQ DQ C D SD_WP GPIO GPIO TEST VGND VDD DQ DQ DQ D E SD_D SD_D SD_D VGND PVDDQ VGND DQ DQ DQ E F SSVDDQ SD_D SSVDDQ SSVDDQ VGND VDD DQ DQ DQ F G SD_CLK SD_D SD_D SD_POW SSVDDQ VDD DQ CE# DQ G H SD_D SD_D SD_CMD SSVDDQ SSVDDQ A A A A H J VDD SSVDDQ SSVDDQ SSVDDQ SSVDDQ A A A A J 1 2 3 4 5 6 7 8 9 XTALSLC XTALSLC POWER DOMAIN KEY UVDDQ AVDDQ, VDD SSVDDQ VGND PVDDQ Document Number: 001-07978 Rev. *M Page 11 of 31 CYWB0124AB CYWB0125AB Absolute Maximum Ratings DC voltage applied to outputs in High Z State ..................... –0.5 V to VDDQ+0.5 V Operating range specifies temperature and voltage boundary conditions for safe operation of the device. Operation outside these boundaries may affect the performance and life of the device. These user guidelines are not tested. Static discharge voltage (ESD) from JESD22-A114 ................................................. > 2000 V Storage temperature ................................ –65 °C to +150 °C Maximum output short circuit current for all I/O configurations. (VOUT = 0 V) .............. –100 mA Ambient temperature with power supplied (Industrial) ........................ –40 °C to +85 °C Latch-up current .................................................... > 200 mA Operating Conditions Supply voltage to ground potential VDD, AVDDQ ................................................–0.5 V to +2.0 V TA (Ambient temperature under bias) Industrial .................................................... –40 °C to +85 °C GVDDQ, PVDDQ, SSVDDQ, SNVDDQ, UVDDQ and VDD33 and XVDDQ ...............–0.5 V to +4.0 V VDD, AVDDQ supply voltage .............................1.7 V to 1.9 V UVDDQ supply voltage .....................................3.0 V to 3.6 V DC input voltage to any input ball ..................1.89 V to 3.6 V (Depends on I/O supply voltage. Inputs are not over voltage tolerant.) PVDDQ, GVDDQ, SNVDDQ, SSVDDQ supply voltage ..................................................1.7 V to 3.6 V XVDDQ (Crystal I/O) supply voltage ...............3.0 V to 3.6 V XVDDQ (Ext. clock I/O) supply voltage ...........1.7 V to 1.9 V DC Characteristics Table 3. DC Specifications for All Voltage Supplies Parameter VDD AVDDQ XVDDQ XVDDQ PVDDQ Description Core voltage supply Analog voltage supply Crystal voltage supply Clock voltage supply Processor interface I/O GVDDQ Miscellaneous I/O voltage supply 1.7 1.8, 2.5, 3.3 3.6 V SNVDDQ S-port NAND I/O voltage supply 1.7 1.8, 2.5, 3.3 3.6 V S-port SD I/O voltage supply 1.7 1.8, 2.5, 3.3 3.6 V USB voltage supply 3.0 3.3 3.6 V VDD33 Power sequence control supply 3.0 3.3 3.6 V VIH1 Input HIGH voltage 1 All ports except USB, 2.0 V VCC 3.6 V 0.625 × VCC – VCC + 0.3 V VIH2 Input HIGH voltage 2 All ports except USB, 1.7 V VCC < 2.0 V VCC – 0.4 – VCC + 0.3 VIL Input LOW voltage Output HIGH voltage Output LOW voltage Input leakage current Output leakage current Operating current of core voltage supply (VDD) and analog voltage supply (AVDDQ) –0.3 0.9 × VCC – –1 –1 – – – – – – – – – 0.25 × VCC – 0.1 × VCC 1 1 110 115 SSVDDQ UVDDQ [11, 12]  VOH VOL IIX IOZ ICC Core Conditions IOH(MAX) = –0.1 mA IOL(MIN) = 0.1 mA All I/O signals held at VDDQ All I/O signals held at VDDQ Outputs tri-stated VFBGA WLCSP Min 1.7 1.7 3.0 1.7 1.7 Typ 1.8 1.8 3.3 1.8 1.8, 2.5, 3.3 Max 1.9 1.9 3.6 1.9 3.6 Unit V V V V V V V V A A mA Notes 10. Do not test more than one output at a time. Duration of the short circuit does not exceed 1 second. Tested initially, and after any redesign or process changes, may affect these parameters. 11. Interfaces with a voltage range are adjustable with respect to the I/O voltage and thus support multiple I/O voltages. 12. The SSVDDQ I/O voltage is dynamically changed (for example, from high range to low range) as long as the supply voltage undershoot does not surpass the lower minimum voltage limit. SSVDDQ levels for SD modes: 2.0 V–3.6 V, MMC modes: 1.7 V–3.6 V. 13. When U-port is in a disabled state, UVDDQ goes down to 2.4 V, provided UVDDQ is still the highest supply voltage level. 14. VCC = pertinent VDDQ value. Document Number: 001-07978 Rev. *M Page 12 of 31 CYWB0124AB CYWB0125AB Table 3. DC Specifications for All Voltage Supplies (continued) Parameter ICC Crystal ICC USB ISB1 ISB2 ISB3 Description Operating current of crystal voltage supply (XVDDQ) Conditions XTALOUT floating VFBGA WLCSP Operating current of USB voltage Operating and terminated for high supply (UVDDQ) speed mode Total standby current of Antioch 1. *VDDQ = 3.3 V Nominal (3.0–3.6 V) when device is in suspend mode 2. Outputs and Bidirs High or Floating 3. XTALOUT Floating 4. D+ Floating (no current drawn through internal 1.5 kohm pull-up), D– Grounded, UVALID Driven LOW 5. Device in Suspend Mode 25 °C Total standby current of Antioch 1. *VDDQ = 3.3 V when device is in standby mode Nominal (3.0–3.6 V) 2. Outputs and Bidirs High or Floating 85 °C 3. XTALOUT Floating 4. D+ Floating, D– Grounded, UVALID Driven LOW Total standby current of Antioch 1. Outputs and Bidirs 25 °C when device is in core power High or Floating down mode 2. XTALOUT Floating 85 °C 3. D+ Floating, D– Grounded, UVALID Driven LOW 4. Core Powered Down Min – – – Typ – – – Max 5 N/A 25 Unit mA – 250 2500 A – – 45 A – – 290 – – 25 – – 139 mA A Notes 15. Active Current Conditions: -UVDDQ: USB transmitting 50% of the time, receiving 50% of the time. -PVDDQ/SNVDDQ/SSVDDQ/GVDDQ: Active Current Depends on I/O activity, bus load, and supply level. -XVDDQ: Assume highest frequency clock (48 MHz) or crystal (26 MHz). 16. The Outputs/Bidirs that are forced low in Standby mode increases I/O supply standby current beyond specified value. 17. Isb1 typical value is not a maximum specification but a typical value. Isb1 maximum current value specified for 85 °C. Document Number: 001-07978 Rev. *M Page 13 of 31 CYWB0124AB CYWB0125AB USB Transceiver USB 2.0 compliant in full speed and high speed modes. Capacitance Parameter CIN COUT Description Conditions Typ Max Unit – 9 pF Input ball capacitance, D+/D– – 15 Output ball capacitance – 10 Input ball capacitance, Except D+/D– TA = 25 °C, f = 1 MHz, VCC = VCCIO pF AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms Document Number: 001-07978 Rev. *M Page 14 of 31 CYWB0124AB CYWB0125AB AC Characteristics USB Transceiver USB 2.0 compliant in full speed and high speed modes. P-Port Interface Asynchronous Mode Timing Parameters Table 4. Asynchronous Mode Timing Parameters Parameter Description Min Max Unit Read Timing Parameters tAA Address to data valid – 30 ns tOH Data output hold from address change 3 – ns tEA Chip enable to data valid – 30 ns tAADV ADV# to data valid access time – 30 ns tAVS Address valid to ADV# HIGH 5 – ns tAVH ADV# HIGH to address hold 2 – ns tCVS CE# low setup time to ADV# HIGH 5 – ns 15 – ns tVPH ADV# HIGH time tVP ADV# pulse width LOW 7.5 – ns tOE OE# LOW to data valid – 22.5 ns tOLZ OE# LOW to Low Z 3 – ns tOHZ OE# HIGH to High Z 0 22.5 ns tLZ CE# LOW to Low Z 3 – ns tHZ CE# HIGH to High Z – 22.5 ns Write Timing Parameters tCW CE# LOW to write end 30 – ns tAW Address valid to write end 30 – ns tAS Address setup to write start 0 – ns tADVS ADV# setup to write start 0 – ns tWP WE# pulse width 22 – ns tWPH WE# HIGH time 10 – ns tCPH CE# HIGH time 10 – ns tAVS Address valid to ADV# HIGH 5 – ns tAVH ADV# HIGH to address hold 2 – ns tCVS CE# LOW setup time to ADV# HIGH 5 – ns 15 – ns tVPH ADV# HIGH time tVP ADV# pulse width LOW 7.5 – ns tVS ADV# LOW to end of write 30 – ns tDW Data setup to write end 18 – ns tDH Data hold from write end 0 – ns tWHZ WE# low to DQ High Z output – 22.5 ns tWLZ WE# high to DQ Low Z output 3 – ns Notes 18. In applications where back-to-back accesses are not performed on different endpoint addresses, the minimum tAVH specification is relaxed to 0 ns. 19. In applications where access cycle time is at least 60 ns, tVPH is relaxed to 12 ns. Document Number: 001-07978 Rev. *M Page 15 of 31 CYWB0124AB CYWB0125AB Figure 6. Asynchronous Single Read Timing A Valid Address tAA tVPH tAVS tAVH ADV# tHZ tVP CE# tAADV tEA tOE OE# tOHZ WE# DQ tOLZ High-Z Valid Output tLZ Figure 7. Asynchronous Back-to-Back Read Timing A Valid Address Valid Address tAA tVPH tAVS tAVH tOH ADV# tHZ tVP CE# tAADV tEA OE# tOHZ WE# DQ High-Z Valid Output Valid Output tLZ Document Number: 001-07978 Rev. *M Page 16 of 31 CYWB0124AB CYWB0125AB Figure 8. Asynchronous Back-to-Back Write Timing A Valid Address tAVS tVPH Valid Address tAVH tVP ADV# tVS CE# tCW OE# tAW tWPH tWP WE# tAS tOW tDH tDW tADVS DQ_IN High-Z Valid Input Valid Input tWHZ tLZ DQ_OUT Figure 9. Asynchronous Read to Write Timing A Valid Address ADV# Valid Address tAA tVPH tAVS tAVS tVPH tAVH tVP tVP CE# Valid Address tAVH tVS tAADV tEA tOE OE# tOHZ tAW tWP WE# tAS DQ_IN High-Z DQ_OUT High-Z tDW tDH Valid Input tOLZ tOW Valid Input tWHZ Valid Output tLZ Document Number: 001-07978 Rev. *M Page 17 of 31 CYWB0124AB CYWB0125AB Figure 10. Asynchronous Write to Read Timing A Valid Address tAVS Valid Address tAA tAVH tAVS tVP tAVH ADV# tVP tVS CE# tAADV tOE OE# tAW tWP WE# tAS DQ_IN tDW tDH Valid Input tOLZ tWHZ DQ_OUT Valid Output Synchronous Mode Timing Parameters Table 5. Synchronous Mode Timing Parameters Parameter Description Conditions Min Max Unit FREQ Interface Clock Frequency – 33 MHz tCLK Clock Period 30 – ns tCLKH Clock HIGH Time 12 – ns tCLKL Clock LOW Time 12 – ns tS CE#/WE#/ADDR/DQ Setup Time 7.5 – ns tH CE#/WE#/ADDR/DQ Hold Time 1.5 – ns tCO Clock to Valid Data – 18 ns tOH Clock to Data Hold Time 2 – ns tHZ OE# HIGH to Data High Z – 22.5 ns tLZ OE# LOW to Data Low Z 3 – ns tOE OE# LOW to Data Valid – 22.5 ns tWHZ WE# Low to DQ High Z Output – 22.5 ns tWLZ WE# High to DQ Low Z Output 3 – ns tCKHZ Clock to Data High Z (Figure 14 on page 20) Measured from the rising edge of the second clock after the deassertion of CE# is latched by the rising edge of the clock. – 18 ns tCKLZ Clock to Data Low Z (Figure 16 on page 22) 3 – ns Document Number: 001-07978 Rev. *M Page 18 of 31 CYWB0124AB CYWB0125AB Figure 11. Synchronous Write Timing tCLKH tCLKL tCLK CLK tH tS CE# A[7:0] An+1 An An+2 An+3 WE# OE# DQ[15:0] (input) Dn+1 Dn DQ[15:0] (output) Dn+2 Dn+3 High-Z Note: - Assumes previous cycle had CE# deselected - OE# is don’t care during write operations Figure 12. Synchronous Read Timing tCLKH tCLKL CLK tCLK tH tS CE# A[7:0] An An+1 An+2 An+4 An+3 WE# OE# DQ[15:0] High-Z (input) DQ[15:0] (output) High-Z tCO tHZ tOH Dn tLZ Dn+1 tOE Note: - Assumes previous cycle had CE# deselected Document Number: 001-07978 Rev. *M Page 19 of 31 CYWB0124AB CYWB0125AB Figure 13. Synchronous Read (OE# Fixed LOW) Timing CLK tH tS CE# A[7:0] Ax+1 Ax Ax+2 WE# OE# DQ[15:0] (output) Dx-2 tCKHZ tOH tCO Dx-1 Dx Dx Dx+1 Note: - Assumes previous several cycles were Read Figure 14. Synchronous Read to Write (OE# Controlled) Timing tCLKH tCLKL CLK tCLK tH tS CE# A[7:0] Ax Ax+1 An An+1 tS tH Dn Dn+1 An+2 WE# OE# DQ[15:0] (input) DQ[15:0] (output) High-Z tOH Dx-2 Dx-1 Dn+2 tHZ Dx tCO Note: - Assumes previous several cycles were Read - (Ax) and (Ax+1) cycles are turnaround. (Ax+1) operation does not cross pipeline. Document Number: 001-07978 Rev. *M Page 20 of 31 CYWB0124AB CYWB0125AB Figure 15. Synchronous Read to Write (OE# Fixed LOW) Timing tCLKH tCLKL CLK tCLK tH tS CE# A[7:0] Ax+1 Ax Ax+2 An An+1 WE# tWHZ OE# tS DQ[15:0] (input) DQ[15:0] (output) High-Z tCO Dx-2 tH Dn Dn+1 tOH Dx Dx-1 tCO Note: - Assumes previous several cycles were Read - In this scenario, OE# is held LOW - (Ax) and (Ax+1) cycles are turnaround. (Ax+1) operation does not cross pipeline. - No operation is performed during the Ax+2 cycle (true turnaround operation) Document Number: 001-07978 Rev. *M Page 21 of 31 CYWB0124AB CYWB0125AB Figure 16. Synchronous Write to Read Timing tCLKH tCLKL CLK tCLK tH tS CE# A[7:0] An+1 An An+2 An+4 An+3 WE# tWLZ OE# tH tS Dn DQ[15:0] (input) DQ[15:0] (output) Dn+1 High-Z tCO tOH Dn+2 tCKLZ Note: - Assumes previous cycle has CE# deselected - In this scenario, OE# is held LOW Document Number: 001-07978 Rev. *M Page 22 of 31 CYWB0124AB CYWB0125AB SD/MMC Parameters Figure 17. SD/MMC Timing Waveform - All Modes tSDCLKH tSDCLK SD_CLK tSDCLKL tSDOS tSDCKLZ tSDOH tSDCKHZ SD_CMD/ SD_D0-D3 Output SD_CMD/ SD_D0-D3 Input tSDIS tSDIH Table 6. Common Timing Parameters for SD and MMC – During Identification Mode Parameter Description Min Max Unit SDFREQ SD_CLK interface clock frequency – 400 kHz tSDCLK Clock period 2.5 – s tSDCLKH Clock high time 1.0 – s tSDCLKL Clock low time 1.0 – s Table 7. Common Timing Parameters for SD and MMC – During Data Transfer Mode Parameter Description Min Max Unit 5 48 MHz SDFREQ SD_CLK interface clock frequency tSDCLK Clock period 20.8 200 ns tSDCLKOD Clock duty cycle 40 60 % tSCLKR Clock rise time – 3 ns tSCLKF Clock fall time – 3 ns Min Max Unit Table 8. Timing Parameters for SD – All Modes Parameter Description tSDIS Input setup time 4 – ns tSDIH Input hold time 2.5 – ns tSDOS Output setup time 7 – ns tSDOH Output hold time 6 – ns tSDCKHZ Clock to data high Z – 18 ns tSDCKLZ Clock to data low Z 3 – ns Min Max Unit Table 9. Timing Parameters for MMC – All Modes Parameter Description tSDIS Input setup time 4 – ns tSDIH Input hold time 4 – ns tSDOS Output setup time 6 – ns tSDOH Output hold time 6 – ns tSDCKHZ Clock to data High Z – 18 ns tSDCKLZ Clock to data Low Z 3 – ns Document Number: 001-07978 Rev. *M Page 23 of 31 CYWB0124AB CYWB0125AB Reset and Standby Timing Parameters Figure 18. Reset and Standby Timing Diagram C ore Pow er-D ow n VDD (core) VDDQ (I/O ) XTALIN up & stable before W AKEU P asserted X TA LIN tW PW tW H W AK E U P R E SE TO U T Standby M ode M andatory R eset Pulse R ES E T# tW U H ard R eset Firm w are Init C om plete tR R M andatory R eset Pulse tR H Firm w are Init C om plete F irm w are Init C om plete H igh-Z tR PW U V ALID U SB Sw itch Enabled C Y_AN _M EM _PM U _U PD AT E.U VALID bit is set to ‘0’ tSLP U SB Sw itch D isabled C Y_AN _M EM _PM U _U PD AT E.U VALID bit is set to ‘1’ C Y_AN _ M EM _PM U _U PD ATE .U VALID bit is set to ‘0’ Table 10. Reset and Standby Timing Parameters Parameter Description tSLP Sleep time tWU WAKEUP time from standby mode tWH WAKEUP high time tWPW tRH tRPW RESET# pulse width tRR Conditions Min Max Unit – 1 ms Clock on XTALIN 1 – ms Crystal on XTALIN-XTALOUT 5 – ms 5 – ms WAKEUP pulse width 5 – ms RESET# high time 5 – ms Clock on XTALIN 1 – ms Crystal on XTALIN-XTALOUT 5 – ms 1 – ms RESET# recovery time Document Number: 001-07978 Rev. *M Page 24 of 31 CYWB0124AB CYWB0125AB Ordering Information Table 11 lists the key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 11. Key Features and Ordering Information Ordering Code Turbo-MTP Enabled Package Type Available Clock Input Frequencies (MHz) No 100 VFBGA – Pb-free 19.2, 24, 26, 48 CYWB0124AB-BVXI CYWB0124ABX-FDXI No 81 WLCSP – Pb-free 19.2, 24, 26, 48 CYWB0125ABX-FDXI Yes 81 WLCSP – Pb-free 19.2, 24, 26, 48 Ordering Code Definitions CY WB 012 4, 5 AB X BV, FD X I Temperature: Industrial Pb-free BV = VFBGA, FD = WLCSP BGA, CSP A generation Turbo MTP is enabled 4 = No, 5 = Yes Antioch Bridge Family: West Bridge Company ID: CY = Cypress Document Number: 001-07978 Rev. *M Page 25 of 31 CYWB0124AB CYWB0125AB Package Diagrams Figure 19. 100 VFBGA (6 × 6 × 1.0 mm) BZ100A 51-85209 *D Figure 20. 81 WLCSP (3.784 × 3.788 × 0.55 mm) 001-13820 *F Document Number: 001-07978 Rev. *M Page 26 of 31 CYWB0124AB CYWB0125AB Acronyms Document Conventions Table 12. Acronyms Used in this Document Units of Measure Acronym Description Table 13. Units of Measure DC Direct Current DMA Direct Memory Access A ampere ESD Electrostatic Discharge dBc decibels relative to the carrier ECC Error Correction Codes kHz kilohertz HDD Hard Disk Drive MBPs megabyte per second MTP Media Transfer Protocol MHz megahertz MMC Multimedia Card µA microampere PLL Phase-Locked Loop µs microsecond SLIM Simultaneous Link to Independent Media ms millisecond SLC Single Level Cell ns nanosecond USB Universal Serial Bus ppm parts per million WLCSP Wafer Level Chip Scale Package pF picofarad CE-ATA Consumer Electronics - Advanced Technology Attachment V volt mA milliampere Document Number: 001-07978 Rev. *M Symbol Unit of Measure Page 27 of 31 CYWB0124AB CYWB0125AB Document History Page Document Title: CYWB0124AB/CYWB0125AB, West Bridge® Antioch™ USB/Mass Storage Peripheral Controller Document Number: 001-07978 Revision ECN Orig. of Change Submission Date ** 460480 ODC See ECN New release *A 539922 VSO See ECN Removed all CYWB0224AB (this is Astoria P/N) Removed CYWB0224AB Additional Features Removed MLC NAND support wordings Removed CE-ATA specification Added 26 MHz for the clock support Removed the paragraph of CYWB0224AB Removed Note 1 Corrected Note 7 is the same as PDD Added Astoria as a future product in Note 9 Added reference figures in tCKHZ and tCKLZ Added condition description to tCKHZ Added figure 11 Updated figure 14 Removed CYWB0224AB-BVXI, removed the columns of CE-ATA and MLC NAND Support *B 567593 VSO See ECN Minor Change: Post part CYWB0124AB on external website under NDA. *C 841760 RUY See ECN Page-1, Changes to the Mass Storage Support with addition of CE-ATA Updated the Revision numbers of SD Card Specifications Added CE-ATA Specifications Clarified footnote 5 that unused inputs are tied through 10k pull up resistors and that CLK is LOW in asynchronous P-port operation Footnote 6, 100k resistor is changed to 10k Footnote 7, a sentence on resistors for speed capability on USB is added SDIO is changed to SD in Pin Assignment Table In Clocking, changed crystal requirement from 50 to 100 ppm. Clarified Core Power Down mode that AVDDQ is also powered down. Split tAS into tAS and tADVS and tWPH into tWPH and tCPH in Table 5 Updated Figure 5 to depict tOH Updated Figure 6 to depict tADVS and corrected tCW Updated Figure 1 to remove “Access Control” Added external clock requirements and Table 1 Added section on Flexible I/Os Specified values in Absolute Maximum Ratings (changed from TBS) In Table 3, updated VIH value for supplies other than UVDDQ, and added pertinent notes 15 and 16. Appended to note 12 that maximum current values are measured at 85°C. Added maximum current values for ISB1, ISB2 and ISB3 In Table 5, the following changes are made: tOH, tOLZ, tLZ, and tOW changed from 5 to 3 ns; tVP changed from 5 to 7.5 ns; tOE, tOHZ, tHZ, and tWHZ changed from 20 to 22.5 ns. Added notes  and  In Table 6, tHZ and tOE changed form 18 to 22.5 ns. Document Number: 001-07978 Rev. *M Description of Change Page 28 of 31 CYWB0124AB CYWB0125AB Document History Page (continued) Document Title: CYWB0124AB/CYWB0125AB, West Bridge® Antioch™ USB/Mass Storage Peripheral Controller Document Number: 001-07978 Revision ECN Orig. of Change Submission Date Description of Change *D 1067820 RUY See ECN Added Table 10 Added “SSVDDQ levels for SD modes: 2.0V - 3.6V, MMC modes:1.7V - 3.6V.” to note 11 in Table 5 Added notation of tSDCKHZ and tSDCKLZ to Figure 15 Added undershoot and overshoot parameters and removed the Supply Voltage Noise requirement in Table 1 External Clock Requirements Added representation of tWHZ to Figure 13 and tWLZ to Figure 14 Added tWHZ and tWLZ to Table 5 Changed name of parameter tOW to tWLZ in Table 6 Added “and less than 4x4 mm WLCSP” to Features Added Figure 19 Added WLCSP ordering information Added functionality of Antioch in WLCSP Added Figure 3 Added two columns to Table 1 showing the Balls are available in the WLCSP and VFBGA packages Added “Note that in the WLCSP option, the S-port is not configurable; it only supports a single SD/MMC+ port with no NAND port.” to Mass Storage Support section Added “Availability of specific signals on the WLCSP option is detailed in Pin Assignments.” to Antioch in WLCSP. Added “Maximum permitted noise on AVDDQ is 20 mV p-p.” and “Noise guideline for all supplies except AVDDQ is maximum 100 mV p-p.” to Antioch Power Domains section Changed maximum value of Isb3 in Table 3 from 170 uA to 139 uA. Changed “Typical” values for Isb2 and Isb3 to correct definition of “Maximum” value at 25°C. Isb1 has typical value at 25°C. Removed “These values are based upon simulation and are subject to change pending closure of full device characterization.” from note 10 Added figure 16 and Table 11 Changed reference from “pin” to “Ball” in Table 2 and throughout the data sheet. Corrected the ball description of SD_WP in Table 2 to say that SD_WP being HIGH, not LOW indicates that the card is write protected Added the requirement that XTALIN is LOW before entry into Core Power Down mode in Core Power Down mode and Antioch in WLCSP sections Re-ordered paragraphs in Clocking section Added “The external clock is a square wave that conforms to high and low voltage levels mentioned in Table 3 and the rise and fall time specifications” in Figure 17 Clarified Standby mode section to reflect that WAKEUP assertion releases Antioch from standby mode only when the mode is entered by de-asserting WAKEUP *E 1116363 RUY See ECN Changed part number for the WLCSP part from CYWB0124AB-FDXI to CYWB0124ABX-FDXI in Ordering Information table Updated the information from *B version of specification 001-13820 in the package diagram of WLCSP Removed mention of erroneous change in Isb1 parameter in *D version from Document History Table *F 1408263 AESA See ECN Changed the DC Characteristics to differentiate between Icc Crystal for Antioch VFBGA and WLCSP Added a footnote to NAND_CE#, NAND_CE2#, NAND_WP#, NAND_CLE, and NAND_ALE pins in the pin assignment table. Document Number: 001-07978 Rev. *M Page 29 of 31 CYWB0124AB CYWB0125AB Document History Page (continued) Document Title: CYWB0124AB/CYWB0125AB, West Bridge® Antioch™ USB/Mass Storage Peripheral Controller Document Number: 001-07978 Revision ECN Orig. of Change Submission Date Description of Change *G 1489983 OSG / AESA See ECN In DC Characteristics Table, changed Icc Crystal and Icc Core to differentiate between values for VFBGA and WLCSP In DC Characteristics Table, clarified the ISB1 measurement conditions. *H 2572476 OSG / AESA 09/25/2008 *I 2949425 ODC 10/22/10 Template and Styles update. Added ordering code definitions. Added Acronym table and units of measure. Included table of contents. Updated package diagrams. *J 3201726 AESA 03/21/11 Removed Pruned part CYWB0125AB-BVXI from ordering information. Updated Figure 19 on page 26 *K 3553527 AASI 03/16/2012 Post the datasheet to Cypress.com. *L 3847849 HBM 12/20/2012 Updated Package Diagrams: spec 001-13820 – Changed revision from *E to *F. *M 4197479 HBM 11/20/2013 Updated in new template. Updated Phase Noise specifications for input clock - Table 1 Updated ppm specification to 150 ppm for input clock and crystal - Table 1 Added Turbo-MTP Support introduction to Functional Overview Added Turbo-MTP part numbers to Ordering Information Added part number CYWB0125AB Changed data sheet title to “CYWB0124AB/CYWB0125AB West Bridge® Antioch™ USB/Mass Storage Peripheral Controller” Updated data sheet template Completing Sunset Review. Document Number: 001-07978 Rev. *M Page 30 of 31 CYWB0124AB CYWB0125AB Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/plc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/psoc Technical Support cypress.com/go/support cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2005-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-07978 Rev. *M Revised November 20, 2013 Page 31 of 31 West Bridge is a registered trademark of Cypress Semiconductor Corp. SLIM and Antioch are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners.