CY7C02732 K / 64 K × 16 Dual-Port Static RAM CY7C027 CY7C028 32 K / 64 K × 16 Dual-Port Static RAM 32 K / 64 K × 16 Dual-Port Static RAM Features Expandable data bus to 32 bits or more using Master/Slave chip select when using more than one device ■ On-chip arbitration logic ■ Semaphores included to permit software handshaking between ports ■ INT flags for port-to-port communication ■ Separate upper-byte and lower-byte control ■ Dual chip enables ■ Pin select for Master or Slave ■ Commercial and industrial temperature ranges ■ Available in 100-pin TQFP ■ Pb-free packages available For a complete list of related documentation, click here. ■ True dual-ported memory cells which allow simultaneous access of the same memory location ■ 32 K × 16 organization (CY7C027) ■ 64 K × 16 organization (CY7C028) ■ 0.35 micron CMOS for optimum speed and power ■ High speed access: 15 and 20 ns ■ Low operating power ■ Active: ICC = 180 mA (typical) ■ Standby: ISB3 = 0.05 mA (typical) ■ Fully asynchronous operation ■ Automatic power down ■ Logic Block Diagram R/WL UBL R/WR UBR CE0L CE1L CE0R CE1R CEL CER LBL LBR OEL OER [1] I/O8L–I/O15L [2] 8 8 8 I/O Control I/O0L–I/O7L [3] A0L–A14/15L [3] 15/16 Address Decode 8 I/O Control 15/16 [2] I/O0L–I/O7R Address Decode True Dual-Ported RAM Array [1] I/O8L–I/O15R 15/16 [3] A0R–A14/15R 15/16 A0L–A14/15L CEL OEL R/WL SEML [3] A0R–A14/15R CER OER R/WR SEMR Interrupt Semaphore Arbitration [4] BUSYL[4] INTL UBL LBL M/S BUSYR INTR UBR LBR Notes 1. I/O8–I/O15 for × 16 devices 2. I/O0–I/O7 for × 16 devices 3. A0–A14 for 32K; A0–A15 for 64K devices. 4. BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation Document Number: 38-06042 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 26, 2014 CY7C027 CY7C028 Functional Description The CY7C027 and CY7C028 are low power CMOS 32 K, 64 K × 16 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16-bit dual-port static RAMs or multiple devices can be combined to function as a 32-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor and multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Document Number: 38-06042 Rev. *K Each port has independent control pins: dual chip enables (CE0 and CE1), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by the chip enable pins. The CY7C027 and CY7C028 are available in 100-pin Thin Quad Flat pack (TQFP) packages. Page 2 of 23 CY7C027 CY7C028 Contents Pin Configurations ........................................................... 4 Selection Guide ................................................................ 5 Pin Definitions .................................................................. 5 Maximum Ratings ............................................................. 6 Operating Range ............................................................... 6 Electrical Characteristics ................................................. 6 Capacitance ...................................................................... 7 AC Test Loads and Waveforms ....................................... 7 Data Retention Mode ........................................................ 7 Timing ................................................................................ 7 Switching Characteristics ................................................ 8 Switching Waveforms .................................................... 10 Architecture .................................................................... 16 Functional Description ................................................... 16 Write Operation ......................................................... 16 Read Operation ......................................................... 16 Interrupts ................................................................... 16 Busy .......................................................................... 16 Document Number: 38-06042 Rev. *K Master/Slave ............................................................. 16 Semaphore Operation ............................................... 16 Ordering Information ...................................................... 19 32 K × 16 Asynchronous Dual-Port SRAM ............... 19 64 K × 16 Asynchronous Dual-Port SRAM ............... 19 Ordering Code Definitions ......................................... 19 Package Diagram ............................................................ 20 Acronyms ........................................................................ 21 Document Conventions ................................................. 21 Units of Measure ....................................................... 21 Document History Page ................................................. 22 Sales, Solutions, and Legal Information ...................... 23 Worldwide Sales and Design Support ....................... 23 Products .................................................................... 23 PSoC® Solutions ...................................................... 23 Cypress Developer Community ................................. 23 Technical Support ..................................................... 23 Page 3 of 23 CY7C027 CY7C028 Pin Configurations A8R A7R A6R A5R A4R A3R A2R A1R A0R INTR BUSYR M/S GND BUSYL INTL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L Figure 1. 100-pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A9R A10L 2 74 A10R A11L 3 73 A11R A12L 4 72 A12R A13L 5 71 A13R A14L 6 70 A14R [5] A15L 7 69 A15R [5] NC 8 68 NC NC 9 67 NC LBL 10 66 LBR UBL 11 65 UBR CE0L 12 64 CE0R CE1L 13 63 CE1R SEML 14 62 SEMR VCC 15 61 GND R/WL 16 60 R/WR OEL 17 59 OER GND 18 58 GND GND 19 57 GND I/O15L 20 56 I/O15R I/O14L 21 55 I/O14R I/O13L 22 54 I/O13R I/O12L 23 53 I/O12R I/O11L 24 52 I/O11R I/O10L 25 51 I/O10R CY7C028 (64 K × 16) CY7C027 (32 K × 16) NC I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R I/O3R I/O2R I/01R I/O0R GND I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note 5. This pin is NC for CY7C027. Document Number: 38-06042 Rev. *K Page 4 of 23 CY7C027 CY7C028 Selection Guide CY7C027/CY7C028 -15 Parameter CY7C027/CY7C028 -20 Unit Maximum Access Time 15 20 ns Typical Operating Current 190 180 mA Typical Standby Current for ISB1 (Both ports TTL level) Typical Standby Current for ISB3 (Both ports CMOS level) 50 45 mA 0.05 0.05 mA Pin Definitions Left Port Right Port Description CE0L, CE1L CE0R, CE1R Chip Enable (CE is LOW when CE0 VIL and CE1 VIH) R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A15L A0R–A15R Address (A0–A14 for 32K; A0–A15 for 64K devices) I/O0L–I/O15L I/O0R–I/O15R Data Bus Input/Output (I/O0–I/O15 for × 16 devices) SEML SEMR Semaphore Enable UBL UBR Upper Byte Select (I/O8–I/O15 for × 16 devices) LBL LBR Lower Byte Select (I/O0–I/O7 for × 16 devices) INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground NC No Connect Document Number: 38-06042 Rev. *K Page 5 of 23 CY7C027 CY7C028 Input Voltage [7] ...........................................–0.5 V to +7.0 V Maximum Ratings Exceeding maximum ratings [6] may shorten the useful life of the device. User guidelines are not tested. Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage .......................................... > 1100V Storage Temperature ............................... –65 °C to +150 °C Latch-Up Current ................................................... > 200 mA Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Operating Range Supply Voltage to Ground Potential .............–0.3 V to +7.0 V DC Voltage Applied to Outputs in High Z State ...................................... –0.5 V to +7.0 V DC Range Ambient Temperature 0 °C to +70 °C 5 V 10% –40 °C to +85 °C 5 V 10% Commercial Industrial VCC Electrical Characteristics Over the Operating Range CY7C027/CY7C028 Symbol Parameter -15 Min Typ – VOH Output HIGH Voltage (VCC = Min, IOH = –4.0 mA) 2.4 VOL Output LOW Voltage (VCC = Min, IOH = +4.0 mA) – -20 Max Min Typ – – 2.4 0.4 – Unit Max – V 0.4 V VIH Input HIGH Voltage 2.2 – 2.2 – V VIL Input LOW Voltage – 0.8 – 0.8 V IOZ Output Leakage Current 10 –10 ICC Operating Current (VCC = Max, IOUT= 0 mA) Outputs Disabled Commercial 280 – Standby Current (Both Ports TTL Level) CEL & CER VIH, f = fMAX Commercial Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Commercial Standby Current (Both Ports CMOS Level) CEL & CER VCC – 0.2 V, f = 0 Commercial Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX[8] Commercial ISB1 ISB2 ISB3 ISB4 –10 – 190 Industrial – 50 Industrial 120 Industrial 180 – 0.05 Industrial Industrial 70 – 0.5 – 110 160 – 10 A 180 265 mA 305 290 mA 45 65 mA 60 80 mA 110 160 mA 125 175 mA 0.05 0.5 mA 0.05 0.5 mA 100 140 mA 115 155 mA Notes 6. The voltage on any input or I/O pin cannot exceed the power pin during power up. 7. Pulse width < 20 ns. 8. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. Document Number: 38-06042 Rev. *K Page 6 of 23 CY7C027 CY7C028 Capacitance Parameter [9] Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Max Unit 10 pF 10 pF AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 5V 5V R1 = 893 C = 30 pF RTH = 250 OUTPUT OUTPUT R1 = 893 OUTPUT C = 30 pF R2 = 347 C = 5 pF R2 = 347 VTH = 1.4 V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0 V GND 10% 90% 10% 90% 3 ns 3 ns Data Retention Mode The CY7C027 and CY7C028 are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2 V. 2. CE must be kept between VCC – 0.2 V and 70% of VCC during the power up and power down transitions. 3. The RAM can begin operation > tRC after VCC reaches the minimum operating voltage (4.5 V). Timing Figure 3. Timing Data Retention Mode VCC CE Parameter ICCDR1 4.5 V VCC 2.0 V 4.5 V VCC to VCC – 0.2 V Test Conditions [10] At VCCDR = 2 V tRC V IH Max Unit 1.5 mA Notes 9. Tested initially and after any design or process changes that may affect these parameters. 10. CE = VCC, VIN = GND to VCC, TA = 25 °C. This parameter is guaranteed but not tested. Document Number: 38-06042 Rev. *K Page 7 of 23 CY7C027 CY7C028 Switching Characteristics Over the Operating Range CY7C027/CY7C028 Parameter [11] Description -15 Min -20 Max Min Unit Max Read Cycle tRC Read Cycle Time 15 – 20 – ns tAA Address to Data Valid – 15 – 20 ns tOHA Output Hold From Address Change 3 – 3 – ns tACE[12] CE LOW to Data Valid – 15 – 20 ns tDOE OE LOW to Data Valid – 10 – 12 ns OE LOW to Low Z 3 – 3 – ns OE HIGH to High Z – 10 – 12 ns CE LOW to Low Z 3 – 3 – ns CE HIGH to High Z – 10 – 12 ns CE LOW to Power Up 0 – 0 – ns CE HIGH to Power Down – 15 – 20 ns Byte Enable Access Time – 15 – 20 ns Write Cycle Time 15 – 20 – ns tLZOE[13, 14, 15] tHZOE[13, 14, 15] tLZCE[13, 14, 15] tHZCE[13, 14, 15] tPU[15] tPD[15] tABE[12] Write Cycle tWC tSCE[12] CE LOW to Write End 12 – 15 – ns tAW Address Valid to Write End 12 – 15 – ns tHA Address Hold From Write End 0 – 0 – ns tSA[12] Address Setup to Write Start 0 – 0 – ns tPWE Write Pulse Width 12 – 15 – ns tSD Data Setup to Write End 10 – 15 – ns tHD Data Hold From Write End 0 – 0 – ns R/W LOW to High Z – 10 – 12 ns R/W HIGH to Low Z 3 – 3 – ns Write Pulse to Data Delay – 30 – 45 ns Write Data Valid to Read Data Valid – 25 – 30 ns – 15 – 20 ns tHZWE[14, 15] tLZWE[14, 15] tWDD[16] tDDD[16] Busy Timing [17] tBLA BUSY LOW from Address Match tBHA BUSY HIGH from Address Mismatch – 15 – 20 ns tBLC BUSY LOW from CE LOW – 15 – 20 ns tBHC BUSY HIGH from CE HIGH – 15 – 17 ns tPS Port Setup for Priority 5 – 5 – ns Notes 11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH and 30 pF load capacitance. 12. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 14. Test conditions used are Load 2. 15. This parameter is guaranteed by design, but it is not production tested. 16. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 on page 13. 17. Test conditions used are Load 1. Document Number: 38-06042 Rev. *K Page 8 of 23 CY7C027 CY7C028 Switching Characteristics (continued) Over the Operating Range CY7C027/CY7C028 Parameter [11] Description -15 -20 Min Max Unit Min Max tWB R/W HIGH after BUSY (Slave) 0 – 0 – ns tWH R/W HIGH after BUSY HIGH (Slave) 13 – 15 – ns tBDD[18] BUSY HIGH to Data Valid – 15 – 20 ns tINS INT Set Time – 15 – 20 ns tINR INT Reset Time – 15 – 20 ns INTERRUPT TIMING[19] SEMAPHORE TIMING tSOP SEM Flag Update Pulse (OE or SEM) 10 – 10 – ns tSWRD SEM Flag Write to Read Time 5 – 5 – ns tSPS SEM Flag Contention Window 5 – 5 – ns tSAA SEM Address Access Time – 15 – 20 ns Notes 18. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). 19. Test conditions used are Load 1. Document Number: 38-06042 Rev. *K Page 9 of 23 CY7C027 CY7C028 Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access) [20, 21, 22] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [20, 23, 24] tACE CE and LB or UB tDOE OE tHZCE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Figure 6. Read Cycle No. 3 (Either Port) [20, 22, 23, 24] tRC ADDRESS tAA tOHA UB or LB tHZCE tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes 20. R/W is HIGH for read cycles. 21. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 22. OE = VIL. 23. Address valid prior to or coincident with CE transition LOW. 24. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. Document Number: 38-06042 Rev. *K Page 10 of 23 CY7C027 CY7C028 Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (R/W Controlled Timing) [25, 26, 27, 28] tWC ADDRESS tHZOE [31] OE tAW CE [29, 30] tPWE[28] tSA tHA R/W tHZWE[31] DATA OUT tLZWE NOTE 32 NOTE 32 tSD tHD DATA IN Figure 8. Write Cycle No. 2 (CE Controlled Timing) [25, 26, 27, 32, 33] tWC ADDRESS tAW CE [29, 30] tSA tSCE tHA R/W tSD tHD DATA IN Notes 25. R/W must be HIGH during all address transitions. 26. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 27. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 28. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 29. To access RAM, CE = VIL, SEM = VIH. 30. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 31. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested. 32. During this period, the I/O pins are in the output state, and input signals must not be applied. 33. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document Number: 38-06042 Rev. *K Page 11 of 23 CY7C027 CY7C028 Switching Waveforms (continued) Figure 9. Semaphore Read After Write Timing, Either Side [34] tOHA tSAA A 0–A 2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tSCE tSOP tSD I/O0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Figure 10. Timing Diagram of Semaphore Contention [35, 36, 37] A0L –A2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes 34. CE = HIGH for the duration of the above timing (both write and read cycle). 35. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 36. Semaphores are reset (available to both ports) at cycle start. 37. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable. Document Number: 38-06042 Rev. *K Page 12 of 23 CY7C027 CY7C028 Switching Waveforms (continued) Figure 11. Timing Diagram of Read with BUSY (M/S = HIGH) [38] tWC ADDRESSR MATCH tPWE R/WR tSD DATA INR tHD VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD Figure 12. Write Timing with Busy Input (M/S = LOW) tPWE R/W BUSY tWB tWH Note 38. CEL = CER = LOW. Document Number: 38-06042 Rev. *K Page 13 of 23 CY7C027 CY7C028 Switching Waveforms (continued) Figure 13. Busy Timing Diagram No.1 (CE Arbitration) [39] CELValid First: ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CE L tBLC tBHC BUSY L Figure 14. Busy Timing Diagram No. 2 (Address Arbitration) [39] Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSY R Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSY L Note 39. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted. Document Number: 38-06042 Rev. *K Page 14 of 23 CY7C027 CY7C028 Switching Waveforms (continued) Figure 15. Interrupt Timing Diagrams Left Side Sets INTR: ADDRESSL tWC WRITE 7FFF (FFFF for CY7C028) tHA[40] CE L R/W L INT R tINS [41] Right Side Clears INTR: tRC READ 7FFF (FFFF for CY7C028) ADDRESSR CE R tINR [41] R/WR OE R INTR Right Side Sets INT L: tWC ADDRESSR WRITE 7FFE (FFFE for CY7C028) tHA[40] CE R R/W R INT L [41] tINS Left Side Clears INTL: tRC READ 7FFE (FFFE for CY7C028) ADDRESSR CE L tINR[41] R/W L OE L INT L Notes 40. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 41. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. Document Number: 38-06042 Rev. *K Page 15 of 23 CY7C027 CY7C028 Architecture Busy The CY7C027 and CY7C028 consist of an array of 32K and 64K words of 16 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be used for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. The CY7C027 and CY7C028 provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic determines which port has access. If tPS is violated, one port definitely gains permission to the location, but it is not predictable which port gets that permission. BUSY is asserted tBLA after an address match or tBLC after CE is taken LOW. Functional Description Write Operation Data must be set up for a duration of tSD before the rising edge of R/W to guarantee a valid write. A write operation is controlled by either the R/W pin (see Figure 7 on page 11) or the CE pin (see Figure 8 on page 11). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (7FFF for the CY7C027, FFFF for the CY7C028) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027, FFFE for the CY7C028) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. The operation of the interrupts and their interaction with Busy is summarized in Table 2. Master/Slave A M/S pin is provided to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This allows the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C027 and CY7C028 provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all sixteen/eighteen data lines output the semaphore value. The read value is latched in an Document Number: 38-06042 Rev. *K Page 16 of 23 CY7C027 CY7C028 output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. Table 1. Non-Contending Read/Write Inputs Outputs CE R/W OE UB LB SEM I/O8–I/O15 I/O0–I/O7 Operation H X X X X H High Z High Z Deselected: Power Down X X X H H H High Z High Z Deselected: Power Down L L X L H H Data In High Z Write to Upper Byte Only L L X H L H High Z Data In Write to Lower Byte Only L L X L L H Data In Data In Write to Both Bytes L H L L H H Data Out High Z Read Upper Byte Only L H L H L H High Z Data Out Read Lower Byte Only L H L L L H Data Out Data Out Read Both Bytes X X H X X X High Z High Z Outputs Disabled H H L X X L Data Out Data Out Read Data in Semaphore Flag X H L H H L Data Out Data Out Read Data in Semaphore Flag H X X X L Data In Data In Write DIN0 into Semaphore Flag X X H H L Data In Data In Write DIN0 into Semaphore Flag L X X L X L Not Allowed L X X X L L Not Allowed Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH) [42] Left Port Function Right Port R/WL CEL OEL A0L–14L INTL R/WR CER OER A0R–14R INTR Set Right INTR Flag L L X 7FFF X X X X X L [43] Reset Right INTR Flag X X X X X X L L 7FFF H [44] X L [44] L L X 7FFE X H [43] X X X X X Set Left INTL Flag Reset Left INTL Flag X X X L X L 7FFE Notes 42. A0L–15L and A0R–15R, FFFF/FFFE for the CY7C028. 43. If BUSYL = L, then no change. 44. If BUSYR = L, then no change. Document Number: 38-06042 Rev. *K Page 17 of 23 CY7C027 CY7C028 Table 3. Semaphore Operation Example Function I/O0–I/O15Left I/O0–I/O15Right 1 1 No action Status Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Document Number: 38-06042 Rev. *K Page 18 of 23 CY7C027 CY7C028 Ordering Information 32 K × 16 Asynchronous Dual-Port SRAM Speed (ns) 20 Package Name Ordering Code Package Type Operating Range CY7C027-20AXC A100 100-pin TQFP (Pb-free) Commercial CY7C027-20AXI A100 100-pin TQFP (Pb-free) Industrial CY7C027-20AXIT A100 100-pin TQFP (Pb-free) Industrial 64 K × 16 Asynchronous Dual-Port SRAM Speed (ns) 15 Package Name Ordering Code CY7C028-15AXC A100 Package Type 100-pin TQFP (Pb-free) Operating Range Commercial CY7C028-15AI A100 100-pin TQFP Industrial CY7C028-15AXI A100 100-pin TQFP (Pb-free) Industrial Ordering Code Definitions CY 7 C 02 X - XX X X X X X = blank or T blank = Tube; T = Tape and Reel Temperature Range: X = C or I C = Commercial; I = Industrial X = Pb-free (RoHS Compliant) Package Type: A = 100-pin TQFP Speed Grade: 20 ns or 15 ns Depth: X = 7 or 8 7 = 32K; 8 = 64K Width: 02 = × 16 Technology Code: C = CMOS Marketing Code: 7 = Dual Port SRAM Company ID: CY = Cypress Document Number: 38-06042 Rev. *K Page 19 of 23 CY7C027 CY7C028 Package Diagram Figure 16. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048 51-85048 *I Document Number: 38-06042 Rev. *K Page 20 of 23 CY7C027 CY7C028 Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static Random Access Memory mA milliampere TQFP Thin Quad Flat Pack mm millimeter TTL Transistor-Transistor Logic ns nanosecond ohm % percent pF picofarad V volt Document Number: 38-06042 Rev. *K Symbol Unit of Measure Page 21 of 23 CY7C027 CY7C028 Document History Page Document Title: CY7C027/CY7C028, 32 K / 64 K × 16 Dual-Port Static RAM Document Number: 38-06042 Rev. ECN No. Orig. of Change Submission Date ** 110190 SZV 09/29/01 Change from Spec number: 38-00666 to 38-06042 *A 122292 RBI 12/27/02 Updated Maximum Ratings (Added Power up requirements). *B 236765 YDT 6/23/04 Updated Features (Removed cross information from this section). *C 377454 PCX See ECN Updated Ordering Information (Added Pb-free Logo, added Pb-free parts to ordering information namely CY7C027-20AXC, CY7C028-12AXC, CY7C028-15AXC, CY7C028-15AI, CY7C028-15AXI). *D 2623540 VKN / PYRS 12/17/08 Updated Ordering Information (Added CY7C027-15AXI in the Ordering information table). *E 2897217 RAME 03/22/2010 Updated Ordering Information (Updated part numbers). Updated Package Diagram. *F 3111417 ADMU 12/15/2010 Added Ordering Code Definitions. *G 3352028 ADMU 08/23/2011 Updated Features (Removed CY7C037/CY7C038 information and also removed -12 speed bin information). Updated Functional Description (Removed CY7C037/CY7C038 information). Updated Pin Configurations (Removed CY7C037/CY7C038 information). Updated Selection Guide (Removed CY7C037/CY7C038 information and also removed -12 speed bin information). Updated Electrical Characteristics (Removed CY7C037/CY7C038 information and also removed -12 speed bin information). Updated AC Test Loads and Waveforms (Removed -12 speed bin information). Updated Switching Characteristics (Removed CY7C037/CY7C038 information and also removed -12 speed bin information). Updated Package Diagram. Added Acronyms and Units of Measure. Updated in new template. *H 3721632 ADMU 08/23/2012 Updated Operating Range (Removed the Note “Industrial parts are available in CY7C028 only.” and its reference). Updated Electrical Characteristics (Removed the Note “Industrial parts are available in CY7C028 only.” and its reference). Updated Ordering Information (Updated part numbers). Updated Package Diagram (spec 51-85048 (Changed revision from *E to *G)). Description of Change *I 3846315 SMCH 12/19/2012 Updated Ordering Information (Updated part numbers). *J 4106180 SMCH 08/28/2013 Updated Pin Configurations: Updated Figure 1 (Removed overline on “R” in “CE1R” in pin 63). Updated Package Diagram: spec 51-85048 – Changed revision from *G to *H. Updated in new template. Completing Sunset Review. *K 4580622 SMCH 11/26/2014 Added related documentation hyperlink in page 1. Updated Figure 16 in Package Diagram (spec 51-85048 *H to *I). Document Number: 38-06042 Rev. *K Page 22 of 23 CY7C027 CY7C028 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06042 Rev. *K Revised November 26, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 23 of 23