ATMEL ATA5824-PLQW

Features
• Full-duplex Operation Mode without Duplex Frequency Offset to Prevent the Relay
Attack against Passive Entry Go (PEG) Systems
• High FSK Sensitivity: –105.5 dBm at 20 kBaud/–109 dBm at 2.4 kBaud (433.92 MHz)
• High ASK Sensitivity: –111.5 dBm at 10 kBaud/–116 dBm at 2.4 kBaud (100% ASK,
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Carrier Level 433.92 MHz)
Low Supply Current: 10.5 mA in RX and TX Mode (3V/TX with 5 dBm/433.92 MHz)
Data Rate 1 to 20 kBaud Manchester FSK, 1 to 10 kBaud Manchester
ASK
ASK/FSK Receiver Uses a Low IF Architecture with High Selectivity,
Blocking and Low Intermodulation (Typical 3 dB Blocking
55.5 dBC at ±750 kHz/60.5 dBC at ±1.5 MHz and 67 dBC at ±10 MHz,
System I1dBCP = –30 dBm/System IIP3 = –20 dBm)
Wide Bandwidth AGC to Handle Large Outband Blockers above the System I1dBCP
226 kHz IF (Intermediate Frequency) with 30 dB Image Rejection and 220 kHz System
Bandwidth to Support TPM Transmitters using ATA5756/ATA5757 Transmitters with
Standard Crystals
Transmitter Uses Closed Loop FSK Modulation with Fractional-N Synthesizer with
High PLL Bandwidth and an Excellent Isolation between PLL and PA
Tolerances of XTAL Compensated by Fractional-N Synthesizer with 800 Hz RF
Resolution
Integrated RX/TX-Switch, Single-ended RF Input and Output
RSSI (Received Signal Strength Indicator)
Communication to Microcontroller with SPI Interface Working at 500 kBit/s Maximum
Configurable Self Polling and RX/TX Protocol Handling with FIFO-RAM Buffering of
Received and Transmitted Data
1 Push Button Input and 1 Wake-up Input are Active in Power-down Mode
Integrated XTAL Capacitors
PA Efficiency: up to 38% (433.92 MHz/10 dBm/3V)
Low In-band Sensitivity Change of Typically ±2.0 dB within ±75 kHz Center Frequency
Change in the Complete Temperature and Supply Voltage Range
Fully Integrated PLL with Low Phase Noise VCO, PLL Loop Filter and full support of
multi-channel operation with arbitrary Channel distance due to Fractional-N
Synthesizer
Sophisticated Threshold Control and Quasi-peak Detector Circuit in the Data Slicer
433.92 MHz, 868.3 MHz and 315 MHz without External VCO and PLL Components
Efficient XTO Start-up Circuit (> –1.5 kΩ Worst Case Start Impedance)
Changing of Modulation Type ASK/FSK and Data Rate without Component Changes to
Allow Different Modulation Schemes in TPM and RKE
Minimal External Circuitry Requirements for Complete System Solution
Adjustable Output Power: 0 to 10 dBm Adjusted and Stabilized with External Resistor,
Programmable Output Power with 0.5dB Steps with Internal Resistor
Clock and Interrupt Generation for Microcontroller
ESD Protection at all Pins (±2.5 kV HBM, ±200V MM, ±500V FCDM)
Supply Voltage Range: 2.15V to 3.6V or 4.4V to 5.25V
Typical Power-down Current < 10 nA
Temperature Range: –40°C to +105°C
Small 7 mm × 7 mm QFN48 Package
UHF ASK/FSK
Transceiver
ATA5823
ATA5824
Rev. 4829C–RKE–09/05
Applications
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Automotive Keyless Entry and Passive Entry Go (Handsfree Car Access)
Tire Pressure Monitoring Systems
Remote Control Systems
Alarm and Telemetering Systems
Energy Metering
Home Automation
Benefits
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No SAW Device Needed in Key Fob Designs to Meet Automotive Specifications
Low System Cost Due to Very High System Integration Level
Only One Crystal Needed in System
Less Demanding Specification for the Microcontroller Due to Handling of Power-down Mode,
Delivering of Clock and Complete Handling of Receive/Transmit Protocol and Polling
• Single-ended Design with High Isolation of PLL/VCO from PA and the Power Supply Allows a
Loop Antenna in the Key Fob to Surround the Whole Application
• Prevention against Relay Attack with Full-duplex Operation Mode
• Integration of Tire Pressure Monitoring, Passive Entry and Remote Keyless Entry
1. General Description
The ATA5823/ATA5824 is a highly integrated UHF ASK/FSK multi-channel half-duplex and
full-duplex transceiver with low power consumption supplied in a small 7 mm × 7 mm QFN48
package. The receive part is built as a fully integrated low-IF receiver, whereas direct PLL modulation with the fractional-N synthesizer is used for FSK transmission and switching of the power
amplifier for ASK transmission. The additional full-duplex mode makes relay attacks much more
difficult, since the attacker has to receive and transmit signals on the same frequency at the
same time.
The device supports data rates of 1 kBaud to 20 kBaud (FSK) and 1 kBaud to 10 kBaud (ASK)
in Manchester, Bi-phase and other codes in transparent mode. The ATA5824 can be used in the
433 MHz to 435 MHz band and the 867 MHz to 870 MHz band, the ATA5823 in the 313 MHz to
316 MHz band. The very high system integration level results in few numbers of external components needed.
Due to its blocking and selectivity performance, together with a typical narrow-band key-fob loop
antenna with 15 dB to 20 dB loss, a bulky blocking SAW is not needed in the key fob application.
Additionally, the building blocks needed for a typical RKE and access control system on both
sides, the base and the mobile stations, are fully integrated.
Its digital control logic with self polling and protocol generation provides a fast challenge
response system without using a high-performance microcontroller. Therefore, the
ATA5823/ATA5824 contains a FIFO buffer RAM and can compose and receive the physical
messages themselves. This provides more time for the microcontroller to carry out other functions such as calculating crypto algorithms, composing the logical messages and controlling
other devices. Due to that, a standard 4-/8-bit microcontroller without special periphery and
clocked with the delivered CLK output of about 4.5 MHz is sufficient to control the communication link. This is especially valid for passive entry go and access control systems, where within
less than 100 ms several communication responses with arbitration of the communication partner have to be handled. It is hence possible to design bi-directional RKE and passive entry go
systems with a fast challenge response crypto function and prevention against relay attacks.
2
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
Figure 1-1.
System Block Diagram
ATA5823/ATA5824
RF Transceiver
Antenna
Digital Control
Logic
Power
Supply
Microcontroller
4 ... 8
Matching/
RF Switch
µC_Interface
XTO
2. Pin Configuration
Pinning QFN48
NC
NC
RX_ACTIVE
N_PWR_ON
SCK_PHA
SCK_POL
NC
NC
PWR_ON
RX_TX1
RX_TX2
CDEM
Figure 2-1.
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
32
5
6
ATA5823/ATA5824 31
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
RSSI
CS
TEST3
SCK
SDI_TMDI
SDO_TMDO
CLK
IRQ
POUT
VSINT
NC
XTAL2
NC
NC
NC
AVCC
VS2
VS1
SETPWR
TEST1
DVCC
CS_POL
TEST2
XTAL1
NC
NC
NC
RF_IN
NC
433_N868
NC
R_PWR
PWR_H
RF_OUT
NC
NC
3
4829C–RKE–09/05
Table 2-1.
4
Pin Description
Pin
Symbol
1
NC
Not connected
2
NC
Not connected
3
NC
4
RF_IN
5
NC
6
433_N868
Function
Not connected
RF input
Not connected
Selects RF input/output frequency range
7
NC
8
R_PWR
Resistor to adjust output power
Not connected
9
PWR_H
Pin to select output power
10
RF_OUT
RF output
11
NC
Not connected
12
NC
Not connected
13
NC
Not connected
14
NC
Not connected
15
NC
Not connected
16
AVCC
17
VS2
Power supply input for voltage range 4.4V to 5.6V
18
VS1
Power supply input for voltage range 2.15V to 3.6V
Blocking of the analog voltage supply
19
SETPWR
20
TEST1
Test input, at GND during operation
Internal Programmable Resistor to adjust output power
21
DVCC
Blocking of the digital voltage supply
22
CS_POL
23
TEST2
Test input, at GND during operation
24
XTAL1
Reference crystal
25
XTAL2
Reference crystal
26
NC
27
VSINT
Microcontroller interface supply voltage
28
POUT
Programmable output
29
IRQ
Interrupt request
30
CLK
Clock output to connect a microcontroller
31
SDO_TMDO
32
SDI_TMDI
33
SCK
34
TEST3
Select polarity of pin CS
Not connected
Serial data out/transparent mode data out
Serial data in/transparent mode data in
Serial clock
Test output open during operation
35
CS
36
RSSI
Chip select for serial interface
37
CDEM
38
RX_TX2
Has to be connected GND
39
RX_TX1
Switch pin to decouple LNA in TX mode (RKE mode)
40
PWR_ON
41
NC
Output of the RSSI amplifier
Capacitor to adjust the lower cut-off frequency data filter
Input to switch on the system (active high)
Not connected
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
Table 2-1.
Pin Description (Continued)
Pin
Symbol
42
NC
Function
Not connected
43
SCK_POL
Polarity of the serial clock
44
SCK_PHA
Phase of the serial clock
45
N_PWR_ON
Keyboard input (can also be used to switch on the system, active low)
46
RX_ACTIVE
Indicates RX operation mode
47
NC
Not connected
48
NC
Not connected
GND
DVCC
RX_ACTIVE
Block Diagram
AVCC
Figure 2-2.
Ground/Backplane (exposed die pad)
433_N868
SETPWR
RF transceiver
R_PWR
RF_OUT
TX_DATA (FSK)
PA
RX/TX
switch
RX_TX2
RF_IN
Digital control logic
Power
Supply
VS2
VS1
PA_Enable (ASK)
PWR_H
RX_TX1
Frontend Enable
LNA
CDEM
Fract.-NFrequency
Synthesizer
Signal
processing
(Mixer
IF-filter
IF-amplifier
FSK/ASK
demodulator
Data filter
Data slicer)
RX/TX
FREQ
FREF
13
Demod_Out
TX/RX Data buffer
Control register
Status register
Polling circuit
Bit-check logic
Synchronous logic
(Full duplex
operation mode)
RSSI
Switches
Regulators
Wake-up
Reset
PWR_ON
N_PWR_ON
Reset
XTAL1
XTO
XTAL2
TEST3
CLK
TEST1
POUT
TEST2
IRQ
µC_Interface
CS
CS_POL
SCK
SPI
SDI_TMDI
SCK_POL
SCK_PHA
GND
VSINT
SDO_TMDO
5
4829C–RKE–09/05
3. Typical Key Fob Application for Bi-directional RKE
Typical Key Fob Application for Bi-directional RKE with 5 dBm TX Power, 433.92 MHz
C7
NC
RX_TX2
RX_TX1
NC
PWR_ON
NC
SCK_POL
NC
SCK_PHA
NC
RX_ACTIVE
NC
C6
N_PWR_ON
SCK
SDI_TMDI
NC
ATA5823/ATA5824
433_N868
CLK
VSINT
Loop antenna
NC
NC
C9
NC
NC
C10
VS1
NC
CS_POL
RF_OUT
DVCC
POUT
TEST1
IRQ
PWR_H
SETPWR
R_PWR
VS2
C8
NC
AVCC
R1
L2
Microcontroller
SDO_TMDO
VCC
VSS
NC
TEST2
C5
CS
TEST3
RF_IN
AVCC
CDEM
RSSI
XTAL1
C11
20 mm × 0.4 mm
L1
NC
Figure 3-1.
XTAL2
13.25311 MHz
C1
C2
C3
+
Litihum-cell
Figure 3-1 shows a typical 433.92 MHz RKE key fob application. The external components are
10 capacitors, 1 resistor, 2 inductors and a crystal. C1 to C3 are 68 nF voltage supply blocking
capacitors. C5 is a 10 nF supply blocking capacitor. C6 is a 15 nF fixed capacitor used for the
internal quasi-peak detector and for the high-pass frequency of the data filter. C7 to C11 are RF
matching capacitors in the range of 1 pF to 33 pF. L1 is a matching inductor of about 5.6 nH to
56 nH. L2 is a feed inductor of about 120 nH. A load capacitor of 9 pF for the crystal is integrated. R1 is typically 22 kΩ and sets the output power to about 5.5 dBm. The loop antenna’s
quality factor is somewhat reduced by this application due to the quality factor of L2 and the
RX/TX switch. On the other hand, this lower quality factor is necessary to have a robust design
with a bandwidth that is wide enough for production tolerances. Due to the single-ended and
ground-referenced design, the loop antenna can be a free-form wire around the application as it
is usually employed in RKE unidirectional systems. The ATA5823/ATA5824 provides sufficient
isolation and robust pulling behavior of internal circuits from the supply voltage as well as an
integrated VCO inductor to allow this. Since the efficiency of a loop antenna is proportional to the
square of the surrounded area, it is beneficial to have a large loop around the application board
with a lower quality factor to relax the tolerance specification of the RF matching components
and to get a high antenna efficiency in spite of their lower quality factor.
6
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
4. Typical Car Application for Bi-directional RKE
Figure 4-1.
Typical Car Application for Bi-directional RKE with 10 dBm TX Power, 433.92 MHz
SAW filter
L3
C7
NC
RX_TX2
RX_TX1
NC
PWR_ON
NC
SCK_POL
SCK_PHA
NC
N_PWR_ON
NC
NC
RX_ACTIVE
SCK
SDI_TMDI
NC
VSINT
NC
C9
NC
C10
NC
NC
RFOUT
VCC
VSS
NC
TEST2
NC
DVCC
RF_OUT
TEST1
POUT
SETPWR
IRQ
PWR_H
VS1
L1 C8
CLK
R_PWR
VS2
50 Ω
connector
ATA5823/ATA5824
NC
AVCC
R1
L2
Microcontroller
SDO_TMDO
433_N868
CS_POL
C5
CS
TEST3
RF_IN
AVCC
CDEM
RSSI
XTAL1
C11
C6
NC
20 mm × 0.4 mm
L4
XTAL2
13.25311 MHz
C1
C2
C4
C3
VCC = 4.4 V ... 5.25 V
Figure 4-1 shows a typical 433.92 MHz VCC = 4.4V to 5.25V RKE car application. The external
components are 11 capacitors, 1 resistor, 4 inductors, a SAW filter and a crystal. C1, C3 and C4
are 68 nF voltage supply blocking capacitors. C2 is a 2.2 µF supply blocking capacitor for the
internal voltage regulator. C5 is a 10 nF supply blocking capacitor. C6 is a 15 nF fixed capacitor
used for the internal quasi-peak detector and for the high-pass frequency of the data filter. C7 to
C11 are RF matching capacitors in the range of 1 pF to 33 pF. L2 to L4 are matching inductors of
about 5.6 nH to 56 nH. A load capacitor for the crystal of 9 pF is integrated. R1 is typically 22 kΩ
and sets the output power at RFOUT to about 10 dBm. Since a quarter wave or PCB antenna,
which has high efficiency and wideband operation, is typically used here, it is recommended to
use a SAW filter to achieve high sensitivity in case of powerful out-of-band blockers. L1, C10 and
C9 together form a low-pass filter, which is needed to filter out the harmonics in the transmitted
signal to meet regulations.
7
4829C–RKE–09/05
5. Typical Key Fob Application for Full-duplex PEG
Figure 5-1.
Typical Key Fob Application for Full-duplex PEG, 433.92 MHz
NC
RX_TX2
RX_TX1
NC
PWR_ON
NC
SCK
SDI_TMDI
NC
IRQ
PWR_H
POUT
RF_OUT
VSINT
C9
VCC
VSS
NC
TEST2
VS1
NC
NC
NC
NC
VS2
NC
DVCC
C8
CLK
ATA5823/ATA5824
R_PWR
AVCC
20% overlap
NC
TEST1
L2
SETPWR
R1
Loop antenna 2
Microcontroller
SDO_TMDO
433_N868
CS_POL
C7
CS
TEST3
RF_IN
AVCC
CDEM
RSSI
XTAL1
C5
SCK_POL
NC
C6
SCK_PHA
RX_ACTIVE
NC
N_PWR_ON
NC
NC
C4
XTAL2
13.25311 MHz
C1
Loop antenna 1
C2
C10
C3
+
Litihum-cell
Figure 5-1 shows a typical 433.92 MHz PEG key fob application. The external components are
10 capacitors, 1 resistor, 1 inductor and a crystal. C1 to C3 are 68 nF voltage supply blocking
capacitors. C7 is a 10 nF supply blocking capacitor. C4 is a 15 nF fixed capacitor used for the
internal quasi-peak detector and for the high-pass frequency of the data filter. C5, C6, C8 and C9
are RF matching capacitors in the range of 1 pF to 33 pF. L2 is a feed inductor of about 120 nH.
C10 is a 10 nF capacitor which is necessary to prevent that signals couple into the pin R_PWR,
causing amplitude modulation of the output power and a spurious rise of the transmitted signal.
R1 and C10 should be placed close to the R_PWR pin. A load capacitor of 9 pF for the crystal is
integrated. R1 is typically 22 kΩ and SETPWR is programmed to get an output power of –7 dBm
in full-duplex mode and 5 dBm in half-duplex mode. The quality factor of the loop antenna 1 is
only reduced by the quality factor of L2, the tolerances of C9 and C8 are thus important. The quality factor of the loop antenna 2 is reduced to half due to the loading with the input impedance of
RF_IN. With well designed loop antennas and the correct degree of overlapping, the isolation
between RF_OUT and RF_IN is about 28 dB and the coupled output power from RF_OUT to
RF_IN is about –35 dBm. The decoupling of two loop antennas situated close to each other is
due to the effect that the magnetic flux from the part of loop antenna 1 that does not overlap and
that of the overlapping part has an opposite direction. Depending on the relative position
between the two antennas, a decoupling of 28 dB is achievable. Due to additional capacitive
coupling between the loops the position of the components C5, C6 and C8, C9 are also important.
The receive Sensitivity in full-duplex mode is reduced from –106 dBm without coupled
RF-Power at RF_IN to –96 dBm with –35 dBm coupled RF power at RF_IN.
8
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
6. Typical Car Application for Full-duplex PEG
Figure 6-1.
Typical Car Application for Full-duplex PEG, 433.92 MHz
50 Ω
connector to
RX antenna
NC
RX_TX2
RX_TX1
NC
PWR_ON
NC
SCK_POL
NC
SCK
SDI_TMDI
NC
IRQ
PWR_H
POUT
RF_OUT
VSINT
VCC
VSS
NC
TEST2
VS1
NC
NC
NC
NC
VS2
TX Loop antenna
(located in the control unit)
AVCC
NC
DVCC
C10
CLK
R_PWR
TEST1
L1
ATA5823/ATA5824
NC
SETPWR
R1
Microcontroller
SDO_TMDO
433_N868
CS_POL
C5
CS
TEST3
RF_IN
AVCC
CDEM
RSSI
XTAL1
L3
C8
SCK_PHA
NC
N_PWR_ON
NC
C7
RX_ACTIVE
SAW filter
L2
NC
RFIN
C6
C9
XTAL2
13.25311 MHz
C1
C2
C4
C11
C3
VCC = 4.4 V ... 5.25 V
Figure 6-1 shows a typical 433.92 MHz VCC = 4.4V to 5.25V PEG car application. The external
components are 11 capacitors, 1 resistor, 3 inductors, a SAW Filter and a crystal. C1, C3 and C4
are 68 nF voltage supply blocking capacitors. C2 is a 2.2 µF supply blocking capacitors for the
internal voltage regulator. C5 is a 10 nF supply blocking capacitor. C6 is a 15 nF fixed capacitor
used for the internal quasi-peak detector and for the high-pass frequency of the data filter. C7 to
C10 are RF matching capacitors in the range of 1 pF to 33 pF. L1 is a feed inductor of about
120 nH, L2 and L3 are matching inductors to match the RX-antenna to the SAW and the SAW to
RF_IN. A load capacitor of 9 pF for the crystal is integrated. C11 is a 10 nF capacitor which is
necessary to prevent that signals couple into the pin R_PWR, causing amplitude modulation of
the output power and a spurious rise of the transmitted signal. R1 and C11 should be placed
close to the R_PWR pin. R1 is typically 22 kΩ and SETPWR is programmed to get an output
power of 0 dBm in full-duplex mode and 5 dBm in half-duplex mode. The quality factor of the
TX-loop antenna is only reduced by the quality factor of L1, the tolerances of C9 and C10 are thus
important. Since the 2 Antennas are located at different places the isolation between RF_OUT
and RF_IN is about 45 dB and the coupled output power from RF_OUT to RF_IN is about
–45 dBm. The receive Sensitivity in full-duplex mode is reduced from –106 dBm without coupled
RF power at RF_IN to –102 dBm with –45 dBm coupled RF power at RF_IN. The use of SAW filters in the full-duplex system is unsuitable due to the high group delay which desensitize the
receiver.
9
4829C–RKE–09/05
7. RF Transceiver in Half-duplex Mode
According to Figure 2-2 on page 5, the RF transceiver consists of an LNA (Low-Noise Amplifier),
PA (Power Amplifier), RX/TX switch, fractional-N frequency synthesizer and the signal processing part with mixer, IF filter, IF amplifier with analog RSSI, FSK/ASK demodulator, data filter and
data slicer.
In receive mode the LNA pre-amplifies the received signal which is converted down to 226 kHz
intermediate frequency (IF), filtered and amplified before it is fed into an FSK/ASK demodulator,
data filter and data slicer. The RSSI (Received Signal Strength Indicator) signal and the raw digital output signal of the demodulator are available at the pins RSSI and on TEST3 (open drain
output). The demodulated data signal Demod_Out is fed into the digital control logic where it is
evaluated and buffered as described in section “Digital Control Logic” on page 35.
In transmit mode the fractional-N frequency synthesizer generates the TX frequency which is fed
into the PA. In ASK mode the PA is modulated by the signal PA_Enable. In FSK mode the PA is
enabled and the signal TX_DATA (FSK) modulates the fractional-N frequency synthesizer. The
frequency deviation is digitally controlled and internally fixed to about ±19.5 kHz (see Table 9-1
on page 30 for exact values). The transmit data can also be buffered as described in section
“Digital Control Logic” on page 35. A lock detector within the synthesizer ensures that the transmission will only start if the synthesizer is locked.
In half-duplex mode the RX/TX switch can be used to combine the LNA input and the PA output
to a single antenna with a minimum of losses. In full-duplex mode more isolation between
receive and transmit antenna is needed, therefore two antennas have to be used.
Transparent modes without buffering of RX and TX data are also available to allow protocols
and coding schemes other than the internal supported Manchester encoding, like PWM and
pulse position coding.
7.1
Low-IF Receiver
The receive path consists of a fully integrated low-IF receiver. It fulfills the sensitivity, blocking,
selectivity, supply voltage and supply current specification needed to manufacture an automotive key fob for RKE and PEG systems without the use of a SAW blocking filter (see Figure 3-1
on page 6 and Figure 5-1 on page 8). The receiver can be connected to the roof antenna in the
car when using an additional blocking SAW front-end filter as shown in Figure 4-1 on page 7.
At 433.92 MHz the receiver has a typical system noise figure of 6.5 dB, a system I1dBCP of
–30 dBm and a system IIP3 of –20 dBm. The signal path is linear for disturbers up to the I1dBCP
and there is hence no AGC or switching of the LNA needed to achieve a better blocking performance. This receiver uses an IF of about 226 kHz (see table “Electrical Characteristics” number
2.10 for exact values), the typical image rejection is 30 dB and the typical 3 dB system bandwidth is 220 kHz (f I F = 226 kHz ±110 kHz, f lo _ I F = 116 kHz and f h i_ I F = 336 kHz). The
demodulator needs a signal to noise ratio of 8 dB for 20 kBaud Manchester with ±19.5 kHz frequency deviation in FSK mode, thus, the resulting sensitivity at 433.92 MHz is typically
–105.5 dBm.
Due to the low phase noise and spurious of the synthesizer in receive mode(1) together with the
eighth order integrated IF filter the receiver has a better selectivity and blocking performance
than more complex double superhet receivers, without using external components and without
numerous spurious receiving frequencies.
Note:
10
1. –120 dBC/Hz at ±1 MHz and –72 dBC at ±fXTO at 433.92 MHz
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than direct
conversion receivers where every pulse or amplitude modulated signal (especially the signals
from TDMA systems like GSM) demodulates to the receiving signal band at second-order
non-linearities.
7.2
Input Matching at RF_IN
The measured input impedances as well as the values of a parallel equivalent circuit of these
impedances can be seen in Table 7-1. The highest sensitivity is achieved with power matching
of these impedances to the source impedance of 50Ω.
Table 7-1.
Measured Input Impedances of the RF_IN Pin
fRF/MHz
ZIn(RF_IN)
RIn_p//CIn_p
315
(44-j233)Ω
1278Ω//2.1 pF
433.92
(32-j169)Ω
925Ω//2.1 pF
868.3
(21-j78)Ω
311Ω//2.2 pF
The matching of the LNA Input to 50Ω was done with the circuit according to Figure 7-1 and with
the values of the matching elements given in Table 7-2. The reflection coefficients were always
≤ –10 dB. Note that value changes of C1 and L1 may be necessary to compensate individual
board layout parasitics. The measured typical FSK and ASK Manchester code sensitivities with
a Bit Error Rate (BER) of 10-3 are shown in Table 7-3 on page 12 and Table 7-4 on page 12.
These measurements were done with multilayer inductors having quality factors according to
Table 7-2, resulting in estimated matching losses of 0.8 dB at 315 MHz, 0.8 dB at 433.92 MHz
and 0.7 dB at 868.3 MHz. These losses can be estimated when calculating the parallel equivalent resistance of the inductor with R loss = 2 × π × f × L × Q L and the matching loss with
10 log(1+RIn_p/Rloss).
With an ideal inductor, for example, the sensitivity at 433.92 MHz/FSK/20 kBaud/
±19.5 kHz/Manchester can be improved from –105.5 dBm to –106.7 dBm. The sensitivity also
depends on the values in the registers of the control logic which examines the incoming data
stream. The examination limits must be programmed in control registers 5 and 6. The measurements in Table 7-3 and Table 7-4 on page 12 are based on the values of registers 5 and 6
according to Table 14-3 on page 60.
Figure 7-1.
Input Matching to 50Ω
ATA5823/ATA5824
C1
4
RF_IN
L1
11
4829C–RKE–09/05
Table 7-2.
Table 7-3.
Input Matching to 50Ω
fRF/MHz
C1/pF
L1/nH
QL1
315
2.4
47
65
433.92
1.8
27
67
868.3
1.2
6.8
50
Measured Typical Sensitivity 433.92 MHz, FSK, ±19.5 kHz, Manchester, BER = 10-3
RF Frequency
BR_Range_0
1.0 kBaud
BR_Range_0
2.4 kBaud
BR_Range_1
5.0 kBaud
BR_Range_2
10 kBaud
BR_Range_3
20 kBaud
315 MHz
–109.5 dBm
–110.0 dBm
–109.0 dBm
–107.5 dBm
–106.5 dBm
433.92 MHz
–108.5 dBm
–109.0 dBm
–108.0 dBm
–106.5 dBm
–105.5 dBm
868.3 MHz
–105.5 dBm
–106.5 dBm
–105.5 dBm
–103.5 dBm
–103.0 dBm
Table 7-4.
Measured Typical Sensitivity 433.92 MHz, 100% ASK, Manchester, BER = 10-3
RF Frequency
BR_Range_0
1.0 kBaud
BR_Range_0
2.4 kBaud
BR_Range_1
5.0 kBaud
BR_Range_2
10 kBaud
315 MHz
–117.0 dBm
–117.0 dBm
–114.5 dBm
–112.5 dBm
433.92 MHz
–116.0 dBm
–116.0 dBm
–113.5 dBm
–111.5 dBm
868.3 MHz
–113.0 dBm
–113.0 dBm
–111.5 dBm
–109.0 dBm
7.3
Sensitivity versus Supply Voltage, Temperature and Frequency Offset
To calculate the behavior of a transmission system it is important to know the reduction of the
sensitivity due to several influences. The most important are frequency offset due to crystal
oscillator (XTO) and crystal frequency (XTAL) errors, temperature and supply voltage dependency of the noise figure and IF filter bandwidth of the receiver. Figure 7-2 shows the typical
sensitivity at 433.92 MHz/FSK/20 kBaud/±19.5 kHz/Manchester versus the frequency offset
between transmitter and receiver at T amb = – 40°C, +25°C and +105°C and supply voltage
VS = VS1 = VS2 = 2.15V, 3.0V and 3.6V.
Figure 7-2.
Measured Sensitivity 433.92 MHz/FSK/20 kBaud/±19.5 kHz/Manchester versus Frequency Offset, Temperature and Supply Voltage
-110.0
-109.0
-108.0
-107.0
Sensitivity/dBm
-106.0
VS = 2.15 V Tamb = -40°C
-105.0
VS = 3.0 V Tamb = -40°C
-104.0
VS = 3.6 V Tamb = -40°C
-103.0
VS = 2.15 V Tamb = 25°C
-102.0
VS = 3.0 V Tamb = 25°C
-101.0
VS = 3.6 V Tamb = 25°C
-100.0
VS = 2.15 V Tamb = 105°C
-99.0
VS = 3.0 V Tamb = 105°C
-98.0
VS = 3.6 V Tamb = 105°C
-97.0
-96.0
-95.0
-100
12
-80
-60
-40
-20
0
20
Frequency Offset/kHz
40
60
80
100
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
As can be seen in Figure 7-2 on page 12 the supply voltage has almost no influence on the sensitivity. The temperature has an influence of about +1.5/ –0.7 dB and a frequency offset of
±85 kHz also influences by about ±1 dB. All these influences, combined with the sensitivity of a
typical IC (–105.5dBm), are then within a range of –102.5 dBm and –107 dBm overtemperature,
supply voltage and frequency offset. The integrated IF filter has an additional production tolerance of ±10 kHz, hence, a frequency offset between the receiver and the transmitter of ±75 kHz
can be accepted for XTAL and XTO tolerances.
Note:
For the demodulator used in the ATA5823/ATA5824, the tolerable frequency offset does not
change with the data frequency, hence, the value of ±75 kHz is valid for 1 kBaud to 20 kBaud.
This small sensitivity change over supply voltage, frequency offset and temperature is very
unusual in such a receiver. It is achieved by an internal, very fast and automatic frequency correction in the FSK demodulator after the IF filter, which leads to a higher system margin. This
frequency correction tracks the input frequency very quickly, if however, the input frequency
makes a larger step (e.g., if the system changes between different communication partners), the
receiver has to be restarted. This can be done by switching back to IDLE mode and then again
to RX mode. For that purpose, an automatic mode is also available. This automatic mode
switches to IDLE mode and back into RX mode every time a bit error occurs (see section “Digital
Control Logic” on page 35).
7.4
Frequency Accuracy of the Crystals in Bi-directional RKE/PEG
The XTO is an amplitude regulated Pierce type oscillator with integrated load capacitors. The initial tolerances (due to the frequency tolerance of the XTAL, the integrated capacitors on XTAL1,
XTAL2 and the XTO’s initial transconductance gm) can be compensated to a value within
±0.5 ppm by measuring the CLK output frequency and tuning of fRF by programming the control
registers 2 and 3 (see Table 12-7 on page 38 and Table 12-10 on page 39). The XTO then has
a remaining influence of less than ±2 ppm overtemperature and supply voltage due to the bandgap controlled gm of the XTO. Thus only 2.5 ppm add to the frequency stability of the used
crystals overtemperature and aging.
The needed frequency stability of the used crystals overtemperature and aging is hence
±75 kHz/433.92 MHz – 2 × ±2.5 ppm = ±167.84 ppm for 433.92 MHz and
±75 kHz/868.3 MHz – 2 × ±2.5 ppm = ±81.4 ppm for 868.3 MHz. Thus, the used crystals in
receiver and transmitter each need to be better than ±83.9 ppm for 433.92 MHz and ±40.7 ppm
for 868.3 MHz.
7.5
Frequency Accuracy of the Crystals in a Combined RKE/PEG and TPM System
In a tire pressure measurement system working at 433.92 MHz and using a TPM transmitter
ATA5757 and a transceiver ATA5824 as a receiver, the higher frequency tolerances and the tolerance of the frequency deviation of this transmitter has to be considered.
In the TPM transmitter the crystal has an frequency error overtemperature –40°C to +125°C,
aging and tolerance of ±80 ppm (±34.7 kHz at 433.92 MHz). The tolerances of the XTO, the
capacitors used for FSK-Modulation and the stray capacitors, causing an additional frequency
error of ±30 ppm (±13 kHz at 433.92 MHz). The frequency deviation of such a transmitter varies
between ±16 kHz and ±24 kHz, since a higher frequency deviation is equivalent to an frequency
error, this has to be considered as an additional ±24 kHz – ±19.5 kHz = ±4.5kHz frequency tolerance. All tolerances added, these transmitters have a worst case frequency offset of
±52.2 kHz.
13
4829C–RKE–09/05
For the transceiver in the car a tolerance of ±75 kHz – ±52.2 kHz = ±22.8 kHz (±52.5 ppm)
remains. The needed frequency stability of the used crystals overtemperature and aging is
±52.5 ppm – ±2.5 ppm = ±50 ppm. The aging of such a crystal is ±10 ppm leaving reasonable
±40 ppm for the temperature dependency of the crystal frequency in the car.
Since the transceiver in the car is able to receive these TPM transmitter signals with high frequency offsets, the component specification in the key can be largely relaxed.
This system calculation is based on worst case tolerances of all the components, this leads in
practice to a system with margin.
For a 315 MHz TPM system using a TPM transmitter ATA5756 and a transceiver ATA5823 as
receiver the same calculation must be done, but since the RF frequency is lower, every ppm of
crystal tolerances results in less frequency offset and either the system can have higher tolerances or a higher margin there.
For 868 MHz it is not possible to use the transceiver ATA5824 in a combined RKE/PEG and
TPM system since all the tolerances double because of the higher RF frequency.
7.6
RX Supply Current versus Temperature and Supply Voltage
Table 7-5 shows the typical supply current at 433.92 MHz of the transceiver in RX mode versus
supply voltage and temperature with VS = V S1 = V S2. As can be seen the supply current at
VS = 2.15V and Tamb = –40°C is less than at VS = 3V/Tamb = 25° which helps to enlarge the battery lifetime within a key fob application because this is also the operation point where a lithium
cell has the worst performance. The typical supply current at 315 MHz or 868.3 MHz in RX mode
is about the same as for 433.92 MHz.
Table 7-5.
7.7
Measured 433.92 MHz Receive Supply Current in FSK mode
VS = VS1 = VS2
2.15V
3.0V
3.6V
Tamb = –40°C
8.2 mA
8.8 mA
9.2 mA
Tamb = 25°C
9.7 mA
10.3 mA
10.8 mA
Tamb = 105°C
11.2 mA
11.9 mA
12.4 mA
Blocking, Selectivity
As can be seen in Figure 7-3, Figure 7-4 and Figure 7-5 on page 15, the receiver can receive
signals 3 dB higher than the sensitivity level in presence of large blockers of
–44.5 dBm/-36.0 dBm with small frequency offsets of ±1/ ±10 MHz.
Figure 7-3 and Figure 7-4 on page 15 shows the close-in and narrow-band blocking and Figure
7-5 on page 15 the wide-band blocking characteristic. The measurements were done with a useful signal of 433.92 MHz/FSK/20 kBaud/±19.5 kHz/Manchester with a level of
–105.5 dBm + 3 dB = –102.5 dBm which is 3 dB above the sensitivity level. The figures show by
how much a continuous wave signal can be larger than –102.5 dBm until the BER is higher than
10-3. The measurements were done at the 50Ω input according to Figure 7-1 on page 11. At
1 MHz, for example, the blocker can be 58 dBC higher than –102.5 dBm which is –102.5 dBm
+58 dBC = –44.5 dBm. These blocking figures, together with the good intermodulation performance, avoid the additional need of a SAW filter in the key fob application.
14
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
Figure 7-3.
Close In 3 dB Blocking Characteristic and Image Response at 433.92 MHz
70.0
Blocking [dBC]
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-1.0
-0.8
-0.6
-0.4
-0.2
-0.0
0.2
0.4
0.6
0.8
1.0
Distance of Interfering to Receiving Signal [MHz]
Figure 7-4.
Narrow Band 3 dB Blocking Characteristic at 433.92 MHz
70.0
Blocking [dBC]
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
Distance of Interfering to Receiving Signal [MHz]
Figure 7-5.
Wide Band 3 dB Blocking Characteristic at 433.92 MHz
80.0
70.0
Blocking [dBC]
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
10.0
20.0
30.0
40.0
50.0
Distance of Interfering to Receiving Signal [MHz]
15
4829C–RKE–09/05
Table 7-6 shows the blocking performance measured relative to –102.5 dBm for some frequencies. Note that sometimes the blocking is measured relative to the sensitivity level –105.5 dBm
(denoted dBS) instead of the carrier –102.5 dBm (denoted dBC).
Blocking 3 dB Above Sensitivity Level with BER < 10-3
Table 7-6.
Frequency Offset
Blocker Level
Blocking
+0.75 MHz
–47.5 dBm
55.0 dBC/58.0 dBS
–0.75 MHz
–47.5 dBm
55.0 dBC/58.0 dBS
+1.0 MHz
–44.5 dBm
58.0 dBC/61.0 dBS
–1.0 MHz
–44.5 dBm
58.0 dBC/61.0 dBS
+1.5 MHz
–42.0 dBm
60.5 dBC/63.5 dBS
–1.5 MHz
–42.0 dBm
60.5 dBC/63.5 dBS
+10 MHz
–35.5 dBm
67.0 dBC/70.0 dBS
–10 MHz
–35.5 dBm
67.0 dBC/70.0 dBS
The ATA5823/ATA5824 can also receive FSK and ASK modulated signals if they are much
higher than the I1dBCP. It can typically receive useful signals at +10 dBm. This is often referred
to as the nonlinear dynamic range which is the maximum to minimum receiving signal which is
115.5 dB for 433.92 MHz/FSK/20kBaud/±19.5 kHz/ Manchester. This value is useful if two
transceivers have to communicate and are very close to each other.
In a keyless entry system there is another blocking characteristic that has to be considered. A
keyless entry system has a typical service range of about 30 m with a receiver sensitivity of
about –106 dBm to –109 dBm. In some cases, large blockers limit this service range, and it is
important to know how large this blockers can be until the system doesn’t work anymore and the
user has to use its key. With a recommended sensitivity of about –85 dBm, the system works
just around the car. Figure 7-6 and Figure 7-7 on page 17 show the blocking performance in this
important case with a useful signal of – 85dBm 433.92 MHz/FSK/20kBaud/±19.5 kHz/
Manchester.
As can be seen the system works even with blockers above the compression point. This is due
to a wide bandwidth automatic gain control that begins to work if blockers above the compression point are at the antenna input and increasing the current in the LNA/Mixer to get a better
compression point needed to handle these large blockers.
Figure 7-6.
±2.5 MHz Blocking Characteristic for –85 dBm Useful Signal at 433.92 MHz
-20.0
Blocker Level [dBm]
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
Distance of Interfering to Receiving Signal [MHz]
16
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
Figure 7-7.
±50 MHz Blocking Characteristic for –85 dBm Useful Signal at 433.92 MHz
0.0
Blocker Level [dBm]
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
10.0
20.0
30.0
40.0
50.0
Distance of Interfering to Receiving Signal [MHz]
This high blocking performance makes it even possible for some applications using quarter
wave whip antennas to use a simple LC band-pass filter instead of a SAW filter in the receiver.
When designing such a LC filter, take into account that the 3 dB blocking at
433.92 MHz/2 = 216.96 MHz is 42 dBC and at 433.92 MHz/3 = 144.64 MHz is 47 dBC and at
2 × (433.92 MHz + 226 kHz) + –226 kHz = 868.066 MHz/868.518 MHz is 50 dBC. And especially that at 3 × (433.92 MHz + 226 kHz)+226 kHz = 1302.664 MHz the receiver has a second
LO harmonic receiving frequency with only 17 dBC blocking.
7.8
Inband Disturbers, Data Filter, Quasi-peak Detector, Data Slicer
If a disturbing signal falls into the received band, or a blocker is not a continuous wave, the performance of a receiver strongly depends on the circuits after the IF filter. Hence the
demodulator, data filter and data slicer are important in that case.
The data filter of the ATA5823/ATA5824 implies a quasi-peak detector. This results in a good
suppression of above mentioned disturbers and exhibits a good carrier to noise performance.
The required ratio of useful signal to disturbing signal, at a BER of 10-3 is less than 12 dB in ASK
mode and less than 3 dB (BR_Range_0 ... BR_Range_2) and 6 dB (BR_Range_3) in FSK
mode. Due to the many different possible waveforms these numbers are measured for signal as
well as for disturbers with peak amplitude values. Note that these values are worst case values
and are valid for any type of modulation and modulating frequency of the disturbing signal as
well as the receiving signal. For many combinations, lower carrier to disturbing signal ratios are
needed.
7.9
TEST3 Output
The internal raw output signal of the demodulator Demod_Out is available at pin TEST3. TEST3
is an open drain output and must be connected to a pull-up resistor if it is used (typically 100 kΩ),
otherwise no signal is present at that pin. This signal is mainly used for debugging purposes during the setup of a new application, since the received data signal can be seen there without any
digital processing.
17
4829C–RKE–09/05
7.10
RSSI Output
The output voltage of the pin RSSI is an analog voltage, proportional to the input power level.
Using the RSSI output signal, the signal strength of different transmitters can be distinguished.
The usable dynamic range of the RSSI amplifier is 70 dB, the input power range P RFIN is
–115 dBm to –45 dBm and the gain is 8 mV/dB. Figure 7-8 on page 18 shows the RSSI characteristic of a typical device at 433.92 MHz with VS1 = VS2 = 2.15V to 3.6V and Tamb = –40°C to
+105°C with a matched input according to Table 7-2 on page 12 and Figure 7-1 on page 11. At
868.3 MHz about 2.7 dB more signal level and at 315 MHz about 1 dB less signal level is
needed for the same RSSI results.
Figure 7-8.
Typical RSSI Characteristic at 433.92 MHz versus Temperature and Supply
Voltage
1100
VRSSI (mV)
1000
900
800
700
max.
typ.
min.
600
500
400
-120
-110
-100
-90
-80
-70
-60
-50
-40
PRF_IN (dBm)
7.11
Frequency Synthesizer and Channel Selection
The synthesizer is a fully integrated fractional-N design with internal loop filters for receive and
transmit mode. The XTO frequency fXTO is the reference frequency FREF for the synthesizer.
The bits FR0 to FR12 in control registers 2 and 3 (see Table 12-7 on page 38 and Table 12-10
on page 39) are used to adjust the deviation of f XTO . In half-duplex transmit mode, at
433.92 MHz, the carrier has a phase noise of –111 dBC/Hz at 1 MHz and spurious at FREF of
– 70 dBC with a high PLL loop bandwidth allowing the direct modulation of the carrier with
20 kBaud Manchester data. Due to the closed loop modulation, any spurious caused by this
modulation are effectively filtered out as can be seen in Figure 7-11 on page 20. In RX mode the
synthesizer has a phase noise of –120 dBC/Hz at 1 MHz and spurious of –72 dBC.
The initial tolerances of the crystal oscillator due to crystal frequency tolerances, internal capacitor tolerances and the parasitics of the board have to be compensated at manufacturing setup
with control registers 2 and 3 as can be seen in Table 9-1 on page 30. The other control words
for the synthesizer needed for ASK, FSK and receive/transmit switching are calculated internally. The RF (Radio Frequency) resolution is equal to the XTO frequency divided by 16384
which is 777.1 Hz at 315.0 MHz, 808.9 Hz at 433.92 MHz and 818.59 Hz at 868.3 MHz.
The frequency control word FREQ in control registers 2 and 3 can be programmed in the range
of 1000 to 6900, hence every frequency within the 433 MHz and 868 MHz ISM bands can be
programmed as receive and as transmit frequency and the position of channels within these ISM
bands can be chosen arbitrarily (see Table 9-1 on page 30).
18
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
Care must be taken regarding the harmonics of the CLK output signal as well as to the harmonics produced by a microprocessor clocked with it, since these harmonics can disturb the
reception of signals. In a single channel system using FREQ = 3803 to 4053 ensures that harmonics of this signal, do not disturb the receive mode.
7.12
FSK/ASK Transmission
Due to the fast modulation capability of the synthesizer and the high resolution, the carrier can
be internally FSK modulated which simplifies the application of the transceiver. The deviation of
the transmitted signal is ±24 digital frequency steps of the synthesizer which is equal to
±18.65 kHz for 315 MHz, ±19.41 kHz for 433.92 MHz and ±19.64 kHz for 868.3 MHz.
Due to closed loop modulation with PLL filtering, the modulated spectrum is very clean, meeting
ETSI and CEPT regulations when using a simple LC filter for the power amplifier harmonics as it
is shown in Figure 4-1. In ASK mode the frequency is internally connected to the center of the
FSK transmission and the power amplifier is switched on and off to perform the modulation.
Figure 7-9 to Figure 7-11 on page 20 show the spectrum of the FSK modulation with
pseudo-random data with 20 kBaud/±19.41 kHz/Manchester and 5 dBm output power.
Figure 7-9.
FSK-modulated TX Spectrum (433.92 MHz/20 kBaud/±19.41 kHz/Manchester Code)
Ref 10 dBm
Samp
Atten 20 dB
Log
10
dB/
VAvg
50
W1 S2
S3 FC
Center 433.92 MHz
Res BW 100 kHz
VBW 100 kHz
Span 30 MHz
Sweep 7.5 ms (401 pts)
19
4829C–RKE–09/05
Figure 7-10. Unmodulated TX Spectrum 433.92 MHz - 19.41 kHz (fFSK_L)
Ref 10 dBm
Samp
Atten 20 dB
Log
10
dB/
VAvg
50
W1 S2
S3 FC
Center 433.92 MHz
Res BW 10 kHz
VBW 10 kHz
Span 1 MHz
Sweep 27.5 ms (401 pts)
Figure 7-11. FSK-modulated TX Spectrum (433.92 MHz/20 kBaud/±19.41 kHz/Manchester Code)
Ref 10 dBm
Samp
Atten 20 dB
Log
10
dB/
VAvg
50
W1 S2
S3 FC
Center 433.92 MHz
Res BW 10 kHz
20
VBW 10 kHz
Span 1 MHz
Sweep 27.5 ms (401 pts)
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
7.13
Output Power Setting and PA Matching at RF_OUT
The Power Amplifier (PA) is a single-ended open collector stage which delivers a current pulse
which is nearly independent of supply voltage, temperature and tolerances due to band-gap stabilization. Resistor R1 (see Figure 7-12 on page 22) sets a reference current which controls the
current in the PA. A higher resistor value results in a lower reference current, a lower output
power and a lower current consumption of the PA. The usable range of R1 is 15 kΩ to 56 kΩ. The
PWR_H pin switches the output power range between about 0 dBm to 5 dBm (PWR_H = GND)
and 5 dBm to 10 dBm (PWR_H = AVCC) by multiplying this reference current with a factor 1
(PWR_H = GND) and 2.5 (PWR_H = AVCC) which corresponds to about 5 dB more output
power.
If the PA is switched off in TX mode, the current consumption without output stage and with
VS1 = VS2 = 3V, Tamb = 25°C is typically 6.5 mA for 868.3 MHz and 6.95 mA for 315 MHz and
433.92 MHz.
The maximum output power is achieved with optimum load resistances RLopt according to Table
7-7 on page 22. The compensation of the 1.0 pF output capacitance of the RF_OUT pin will be
achieved by absorbing it into the matching network, consisting of L1, C1, C3 as shown in Figure
7-12 on page 22. There must be also a low resistive DC path to AVCC to deliver the DC current
of the power amplifier's last stage. The matching of the PA output was done with the circuit
according to Figure 7-12 on page 22 with the values in Table 7-7. Note that value changes of
these elements may be necessary to compensate individual board layout parasitics.
Example:
According to Table 7-7 on page 22, with a frequency of 433.92 MHz and output power of
11 dBm, the overall current consumption is typically 17.8 mA. Hence the PA needs
17.8 mA - 6.95 mA = 10.85 mA in this mode which corresponds to an overall power amplifier
efficiency of the PA of (10(11dBm/10) × 1 mW)/(3V × 10.85 mA) × 100% = 38.6% in this case.
Using a higher resistor in this example of R1 = 1.091 × 22 kΩ = 24 kΩ results in 9.1% less current in the PA of 10.85 mA/1.091 = 9.95 mA and 10 × log(1.091) = 0.38 dB less output power if
using a new load resistance of 300Ω × 1.091 = 327Ω. The resulting output power is then
11 dBm – 0.38 dB = 10.6 dBm and the overall current consumption is
6.95 mA + 9.95 mA = 16.9 mA.
The values of Table 7-7 on page 22 were measured with standard multi-layer chip inductors with
quality factors Q according to Table 7-7 on page 22.
Looking to the 433.92 MHz/11 dBm case with the quality factor of QL1 = 43 the loss in this inductor L1 is estimated with the parallel equivalent resistance of the inductor
Rloss = 2 × π × f × L1 × QL1 and the matching loss with 10 log (1 + RLopt/Rloss) which is equal to
0.32 dB losses in this inductor. Taking this into account the PA efficiency is then 42% instead of
38.6%.
Be aware that the high power mode (PWR_H = AVCC) can only be used with a supply voltage
higher than 2.7V, whereas the low power mode (PWR_H = GND) can be used down to 2.15V as
can be seen in the section “Electrical Characteristics: General” on page 72.
The supply blocking capacitor C2 (10 nF) in Figure 7-12 on page 22 has to be placed close to the
matching network because of the RF current flowing through it.
21
4829C–RKE–09/05
An internal programmable resistor SETPWR is programmable with the control register 8,
described in Table 12-25 on page 43. It can be used in conjunction with an external resistor to
adjust the output power by connection it like in the application Figure 5-1 on page 8 or Figure 6-1
on page 9. To do that the output power should be adjusted with an external resistor about 50%
lower than needed for the target output power and reduced with the programmable resistor during production test until the target power is as close as possible to the target. For example, if
using 433.92 MHz at 5 dBm, a resistor of 12k instead of 24k is used and values of PWSET
between 25 and 29 can be used to achieve an output power within 5 dBm ±0.5 dB over production. In full-duplex mode this internal resistor is used to reduce the output power for full-duplex
operation versus the power in half-duplex operation. Note that this resistor is temperature stable
but has tolerances of ±20% and introduces, therefore, additional output power tolerances, it is
recommended to adjust output power during the production test if using the SETPWR resistor.
Figure 7-12. Power Setting and Output Matching
AVCC
C2
L1
ATA5820/ATA5821
C1
10
RF_OUT
RFOUT
8
C3
R_PWR
R1
9
VPWR_H
Table 7-7.
22
PWR_H
Measured Output Power and Current Consumption with VS1 = VS2 = 3V, Tamb = 25°C
Frequency
(MHz)
TX Current
(mA)
Output Power
(dBm)
R1
(kΩ)
VPWR_H
RLopt (Ω)
L1
(nH)
QL1
C1
(pF)
C3
(pF)
315
8.5
0.4
56
0
2500
82
28
1.5
0
315
10.5
5.7
27
0
920
68
32
2.2
0
315
16.7
10.5
27
AVCC
350
56
35
3.9
0
433.92
8.6
0.1
56
0
2300
56
40
0.75
0
433.92
11.2
6.2
22
0
890
47
38
1.5
0
433.92
17.8
11
22
AVCC
300
33
43
2.7
0
868.3
9.3
–0.3
33
0
1170
12
58
1.0
3.3
868.3
11.5
5.4
15
0
471
15
54
1.0
0
868.3
16.3
9.5
22
AVCC
245
10
57
1.5
0
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
7.14
Output Power and TX Supply Current versus Supply Voltage and Temperature
Table 7-8 shows the measurement of the output power for a typical device with VS1 = VS2 = VS in
the 433.92 MHz and 6.2 dBm case versus temperature and supply voltage measured according
to Figure 7-12 on page 22 with components according to Table 7-7 on page 22. As opposed to
the receiver sensitivity the supply voltage has here the major impact on output power variations
because of the large signal behavior of a power amplifier. Thus a 5V system using the internal
voltage regulator shows much less variation than a 2.15V to 3.6V battery system because the
AVCC supply voltage is 3.25V ±0.25V for a 5V system.
The reason is that the amplitude at the output RF_OUT with optimum load resistance is
AVCC – 0.4V and the power is proportional to (AVCC – 0.4V)2 if the load impedance is not
changed. This means that the theoretical output power reduction if reducing the supply voltage
from 3.0V to 2.15V is 10 log ((3V – 0.4V)2/(2.15V – 0.4V)2) = 3.4 dB. Table 7-8 shows that principle behavior in the measurements. This is not the same case for higher voltages, since here,
increasing the supply voltage from 3V to 3.6V should theoretical increase the power by 1.8 dB,
but only 0.9 dB in the measurements shows that the amplitude does not increase with the supply
voltage because the load impedance is optimized for 3V and the output amplitude stays more
constant because of the current source nature of the output.
.
Table 7-8.
Measured Output Power and Supply Current at 433.92 MHz, PWR_H = GND
VS = VS1 = VS2
2.15V
3.0V
3.6V
Tamb = –40°C
9.25 mA
3.2 dBm
10.19 mA
5.5 dBm
10.78 mA
6.2 dBm
Tamb = +25°C
10.2 mA
3.4 dBm
11.19 mA
6.2 dBm
11.79 mA
7.1 dBm
Tamb = +105°C
10.9 mA
3.0 dBm
12.02 mA
5.4 dBm
12.73 mA
6.3 dBm
Table 7-9 shows the relative changes of the output power of a typical device compared to
3.0V/25°C. As can be seen, a temperature change to –40°C as well as to +105°C reduces the
power by less than 1 dB due to the band-gap regulated output current. Measurements of all the
cases in Table 7-7 on page 22 overtemperature and supply voltage have shown about the same
relative behavior as shown in Table 7-9.
Table 7-9.
Measurements of Typical Output Power Relative to 3 V/25°C
VS = VS1 = VS2
2.15V
3.0V
3.6V
Tamb = –40°C
–3.0 dB
–0.7 dB
0 dB
Tamb = +25°C
–2.8 dB
0 dB
+0.9 dB
Tamb = +105°C
–3.2 dB
–0.8 dB
+0.1 dB
23
4829C–RKE–09/05
7.15
RX/TX Switch
The RX/TX switch decouples the LNA from the PA in TX mode, and directs the received power
to the LNA in RX mode. To do this, it has a low impedance to GND in TX mode and a high
impedance to GND in RX mode. The pin 38 (RX_TX2) must always be connected to GND in the
application. To design a proper RX/TX decoupling a linear simulation tool for radio frequency
design together with the measured device impedances of Table 7-1 on page 11, Table 7-7 on
page 22, Table 7-10 on page 24 and Table 7-11 on page 25 should be used. The exact element
values have to be found on board. Figure 7-13 on page 24 shows an approximate equivalent circuit of the switch. The principal switching operation is described here according to the
application of Figure 3-1 on page 6. The application of Figure 4-1 on page 7 works similarly.
.
Table 7-10.
Impedance of the RX/TX Switch RX_TX2 Shorted to GND
Frequency
Z(RX_TX1) TX mode
Z(RX_TX1) RX mode
315 MHz
(4.8 + j3.2)Ω
(11.3 – j214)Ω
433.92 MHz
(4.5 + j4.3)Ω
(10.3 – j153)Ω
868.3 MHz
(5 + j9)Ω
(8.9 – j73)Ω
Figure 7-13. Equivalent Circuit of the Switch
RX_TX1
1.6 nH
2.5 pF
11 Ω
7.16
TX
5Ω
Matching Network in TX Mode
In TX mode the 20 mm long and 0.4 mm wide transmission line which is much shorter than λ/4 is
approximately switched in parallel to the capacitor C9 to GND. The antenna connection between
C8 and C9 has an impedance of about 50Ω looking from the transmission line into the loop
antenna with pin RF_OUT, L2, C10, C8 and C9 connected (using a C9 without the added 7.6 pF
capacitor as discussed later). The transmission line can be approximated with a 16 nH inductor
in series with a 1.5Ω resistor, the closed switch can be approximated according to Table 7-10
with the series connection of 1.6 nH and 5Ω in this mode. To have a parallel resonant high
impedance circuit with little RF power going into it looking, from the loop antenna into the transmission line a capacitor of about 7.6 pF to GND is needed at the beginning of the transmission
line (this capacitor is later absorbed into C9, which is then higher as needed for 50Ω transformation). To keep the 50Ω impedance in RX mode at the end of this transmission line C7 has to be
also about 7.6 pF. This reduces the TX power by about 0.5 dB at 433.92 MHz compared to the
case where the LNA path is completely disconnected.
24
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
7.17
Matching Network in RX Mode
In RX mode the RF_OUT pin has a high impedance of about 7 kΩ in parallel with 1.0 pF at
433.92 MHz as can be seen in Table 7-11 on page 25. This together with the losses of the
inductor L2 with 120 nH and QL2 = 25 gives about 3.7 kΩ loss impedance at RF_OUT. Since the
optimum load impedance in TX mode for the power amplifier at RF_OUT is 890Ω the loss associated with the inductor L2 and the RF_OUT pin can be estimated to be
10 × log(1 + 890/3700) = 0.95 dB compared to the optimum matched loop antenna without L2
and RF_OUT. The switch represents, in this mode at 433.92 MHz, about an inductor of 1.6 nH in
series with the parallel connection of 2.5 pF and 2.0 kΩ. Since the impedance level at pin
RX_TX1 in RX mode is about 50Ω there is only a negligible damping of the received signal by
about 0.1 dB. When matching the LNA to the loop antenna the transmission line and the 7.6 pF
part of C9 has to be taken into account when choosing the values of C11 and L1 so that the
impedance seen from the loop antenna into the transmission line with the 7.6 pF capacitor connected is 50Ω.
Since the loop antenna in RX mode is loaded by the LNA input impedance the loaded Q of the
loop antenna is lowered by about a factor of 2 in RX mode hence the antenna bandwidth is
higher than in TX mode.
.
Table 7-11.
Impedance RF_OUT Pin in RX mode
Frequency
Z(RF_OUT)RX
RP//CP
315 MHz
36Ω − j 502 Ω
7 kΩ/ / 1.0 pF
433.92 MHz
19Ω − j 366 Ω
7 kΩ/ / 1.0 pF
868.3 MHz
2.8Ω −j 141Ω
7 kΩ/ / 1.3 pF
Note that if matching to 50Ω, like in Figure 4-1 on page 7, a high Q wire wound inductor with a
Q > 70 should be used for L2 to minimize its contribution to RX losses which will otherwise be
dominant. The RX and TX losses will be in the range of 1.0 dB there.
8. RF Transceiver in Full-duplex Mode
The full-duplex mode of the ATA5823/ATA5824 is intended to be used for the purpose of security against a so called relay attack in passive entry systems. A property of such a passive entry
system is that the user has not to push a key fob button like in a keyless entry system. If the user
approaches to the door of the car it will wake up the key (in most cases with a low frequency
125 kHz signal) and the communication between the key and the car starts without interaction of
the user and afterwards the door opens.
Due to this new feature of the system there is a new possibility of entering a car without permission. One can trigger this communication, take the 125 kHz signal from the car, remodulate it on
another carrier and transmit it over a much longer distance than intended by the system. Than
receive this signal and remodulate it onto the 125 kHz carrier and retransmit this signal close to
the user having the key fob with permission for the car. Such a system is called an RF-Relay and
therefore this kind of attack is called relay attack. The high frequency signals of the
ATA5823/ATA5824 could be treated the same way if only a half-duplex mode is used within a
passive entry system. If using half-duplex RF transceivers, the attacker can switch the direction
of the relay with a transmit power detector.
25
4829C–RKE–09/05
To prevent that the ATA5823/ATA5824 receives and transmit its RF-signals on the same frequency and at the same time. Since the attacker has then to receive and transmit RF signals at
the same frequency and time it will be much more difficult to built the hardware for this kind of
attack, since its own transmitted output power couples back to its receiver.
This mode works as follows:
Both transceivers transmit FSK with a modulation deviation of half the IF (a frequency deviation
of about ±113 kHz), switches the image rejection in the receive path off and uses the transmit
frequency as local oscillator for the receiver. If both transceivers send FSK-low or both send
FSK-high, the resulting IF is close to zero and is filtered out by the IF-filter. Both receivers
receive than a low-signal by using the ASK demodulator as receiver. If the transceivers send different symbols e.g. FSK-low/FSK-high or FSK-high/FSK-low the resulting IF is close to 226 kHz
and the ASK demodulator receives a high-signal. Since the transceivers are synchronized at the
beginning of the data transfer, they can calculate the transmitted data of the other transceiver
from their own transmitted data and the data received from the ASK demodulator.
To use that mode, the received power from the transmitter side of a transceiver should not couple with a to high magnitude to its LNA otherwise the receive path will be desensitized.
Therefore, two different antennas for transmit and receive are used with good decoupling (see
Figure 5-1 on page 8 and Figure 6-1 on page 9).
Since defined packets are transmitted in FD-mode and the critical point in the transmission is the
synchronization and not the data transfer, the sensitivity in FD-mode is defined for packets with
8 bytes of useful data (usually the response from a crypto-challenge response transmission) and
for a Packet Error Rate PER of 5%. For the full-duplex mode the data rate is fixed to 5 kBaud
The sensitivity of the receiver in full-duplex mode is dependant on the absolute power value and
the phase of the power coupled from the PA to the LNA. Due to the phase dependency, three
values are given in the Table 8-1, the first is the typical and the second and third one shows the
sensitivity variation.
Table 8-1.
Typical Full-duplex Sensitivity Dependent on the Parasitic Received Power and
Coupling Phase from the PA 433.92 MHz/Full-duplex Mode/5 kBaud PER = 5%
at 3V, 25°C
Power from RFOUT at
RFIN/dBm
Typical Sensitivity/dBm
Sensitivity Variation/dBm
–30
–91
–88.5/–92.5
–35
–96
–93.5/–97.5
–40
–100
–97.5/–101.5
–45
–103
–100.5/–104.5
–50
–104
–101.5/–105.5
The IC internal decoupling of the RFIN from RFOUT with a power amplifier load impedance optimized for +5dBm is 65 dB on a well designed PCB, hence the coupling is mainly due to the
cross-coupling of the antennas.
26
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
Table 8-2.
Typical Measured Supply Current and Output Power in Full-duplex Mode
433.92 MHz/Power Amplifier is Load Optimized for +5 dBm, R1 = 22k,
PWRSET = 20, (Battery Application)
VS = VS1 = VS2 = VSINT
2.15V
3.0V
3.6V
Tamb = –40°C
10.2 mA/–6.2 dBm
10.9 mA/–5.2 dBm
11.4 mA/–4.6 dBm
Tamb = +25°C
11.8 mA/–6.4 dBm
12.5 mA/–5.2 dBm
13.1 mA/–4.5 dBm
Tamb = +105°C
13.4 mA/–7.5 dBm
14.2 mA/–5.9 dBm
14.8 mA/–5.0 dBm
Table 8-3.
Typical Measured Supply Current and Output Power in Full-duplex Mode/
433.92 MHz/Power Amplifier is Load Optimized for +5 dBm, R1 = 22k,
PWRSET = 31, (Car Application)
VS = VS2 = VSINT
4.4V
5V
5.25V
Tamb = –40°C
13.6 mA/3.7 dBm
13.6 mA/3.7 dBm
13.6 mA/3.7 dBm
Tamb = +25°C
15.6 mA/4.3 dBm
15.6 mA/4.3 dBm
15.6 mA/4.3 dBm
Tamb = +105°C
17.6 mA/ 4.6 dBm
17.6 mA/4.6 dBm
17.6 mA/4.6 dBm
9. XTO
The XTO is an amplitude regulated Pierce oscillator type with integrated load capacitances
(2 × 18 pF with a tolerance of ±17%) hence CLmin = 7.4 pF and CLmax = 10.6 pF. The XTO oscillation frequency fXTO is the reference frequency FREF for the fractional-N synthesizer. When
designing the system in terms of receiving and transmitting frequency offset the accuracy of the
crystal and XTO have to be considered.
The synthesizer can adjust the local oscillator frequency for the initial frequency error in fXTO.
This is done at nominal supply voltage and temperature with the control registers 2 and 3 (see
Table 12-7 on page 38 and Table 12-10 on page 39). The remaining local oscillator tolerance at
nominal supply voltage and temperature is then < ±0.5 ppm. The XTO’s gm has very low influence of less than ±2 ppm on the frequency at nominal supply voltage and temperature.
In a single channel system less than ±150 ppm should be corrected to avoid that harmonics of
the CLK output disturb the receive mode. If the CLK is not used, or carefully layouted on the
application PCB (as needed for multi channel systems), more than ±150 ppm can be
compensated.
The additional XTO pulling is only ±2 ppm, overtemperature and supply voltage. The XTAL versus temperature and its aging is then the main source of frequency error in the local oscillator.
The XTO frequency depends on XTAL properties and the load capacitances CL1, 2 at pin XTAL1
and XTAL2. The pulling of fXTO from the nominal fXTAL is calculated using the following formula:
Cm
C LN – C L
6
P = -------- × ------------------------------------------------------------- × 10 ppm.
2
( C 0 + C LN ) × ( C 0 + C L )
Cm is the crystal's motional, C0 the shunt and CLN the nominal load capacitance of the XTAL
found in its datasheet. CL is the total actual load capacitance of the crystal in the circuit and consists of CL1 and CL2 in series connection.
27
4829C–RKE–09/05
Figure 9-1.
XTAL with Load Capacitances
Crystal equivalent circuit
XTAL
CL1
C0
Lm
CL2
Cm
Rm
CL= CL1 × CL2/(CL1 + CL2)
With C m ≤ 14 fF, C 0 ≥ 1.5 pF, C LN = 9 pF and C L = 7.4 pF to 10.6 pF the pulling amounts to
P ≤ ±100 ppm and with Cm ≤ 7 fF, C0 ≥ 1.5 pF, CLN = 9 pF and CL = 7.4 pF to 10.6 pF the pulling
is P ≤ ±50 ppm.
Since typical crystals have less than ±50 ppm tolerance at 25°C, the compensation is not critical
and can, in both cases, be done with the ±150 ppm.
C0 of the XTAL has to be lower than CLmin/2 = 3.7 pF for a Pierce oscillator type in order to not
enter the steep region of pulling versus load capacitance where there is a risk of an unstable
oscillation.
To ensure proper start-up behavior the small signal gain, and thus the negative resistance provided by this XTO at start is very large. For example oscillation starts up, even in worst case,
with a crystal series resistance of 1.5 kΩ at C0 ≤2.2 pF with this XTO. The negative resistance is
approximately given by
⎧ Z1 × Z3 + Z2 × Z3 + Z1 × Z2 × Z3 × gm ⎫
Re {Z XTOcore } = Re ⎨ ------------------------------------------------------------------------------------------------------ ⎬
Z1 + Z2 + Z3 + Z1 × Z2 × gm
⎩
⎭
with Z1, Z2 as complex impedances at pin XTAL1 and XTAL2 hence
Z1 = –j/(2 × π × fXTO × CL1) + 5Ω and Z2 = –j/(2 × π × fXTO × CL2) + 5Ω.
Z3 consists of crystals C0 in parallel with an internal 110 kΩ resistor hence
Z3 = –j/(2 × π × fXTO × C0) /110 kΩ, gm is the internal transconductance between XTAL1 and
XTAL2 with typically 19 ms at 25°C.
With fXTO = 13.5 MHz, gm = 19 ms, CL = 9 pF, C0 = 2.2 pF this results in a negative resistance of
about 2 kΩ. The worst case for technological, supply voltage and temperature variations is then
for C0 ≤ 2.2 pF always higher than 1.5 kΩ.
Due to the large gain at start, the XTO is able to meet a very low start-up time. The oscillation
start-up time can be estimated with the time constant τ .
2
τ = ----------------------------------------------------------------------------------------------------------2
2
4 × π × f m × C m × ( Re ( Z XTOcore ) + R m )
After 10 τ to 20 τ , an amplitude detector detects the oscillation amplitude and sets XTO_OK to
High if the amplitude is large enough. This activates the CLK output if CLK_ON and CLK_EN in
control register 3 are High (see Table 12-12 on page 39). Note that the necessary conditions of
the DVCC voltage also have to be fulfilled (see Figure 9-2 on page 29 and Figure 10-1 on page
31).
28
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
To save current in IDLE and Sleep mode, the load capacitors partially are switched off in this
modes with S1 and S2 seen in Figure 9-2 on page 29.
It is recommended to use a crystal with C m = 3.0 fF to 7.0 fF, C LN = 9 pF, R m < 120Ω and
C0 = 1.0 pF to 2.2 pF.
Lower values of Cm can be used, this increases slightly the start-up time. Lower values of C0 or
higher values of Cm (up to 15 fF) can also be used, this has only little influence to pulling.
Figure 9-2.
XTO Block Diagram
XTAL1
XTAL2
CLK
&
fXTO
8 pF
S1
10 pF
CL1
CL2
10 pF
CLK_EN
(Control
register 3)
8 pF
S2
In IDLE mode and during sleep mode (RX_Polling) the switches
S1 and S2 are open.
DVCC_OK
(from power
supply)
Divider
/3
Amplitude
detector
CLK_ON
(Control
register 3)
XTO_OK
(to reset logic)
Divider
/16
fDCLK
Divider
/1
/2
/4
/8
/16
fXDCLK
Baud1
Baud0
XLim
To find the right values used in the control registers 2 and 3 (see Table 12-7 on page 38 and
Table 12-10 on page 39) the relationship between fXTO and the fRF is shown in Table 9-1. To
determine the right content, the frequency at pin CLK, as well as the output frequency at
RF_OUT in ASK mode can be measured, than the FREQ value can be calculated according to
Table 9-1 so that fRF is exactly the desired radio frequency.
29
4829C–RKE–09/05
Table 9-1.
Calculation of fRF
CREG1
Bit(4)
FS
fXTO (MHz)
Frequency
(MHz)
Pin 6
433_N868
fTX_FSK_L =
fTX_FSK_L(FD)
fTX_FSK_H
315.0
AVCC
1
12.73193
FREQ + 24,5
f XTO × ⎛ 24, 5 + ----------------------------------⎞
⎝
16384 ⎠
fRF 18.65 kHz
fRF +
18.65 kHz
fRF +
208.23 kHz
777.1 Hz
868.3
GND
0
13.41180
FREQ + 24,5
f XTO × ⎛ 64, 5 + ----------------------------------⎞
⎝
16384 ⎠
fRF 19.64 kHz
fRF +
19.64 kHz
fRF +
206.26 kHz
818.6 Hz
433.92
AVCC
0
13.25311
FREQ + 24,5
f XTO × ⎛ 32, 5 + ----------------------------------⎞
⎝
16384 ⎠
fRF 19.41 kHz
fRF +
19.41 kHz
fRF +
203.74 kHz
808.9 Hz
fRF = fTX_ASK = fRX
Frequency
fTX_FSK_H(FD) Resolution
The variable FREQ depends on the bit PLL_MODE in control register 1 and the parameter
FREQ2 and FREQ3, which are defined by the bits FR0 to FR12 in control register 2 and 3 and is
calculated as follows:
FREQ = FREQ2 + FREQ3
Care must be taken with the harmonics of the CLK output signal fCLK, as well as to the harmonics
produced by an microprocessor clocked with it, since these harmonics can disturb the reception
of signals if they get to the RF input. In a single channel system the use of FREQ = 3803 to 4053
ensures that harmonics of this signal do not disturb the receive mode. In a multichannel system
the CLK signal can either be not used or carefully layouted on the application PCB. The supply
voltage of the microcontroller must also be carefully blocked in a multichannel system.
9.1
Pin CLK
Pin CLK is an output to clock a connected microcontroller. The clock frequency fCLK is calculated
as follows:
f XTO
f CLK = ---------3
The signal at CLK output has a nominal 50% duty cycle.
If the bit CLK_EN in control register 3 is set to 0, the clock is disabled permanently.
If the bit CLK_EN is set to 1 and bit CLK_ON (control register 3) is set to 0, the clock is disabled
as well. If bit CLK_ON is set to 1 and thus the clock is enabled if the Bit-check is ok (RX, RX Polling, FD mode (Slave)), an event on pin N_PWR_ON occurs or the bit Power_On in the status
register is 1.
Figure 9-3.
Clock Timing
DVCC
VDVCC = 1.6 V (typ)
CLK
CLK_EN
(Control Register 3)
CLK_ON
(Control Register 3)
30
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
9.2
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry is derived from one clock. According to Figure 9-2 on
page 29, this clock cycle TDCLK is derived from the crystal oscillator (XTO) in combination with a
divider.
f XTO
f DCLK = ---------16
TDCLK controls the following application relevant parameters:
• Timing of the polling circuit including bit-check
• TX baud rate
The clock cycle of the Bit-check and the TX baud rate depends on the selected baud-rate range
(BR_Range) which is defined in control register 6 (see Table 12-19 on page 41) and XLim which
is defined in control register 4 (see Table 12-16 on page 40). This clock cycle TXDCLK is defined
by the following formulas for further reference:
BR_Range ⇒
BR_Range 0: TXDCLK = 8 ×
BR_Range 1: TXDCLK = 4 ×
BR_Range 2: TXDCLK = 2 ×
BR_Range 3: TXDCLK = 1 ×
TDCLK ×
TDCLK ×
TDCLK ×
TDCLK ×
XLim
XLim
XLim
XLim
10. Power Supply
Figure 10-1. Power Supply
VS1
SW_AVCC
IN
VS2
OUT
V_REG
3.25 V typ.
VSINT
EN
≥1
PWR_ON
N_PWR_ON
FF1
S
≥1
OFFCMD
(Command via SPI)
DVCC_OK
XTO_OK
AVCC
&
Q
R
S
0
0
1
1
R
0
1
0
1
Q
no change
0
1
1
DVCC
SW_DVCC
V_Monitor
(1.6 V typ.)
DVCC_OK
(to XTO and
reset logic)
31
4829C–RKE–09/05
The supply voltage range of the ATA5823/ATA5824 is 2.15V to 3.6V or 4.4V to 5.25V.
Pin VS1 is the supply voltage input for the range 2.15V to 3.6V and is used in battery applications using a single lithium 3V cell. Pin VS2 is the voltage input for the range 4.4V to 5.25V (car
applications), in this case the voltage regulator V_REG regulates VS1 to typically 3.25V. If the
voltage regulator is active, a blocking capacitor of 2.2 µF has to be connected to VS1.
Pin VSINT is the voltage input for the Microcontroller_Interface and must be connected to the
power supply of the microcontroller. The voltage range of VVSINT is 2.25V to 5.25V (see Figure
10-5 and Figure 10-6 on page 35).
AVCC is the internal operation voltage of the RF transceiver and is feed via the switch
SW_AVCC by VS1. AVCC must be blocked on pin AVCC with a 68 nF capacitor (see Figure 3-1
on page 6, Figure 4-1 on page 7, Figure 5-1 on page 8 and Figure 6-1 on page 9).
DVCC is the internal operation voltage of the digital control logic and is fed via the switch
SW_DVCC by VS1. DVCC must be blocked on pin DVCC with 68 nF (see Figure 3-1 on page 6,
Figure 4-1 on page 7, Figure 5-1 on page 8 and Figure 6-1 on page 9).
Pin PWR_ON is an input to switch on the transceiver (active high).
Pin N_PWR_ON is an input for a push button and can also be used to switch on the transceiver
(active low).
For current consumption reasons it is recommended to set N_PWR_ON to GND only temporarily. Otherwise an additional current flows because of a 50 kΩ pull-up resistor.
A voltage monitor generates the signal DVCC_OK if DVCC ≥ 1.6V typically.
Figure 10-2. Flow Chart Operation Modes
OFF command and
pin PWR_ON = 0 and
pin N_PWR_ON = 1
OFF Mode
AVCC = OFF
DVCC = OFF
Pin PWR_ON = 1 or
pin N_PWR_ON = 0
OPM2 OPM1 OPM0
0
0
1 TX mode
0
1
0 RX polling mode
0
1
1 RX mode
1
0
1 FD mode (master)
1
1
1 FD mode (slave)
TX Mode
RX Polling
Mode
OPM2 = 0 and OPM1 = 0 and
OPM0 = 0
IDLE Mode
AVCC = VS1
DVCC = VS1
RX Mode
FD Mode
(Slave)
FD Mode
(Master)
AVCC = VS1; DVCC = VS1
32
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
10.1
OFF Mode
After connecting the power supply (battery) to pin VS1 and/or VS2 and VSINT, the transceiver is
in OFF mode. In OFF mode AVCC and DVCC are disabled, resulting in very low power consumption (IS_OFF is typically ≤10 nA in the key fob application Figure 3-1 on page 6 and Figure
5-1 on page 8 and ≤0.5 µA in the car application Figure 4-1 on page 7 and Figure 6-1 on page 9).
In OFF mode the transceiver is not programmable via the 4-wire serial interface.
10.2
IDLE Mode
In IDLE mode AVCC and DVCC are connected to the battery voltage (VS1).
From OFF mode the transceiver changes to IDLE mode if pin PWR_ON is set to 1 or pin
N_PWR_ON is set to 0. This state transition is indicated by an interrupt at pin IRQ and the status
bits Power_On = 1 or N_Power_On = 1.
In IDLE mode the RF transceiver is disabled and the power consumption IIDLE_VS1,2 is about
270 µA (CLK output OFF VS1 = VS2 = 3V). The exact value of this current is strongly dependent
on the application and the exact operation mode, therefore check the section “Electrical Characteristics” for the appropriate application case.
Via the 4-wire serial interface a connected microcontroller can program the required parameter
and enable the TX, RX polling, RX or FD mode.The transceiver can be set back to OFF mode by
an OFF command via the 4-wire serial interface (the input level of pin PWR_ON must be 0 and
pin N_PWR_ON = 1 before writing the OFF command)
Table 10-1.
10.3
Control Register 1
OPM2
OPM1
OPM0
Function
0
0
0
IDLE mode
Reset Timing and Reset Logic
If the transceiver is switched on (OFF mode to IDLE mode) DVCC and AVCC are ramping up as
illustrated in Figure 10-3. The internal signal DVCC_RESET resets the digital control logic and
sets the control register to default values. Bit DVCC_RST in the status register is set to 1.
After VDVCC exceeds 1.6V (typically) and the start-up time of the XTO is elapsed, the output
clock at pin CLK is available.
DVCC_RST in the status register is set to 0 if VDVCC exceeds 1.6V, the start-up time of the XTO
is elapsed and the status register is read via the 4-wire serial interface.
If VDVCC drops below 1.6V (typically) and pin N_PWR_ON = 1 and pin PWR_ON = 0 the transceiver switches to OFF mode.
33
4829C–RKE–09/05
Figure 10-3. Reset Timing
1.6 V (typ)
DVCC, AVCC
DVCC_RESET
read status register
DVCC_RST
(Status Register)
VDVCC > 1.6 V and the XTO is running
CLK
IDLE, TX, RX, RX Polling, FD
mode
OFF mode IDLE mode
OFF mode
Figure 10-4. Reset Logic
DVCC_OK
&
DVCC_RESET
XTO_OK
10.4
Battery Application
The supply voltage range is 2.15V to 3.6V.
Figure 10-5. Battery Application
2.15 V to 3.6 V
ATA5823/ATA5824
VS1
VS
Microcontroller
VS2
RF transceiver
microcontroller_Interface
Digital control logic
34
AVCC
DVCC
VSINT
CS
OUT
SCK
OUT
SDI_TMDI
OUT
SDO_TMDO
IN
IRQ
IN
CLK
IN
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
10.5
Car Application
The supply voltage range is 4.4V to 5.25V.
Figure 10-6. Car Application
4.4 V to 5.25 V
ATA5823/ATA5824
VS1
VS
Microcontroller
VS2
AVCC
Digital control logic
DVCC
microcontroller_Interface
RF transceiver
VSINT
CS
OUT
SCK
OUT
SDI_TMDI
OUT
SDO_TMDO
IN
IRQ
IN
CLK
IN
11. Microcontroller Interface
The microcontroller interface is a level converter which converts all internal digital signals which
are referred to the DVCC voltage, into the voltage used by the microcontroller. Therefore, the pin
VSINT can be connected to the supply voltage of the microcontroller in the case the microcontroller has another supply voltage than the ATA5823/ATA5824.
12. Digital Control Logic
12.1
Register Structure
The configuration of the transceiver is stored in RAM cells. The RAM contains a 16 × 8-bit
TX/RX data buffer and a 8 × 8-bit Control register and is write and readable via a 4-wire serial
interface (CS, SCK, SDI_TMDI, SDO_TMDO).
The 1 × 8-bit status register is not part of the RAM and is readable via the 4-wire serial interface.
The RAM and the status information is stored as long as the transceiver is in any active mode
(DVCC = VS1) and gets lost if the transceiver is in the OFF mode (DVCC = OFF).
After the transceiver is turned on via pin PWR_ON = High or pin N_PWR_ON = Low the control
registers are in the default state.
35
4829C–RKE–09/05
Figure 12-1. Register Structure
LSB
MSB
TX/RX Data Buffer:
16 × 8 Bit
IR1
IR0
PLL_
MODE
FS
FR6
FR5
FR4
FR3
FR2
FR1
FR12
FR11
FR10
FR9
FR8
FR7
T_
MODE
Control Register 1 (ADR 0)
FR0
P_
MODE
Control Register 2 (ADR 1)
CLK_
EN
CLK_
ON
Control Register 3 (ADR 2)
ASK_
Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 XSleep XLim
NFSK
Control Register 4 (ADR 3)
OPM2 OPM1 OPM0
BitCh
k1
BitCh
k0
Lim_
min5
Lim_
min4
Lim_
min3
Lim_
min2
Lim_
min1
Lim_
min0
Control Register 5 (ADR 4)
Baud
1
Baud
0
Lim_
max5
Lim_
max4
Lim_
max3
Lim_
max2
Lim_
max1
Lim_
max0
Control Register 6 (ADR 5)
TX5
TX4
TX3
TX2
TX1
TX0
Control Register 7 (ADR 6)
FE_ PWS PWS
MODE ELECT ET4
PWS
ET3
PWS
ET2
PWS
ET1
PWS
ET0
Control Register 8 (ADR 7)
POUT_ POUT_
SELECT DATA
-
N_
Power
_On
-
-
-
-
Power DVCC
_On _RST
-
Status Register (ADR 16)
- = Don't care
36
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
12.2
TX/RX Data Buffer
The TX/RX data buffer is used to handle the data transfer during RX and TX operations.
12.3
Control Register
To use the transceiver in different applications the transceiver can be configured by a microcontroller connected via the 4-wire serial interface.
12.3.1
Control Register 1 (ADR 0)
Table 12-1.
Control Register 1 (Function of Bit 7 and Bit 6 in RX Mode)
IR1
IR0
0
0
Pin IRQ is set to 1 if 1 received byte is in the TX/RX data buffer or a receiving error
occurred
0
1
Pin IRQ is set to 1 if 2 received bytes are in the TX/RX data buffer or a receiving error
occurred
1
0
Pin IRQ is set to 1 if 4 received bytes are in the TX/RX data buffer or a receiving error
occurred (default)
1
1
Pin IRQ is set to 1 if 12 received bytes are in the TX/RX data buffer or a receiving error
occurred
Table 12-2.
Function (RX Mode)
Control Register 1 (Function of Bit 7 and Bit 6 in TX Mode)
IR1
IR0
Function (TX Mode)
0
0
Pin IRQ is set to 1 if 1 byte still is in the TX/RX data buffer or the TX data buffer is empty
0
1
Pin IRQ is set to 1 if 2 bytes still are in the TX/RX data buffer or the TX data buffer is
empty
1
0
Pin IRQ is set to 1 if 4 bytes still are in the TX/RX data buffer or the TX data buffer is
empty (default)
1
1
Pin IRQ is set to 1 if 12 bytes still are in the TX/RX data buffer or the TX data buffer is
empty
The Bits IR0 and IR1 have no function in FD mode
Note:
Table 12-3.
PLL_MODE
Control Register 1 (Function of Bit 5)
Function
0
Adjustable range of FREQ: 3072 to 4095 (default), see Table 12-10 on page 39
1
Adjustable range of FREQ: 0 to 8191, see Table 12-11 on page 39
Table 12-4.
Control Register 1 (Function of Bit 4)
FS
Function (RX Mode, TX Mode, FD Mode)
0
Selected frequency 433/868 MHz (default)
1
Selected frequency 315 MHz
37
4829C–RKE–09/05
Control Register 1 (Function of Bit 3, Bit 2 and Bit 1)
Table 12-5.
OPM2
OPM1
OPM0
0
0
0
IDLE mode (default)
0
0
1
TX mode
0
1
0
RX polling mode
0
1
1
RX mode
1
0
0
-
1
0
1
Full-duplex mode (Master)
1
1
0
-
1
1
1
Full-duplex mode (Slave)
Control Register 1 (Function of Bit 0)
Table 12-6.
T_MODE
12.3.2
Function
0
TX and RX function via TX/RX data buffer (default)
1
Transparent mode, TX/RX data buffer disabled, TX modulation data stream via pin
SDI_TMDI, RX modulation data stream via pin SDO_TMDO
Control Register 2 (ADR 1)
Control Register 2 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2 and Bit 1)
Table 12-7.
FR6
26
FR5
25
FR4
24
FR3
23
FR2
22
FR1
21
FR0
20
0
0
0
0
0
0
0
FREQ2 = 0
0
0
0
0
0
0
1
FREQ2 = 1
.
.
.
.
.
.
.
1
0
1
0
1
0
0
.
.
.
.
.
.
.
1
Note:
P_MODE
FREQ2 = 84 (default)
Control Register 2 (Function of Bit 0 in RX mode)
Function (RX mode)
0
Pin IRQ is set to 1 if the Bit-check is successful (default)
1
No effect on pin IRQ if the Bit-check is successful
Table 12-9.
P_MODE
0
1
Note:
Function
1
1
1
1
1
1
FREQ2 = 127
LSB’s
(total
13
bits),
frequency
trimming,
resolution
of fRF is fXTO/16384 which is
Tuning of fRF
approximately 800 Hz (see section “XTO”, Table 9-1 on page 30)
Table 12-8.
38
Function
Control Register 2 (Function of Bit 0 in TX mode)
Function (TX mode)
Manchester modulator on (default)
Manchester modulator off (NRZ mode)
Bit P_MODE has no function in FD mode
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
12.3.3
Control Register 3 (ADR 2)
Table 12-10. Control Register 3 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2 if Bit
PLL_MODE = 0 (in Control Register 1)
FR12
212
FR11
211
FR10
210
FR9
29
FR8
28
FR7
27
X
X
X
0
0
0
FREQ3 = 3072
X
X
X
0
0
1
FREQ3 = 3200
X
X
X
0
1
0
FREQ3 = 3328
X
X
X
0
1
1
FREQ3 = 3456
X
X
X
1
0
0
FREQ3 = 3584
X
X
X
1
0
1
FREQ3 = 3712
X
X
X
1
1
0
FREQ3 = 3840(default)
1
1
1
FREQ3 = 3968
X
Note:
X
X
Tuning of fRF MSB’s
Function
Table 12-11. Control Register 3 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2 if Bit
PLL_MODE = 1 (in Control Register 1)
FR12
212
FR11
211
FR10
210
FR9
29
FR8
28
FR7
27
0
0
0
0
0
0
FREQ3 = 0
0
0
0
0
0
1
FREQ3 = 128
0
0
0
0
1
0
FREQ3 = 256
.
.
.
.
.
.
.
0
1
1
1
1
0
FREQ3 = 3840 (default)
Function
.
.
.
.
.
.
.
1
1
1
1
1
0
FREQ3 = 7936
1
1
1
FREQ3 = 8064
1
Note:
1
1
Tuning of fRF MSB’s
Table 12-12. Control Register 3 (Function of Bit 1 and Bit 0)
CLK_EN
CLK_ON
0
X
Clock output off (pin CLK)
0
Clock output off (pin CLK). Clock switched on by an event:
- Bit-check ok or
- event on pin N_PWR_ON or
- bit Power_On in the status register is 1
1
1
Note:
Function (RX Mode, TX Mode, FD Mode)
1
Clock output on (default)
Bit CLK_ON is set to 1 if the Bit-check is ok (RX_Polling, RX mode), an event at pin
N_PWR_ON occurs or the bit Power_On in the status register is 1.
39
4829C–RKE–09/05
12.3.4
Control Register 4 (ADR 3)
Table 12-13. Control Register 4 (Function of Bit 7)
ASK_NFSK
Function (TX Mode, RX Mode)
0
1
Note:
FSK mode (default)
ASK mode
Bit ASK_NFSK has no function in FD mode
Table 12-14. Control Register 4 (Function of Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2)
Sleep4
24
Sleep3
23
Sleep2
22
Sleep1
21
Sleep0
20
Function (RX Mode)
Sleep
(TSleep = Sleep × 1024 × TDCLK × XSleep)
0
0
0
0
0
0
0
0
0
0
1
1
.
.
.
.
.
1
1
0
0
0
.
.
.
.
.
1
Note:
24
(TSleep = 24× 1024 × TDCLK × XSleep)
(default)
1
1
1
1
Bits Sleep0 ... Sleep4 have no function in TX mode and FD mode
31
Table 12-15. Control Register 4 (Function of Bit 1)
XSleep
0
1
Note:
Function
XSleep = 1; extended TSleep off (default)
XSleep = 8; extended TSleep on
Bit XSleep has no function in TX mode and FD mode
Table 12-16. Control Register 4 (Function of Bit 0)
XLim
0
1
Note:
12.3.5
Function
XLim = 1; extended TLim_min, TLim_max off (default)
XLim = 2; extended TLim_min, TLim_max on
Bit XLim has no function in TX mode and FD mode
Control Register 5 (ADR 4)
Table 12-17. Control Register 5 (Function of Bit 7 and Bit 6)
BitChk1
BitChk0
0
0
NBit-check = 0 (0 bits checked during bit-check)
0
1
NBit-check = 3 (3 bits checked during bit-check) (default)
1
0
NBit-check = 6 (6 bits checked during bit-check)
1
Note:
40
Function
1
NBit-check = 9 (9 bits checked during bit-check)
Bits BitChk0 and BitChk1 have no function in TX mode and FD mode Master
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
Table 12-18. Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0)
Lim_min5
25
Lim_min4
24
Lim_min3
23
Lim_min2
22
Lim_min1
21
Lim_min0
20
Function (RX Mode, FD Mode Slave)
Lim_min
(Lim_min < 10 are not Applicable)
(TLim_min = Lim_min × TXDCLK)
0
0
1
0
1
0
10
0
0
1
0
1
1
11
(TLim_min = 11 × TXDCLK)
(default)
.
.
.
.
.
.
1
1
1
1
1
1
63
Bits Lim_min0 to Lim_min5 have no function in TX mode and FD mode Master.
12.3.6
Control Register 6 (ADR 5)
Table 12-19. Control Register 6 (Function of Bit 7 and Bit 6)
Baud1
Baud0
Function (RX Mode, TX Mode, FD Mode)
0
0
Baud-rate range 0 (B0) 1.0 kBaud to 2.5 kBaud;
TXDCLK = 8 × TDCLK × XLim
0
1
Baud-rate range 1 (B1) 2.0 kBaud to 5.0 kBaud;
TXDCLK = 4 × TDCLK × XLim
Baud-rate in FD mode = 1 / (168 × TDCLK)
1
0
Baud-rate range 2 (B2) 4.0 kBaud to 10.0 kBaud;
TXDCLK = 2 × TDCLK × XLim (default)
1
1
Baud-rate range 3 (B3) 8.0 kBaud to 20.0 kBaud;
TXDCLK = 1 × TDCLK × XLim
Note that the receiver is not working with >10 kBaud in ASK mode
Table 12-20. Control Register 6 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0)
Lim_max5
25
Lim_max4
24
Lim_max3
23
Lim_max2
22
Lim_max1
21
Lim_max0
20
Function (RX Mode, FD Mode Slave)
Lim_max
(Lim_max < 12 are not Applicable)
(TLim_max = (Lim_max - 1) × TXDCLK)
0
0
1
1
0
0
12
0
0
1
1
0
1
13
.
.
.
.
.
.
1
0
0
0
0
0
.
.
.
.
.
.
1
Note:
1
1
1
1
1
Bits Lim_max0 to Lim_max5 have no function in TX mode and FD mode Master
32
(TLim_max = (32 – 1) × TXDCLK)
(default)
63
41
4829C–RKE–09/05
12.3.7
Control Register 7 (ADR 6)
Table 12-21. Control Register 7 (Function of Bit 7 and Bit 6)
POUT_SELECT
POUT_DATA
0
0
Function (RX Mode, TX Mode, FD Mode)
Output level on pin POUT = 0 (default)
0
1
Output level on pin POUT = 1
1
X
Output level on pin POUT = N_RX_ACTIVE(1)
1. IDLE, TX, FD mode: N_RX_ACTIVE = 1
RX mode: N_RX_ACTIVE = 0
Note:
Table 12-22. Control Register 7(Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0)
TX5
25
TX4
24
TX3
23
TX2
22
TX1
21
TX0
20
Function (TX Mode)
TX
(TX < 10 are not Applicable)
(TX_Baudrate = 1/(TX + 1) × TXDCLK × 2)
0
0
1
0
1
0
10
0
0
1
0
1
1
11
.
.
.
.
.
.
0
1
0
1
0
0
.
.
.
.
.
1
Note:
12.3.8
1
1
1
1
Bits TX0 to TX5 have no function in RX mode and FD mode
20
(TX_Baudrate = 1/(20 + 1) × TXDCLK × 2)
(default)
.
1
63
Control Register 8 (ADR 7)
Table 12-23. Control Register 8 (Function of Bit 6)
FE_mode
Function
0
For future use
1
Bit for internal use, must always set to 1 (default)
Table 12-24. Control Register 8 (Function of Bit 5)
PWSELECT
42
Function (TX Mode, FD Mode)
0
RPWSET = 140Ω typically in TX-mode and as defined by the bits PWSET0 to PWSET4
in FD mode (default)
1
RPWSET as defined by the bits PWSET0 to PWSET4
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
Table 12-25. Control Register 8 (Function of Bit 4, Bit 3, Bit 2, Bit 1, Bit 0)
PWSET4
24
PWSET3
23
PWSET2
22
PWSET1
21
PWSET0
20
Function (TX Mode, FD Mode)
(SETPWR: Programmable internal
resistor to reduce the output power
in FD and TX mode)
PWSET
SETPWR = 800Ω + (31 – PWSET)
× 3 kΩ (typically)
0
0
0
0
0
0
0
0
0
0
1
1
.
.
.
.
.
1
0
0
0
0
.
.
.
.
.
1
1
1
1
0
30
1
1
1
1
1
31
16 (default)
SETPWR = 800Ω + (31 – 16) ×
3 kΩ (typically)
Normally the SETPWR resistor at pin 19 is used in full-duplex mode to decrease the output
power until the level at RF_IN is low enough for reception of signals (PWSELECT = 0). With
PWSELECT = 1 this resistor can also be used in normal half-duplex TX operation to adjust the
output power for production tolerances.
12.3.9
Status Register (ADR 16)
The status register indicates the current status of the transceiver and is readable via the 4-wire
serial interface. Setting Power_On or an event on N_Power_On is indicated by an IRQ.
Reading the status register resets the bits Power_On, DVCC_RST and the IRQ.
Table 12-26. Status Register
Status Bit
N_Power_On
Function
Status of pin N_PWR_On
Pin N_PWR_ON = 0 → N_Power_On = 1
Pin N_PWR_ON = 1 → N_Power_On = 0
(Figure 12-3 on page 45)
Power_On
Indicates that the transceiver was woken up by pin PWR_ON (rising edge on
pin PWR_ON). During Power_On = 1, the bit CLK_ON in control register 3 is
set to 1 (Figure 12-4 on page 46).
DVCC_RST
DVCC_RST is set to 1 if the supply voltage of the RAM (VDVCC) was too low and the
information in the RAM may be lost.
DVCC_RST = 0 → supply voltage of the RAM ok
DVCC_RST = 1 → supply voltage of the RAM was too low (typically VDVCC < 1.6V)
If the transceiver changes from OFF mode to IDLE mode, DVCC_RST will be set to 1.
Reading the Status register resets DVCC_RST to 0.
43
4829C–RKE–09/05
12.4
Pin N_PWR_ON
To switch the transceiver from OFF to IDLE mode, pin N_PWR_ON must be set to 0 (maximum
0.2 × VVS2) for at least TN_PWR_ON_IRQ (see Figure 12-2). The transceiver recognizes the negative edge and switches on DVCC and AVCC.
If VDVCC exceeds 1.6V (typically) and the XTO is settled, the digital control logic is active and
sets the status bit N_Power_On to 1, an interrupt is issued (TN_PWR_ON_IRQ) and the output clock
on pin CLK is available.
If the level on pin N_PWR_ON was set to 1 before the interrupt is issued, the transceiver stays in
OFF mode.
Note:
It is not possible to set the transceiver to OFF-mode by setting pin N_PWR_ON to 1. If pin
N_PWR_ON is not used, it should be left open because of the internal pull-up resistor
Figure 12-2. Timing Pin N_PWR_ON, Status Bit N_Power_On
N_PWR_ON
DVCC, AVCC
1.6 V (typ)
CLK
TN_PWR_ON_IRQ
N_Power_On
(Status Register)
IRQ
OFF Mode
IDLE Mode
If the transceiver is in any of the active modes (IDLE, TX, RX, RX_Polling, FD), an integrated
debounce logic is active. If there is an event on pin N_PWR_ON, a debounce counter is set to 0
(T = 0) and started. The status is updated, an interrupt is issued and the debounce counter is
stopped after reaching the counter value T = 8195 × TDCLK.
An event on N_PWR_ON before reaching T = 8195 × TDCLK stops the debounce counter.
While the debounce counter is running, the bit CLK_ON in control register 3 is set to 1.
The interrupt is deleted after reading the status register or executes the command Delete_IRQ.
If pin N_PWR_ON is not used, it can be left open because of an internal pull-up resistor (typically 50 kΩ).
44
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
Figure 12-3. Timing Flow Pin N_PWR_ON, Status Bit N_Power_On
IDLE Mode or
TX Mode or
RX Polling Mode or
RX Mode or
FD Mode
Event on pin
N_PWR_ON ?
N
Y
T=0
Start debounce counter
Event on pin
N_PWR_ON ?
N
Y
T = 8195 × TDCLK
?
N
Y
Pin N_PWR_ON
=0?
N
Y
Stop debounce counter
12.5
Stop debounce counter
N_Power_On = 1;
IRQ = 1
Stop debounce counter
N_Power_On = 0;
IRQ = 1
Pin PWR_ON
To switch the transceiver from OFF to IDLE mode, pin PWR_ON must set to 1 (minimum
0.8 × VVSINT) for at least TPWR_ON (see Figure 12-4 on page 46). The transceiver recognizes the
positive edge and switches on DVCC and AVCC.
If VDVCC exceeds 1.6V (typically) and the XTO is settled, the digital control logic is active and
sets the status bit Power_On to 1, an interrupt is issued (TPWR_ON_IRQ_1) and the output clock on
pin CLK is available.
If the level on pin PWR_ON was set to 0 before the interrupt is issued, the transceiver stays in
OFF mode.
If the transceiver is in any of the active modes (IDLE, RX, RX_Polling, TX, FD), a positive edge
on pin PWR_ON sets Power_On to 1 (after TPWR_ON_IRQ_2). The state transition Power_On 0 →1
generates an interrupt. If Power_On is still 1 during the positive edge on pin PWR_ON, no interrupt is issued. Power_On and the interrupt is deleted after reading the status register.
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4829C–RKE–09/05
During Power_On = 1, the bit CLK_EN in control register 3 is set to 1.
Note:
It is not possible to set the transceiver to OFF mode by setting pin PWR_ON to 0. If pin PWR_ON
is not used, it must be connected to GND.
Figure 12-4. Timing Pin PWR_ON, Status Bit Power_On
TPWR_ON > TPWR_ON_IRQ_1
TPWR_ON > TPWR_ON_IRQ_2
TPWR_ON_IRQ_1
TPWR_ON_IRQ_2
PWR_ON
DVCC, AVCC
1.6 V (typ)
CLK
Power_On
(Status Register)
IRQ
OFF Mode
12.6
IDLE Mode
IDLE, RX, RX Polling, TX, FD Mode
DVCC_RST
The status bit DVCC_RST is set to 1 if the voltage on pin DVCC VDVCC drops under 1.6V
(typically).
DVCC_RST is set to 0 if VDVCC exceeds 1.6V (typically) and the status register is read via the
4-wire serial interface (see Figure 10-3 on page 34).
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Figure 12-5. Timing Flow Status Bit DVCC_RST
IDLE, TX, RX, RX Polling,
FD Mode
VDVCC < 1.6 V (typ)
?
N
Y
Pin PWR_ON = 1
or pin N_PWR_ON = 0
?
OFF_Mode
N
Y
DVCC_RST = 1;
Read Status Register
13. Transceiver Configuration
The configuration of the transceiver takes place via a 4-wire serial interface (CS, SCK,
SDI_TMDI, SDO_TMDO) and is organized in 8-bit units. The configuration is initiated with a 8-bit
command. While shifting the command into pin SDI_TMDI, the number of bytes in the TX/RX
data buffer are available on pin SDO_TMDO. The read and write commands are followed by one
or more 8-bit data units. Each 8-bit data transmission begins with the MSB.
13.1
Command: Read TX/RX Data Buffer
During a RX operation the user can read the received bytes in the TX/RX data buffer
successively.
Figure 13-1. Read TX/RX Data Buffer
MSB
LSB
MSB
LSB
MSB
LSB
SDI_TMDI
Command: Read TX/RX Data Buffer
X
X
SDO_TMDO
No. Bytes in the TX/RX Data Buffer
RX Data Byte 1
RX Data Byte 2
SCK
CS
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13.2
Command: Write TX/RX Data Buffer
During a TX operation the user can write the bytes in the TX/RX data buffer successively.
Figure 13-2. Write TX/RX Data Buffer
MSB
LSB
MSB
LSB
MSB
LSB
SDI_TMDI
Command: Write TX/RX Data Buffer
TX Data Byte 1
TX Data Byte 2
SDO_TMDO
No. Bytes in the TX/RX Data Buffer
Write TX/RX Data Buffer
TX Data Byte 1
SCK
CS
13.3
Command: Read Control/Status Register
The control and status registers can be read individually or successively.
Figure 13-3. Read Control/Status Register
MSB
SDI_TMDI
SDO_TMDO
LSB
MSB
LSB
MSB
LSB
Command: Read C/S Register X
Command: Read C/S Register Y
Command: Read C/S Register Z
No. Bytes in the TX/RX Data Buffer
Data C/S Register X
Data C/S Register Y
SCK
CS
13.4
Command: Write Control Register
The control registers can be written individually or successively.
Figure 13-4. Write Control Register
MSB
LSB
MSB
LSB
MSB
LSB
SDI_TMDI
Command: Write Control Register X
Data Control Register X
Command: Write Control Register Y
SDO_TMDO
No. Bytes in the TX/RX Data Buffer
Write Control Register X
Data Control Register X
SCK
CS
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13.5
Command: OFF Command
If the input level on pin PWR_ON is low and on the key input N_PWR_ON is high, the OFF command sets the transceiver to the OFF mode.
Figure 13-5. OFF Command
MSB
SDI_TMDI
SDO_TMDO
LSB
Command: OFF Command
No. Bytes in the TX/RX Data Buffer
SCK
CS
13.6
Command: Delete IRQ
The delete IRQ command sets pin IRQ to low.
Figure 13-6. Delete IRQ
MSB
SDI_TMDI
SDO_TMDO
LSB
Command: Delete IRQ
No. Bytes in the TX/RX Data Buffer
SCK
CS
13.7
Command Structure
The three most significant bits of the command (bit 5 to bit 7) indicates the command type. Bit 0
to bit 4 describes the target address when reading or writing to a control or status register.
Bit 0 to bit 4 in the command Write TX/RX Data Buffer defines the value N (0 ≤ N ≤ 16). The TX
operation only will be started if the number of bytes in the TX buffer ≥ N. This function makes
sure that the datastream will be sent without gaps. The TX operation only will be started if at
least 1 byte are in the TX buffer. This means that N = 0 and N = 1 have the same function.
In all other commands Bit 0 to Bit 4 have no effect and should be set to 0 for compatibility reasons with future products.
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Table 13-1.
Command Structure
MSB
Command
13.8
LSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read TX/RX data buffer
0
0
0
X
X
X
X
X
Write TX/RX data buffer
0
0
1
N4
N3
N2
N1
N0
Read control/status register
0
1
0
A4
A3
A2
A1
A0
Write control register
0
1
1
A4
A3
A2
A1
A0
OFF command
1
0
0
X
X
X
X
X
Delete IRQ
1
0
1
X
X
X
X
X
Not used
1
1
0
X
X
X
X
X
Not used
1
1
1
X
X
X
X
X
4-wire Serial Interface
The 4-wire serial interface consists of the Chip Select (CS), the Serial Clock (SCK), the Serial
Data Input (SDI_TMDI) and the Serial Data Output (SDO_TMDO). Data is transmitted/received
bit by bit in synchronization with the serial clock.
Pin CS_POL defines the active level of the CS:
Table 13-2.
Active Level of the CS
CS_POL
Function
0
CS active high
1
CS active low
When CS is inactive and the transceiver is not in RX transparent mode, SDO_TMDO is in a
high-impedance state.
Pins SCK_POL and SCK_PHA defines the polarity and the phase of the serial clock SCK.
Figure 13-7. Serial Timing SCK_POL = 0, SCK_PHA = 0
TCS_disable
CS
TSCK_setup1
TCS_setup
TCycle
TSCK_setup2
TSCK_hold
SCK X
X
TSetup
SDI_TMDI
X
THold
MSB
X
X
X
TOut_delay
TOut_enable
SDO_TMDO
MSB-1
MSB
TOut_disable
MSB-1
LSB
X can be either ViL or ViH
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Figure 13-8. Serial Timing SCK_POL = 0, SCK_PHA = 1
TCS_disable
CS
TSCK_setup1
SCK
TCS_setup
TCycle
TSCK_hold
TSCK_setup2
X
X
TSetup THold
SDI_TMDI
X
MSB
MSB-1
LSB
X
TOut_delay
TOut_enable
SDO_TMDO
X
TOut_disable
X
MSB
MSB-1
LSB
X can be either ViL or ViH
Figure 13-9. Serial Timing SCK_POL = 1, SCK_PHA = 0
TCS_disable
CS
TSCK_setup1
TCS_setup
TSCK_setup2
TCycle
TSCK_hold
SCK X
X
TSetup THold
SDI_TMDI
X
MSB
X
TOut_enable
MSB-1
X
X
TOut_disable
TOut_delay
SDO_TMDO
MSB-1
MSB
LSB
X can be either ViL or ViH
Figure 13-10. Serial Timing SCK_POL = 1, SCK_PHA = 1
TCS_disable
CS
TSCK_setup1
SCK
TCS_setup
TCycle
X
X
THold
MSB
X
MSB-1
LSB
TOut_delay
TOut_enable
SDO_TMDO
TSCK_hold
X
TSetup
SDI_TMDI
TSCK_setup2
X
X
TOut_disable
MSB
MSB-1
LSB
X can be either ViL or ViH
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14. Operation Modes
14.1
RX Operation
The transceiver is set to RX operation with the bits OPM0, OPM1 and OPM2 in control register 1
Table 14-1.
Control Register 1
OPM2
OPM1
OPM0
Function
0
1
0
RX polling mode
0
1
1
RX mode
The transceiver is designed to consume less than 1 mA in RX operation while being sensitive to
signals from a corresponding transmitter. This is achieved via the polling circuit. This circuits
enable the signal path periodically for a short time. During this time the Bit-check logic verifies
the presence of a valid transmitter signal. Only if a valid signal is detected the transceiver
remains active and transfers the data to the connected microcontroller. This transfer take place
either via the TX/RX data buffer or via the pin SDO_TMDO. If there is no valid signal present the
transceiver is in sleep mode most of the time resulting in low current consumption. This condition
is called RX polling mode. A connected microcontroller can be disabled during this time.
All relevant parameters of the polling logic can be configured by the connected microcontroller.
This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc.
In RX mode the RF transceiver is enabled permanently and the Bit-check logic verifies the presence of a valid transmitter signal. If a valid signal is detected the transceiver transfers the data to
the connected microcontroller. This transfer takes place either via the TX/RX data buffer or via
the pin SDO_TMDO.
14.1.1
RX Polling Mode
If the transceiver is in RX polling mode, it stays in a continuous cycle of three different modes. In
sleep mode, the RF transceiver is disabled for the time period TSleep while consuming low current of IS = IIDLE_X. During the start-up period, TStartup_PLL and TStartup_Sig_Proc, all signal processing
circuits are enabled and settled. In the following Bit-check mode, the incoming data stream is
analyzed bit by bit versus a valid transmitter signal. If no valid signal is present, the transceiver is
set back to sleep mode after the period TBit-check. This period varies check by check as it is a statistical process. An average value for TBit-check is given in the electrical characteristics. During
TStartup_PLL the current consumption is IS = IRX_X. During TStartup_Sig_Proc and TBit-check the current
consumption is I S = I Startup_Sig_Proc_X . The condition of the transceiver is indicated on pin
RX_ACTIVE (see Figure 14-1). The average current consumption in RX polling mode IPoll is different in battery application or car application. To calculate IPoll the index X must be replaced by
VS1,2 in battery application or VS2 in car application (see section “Electrical Characteristics:
General” on page 72).
I IDLE_X × T Sleep + I Startup_PLL_X × T Startup_PLL + I RX_X × ( T Startup_Sig_Proc + T Bitcheck )
I Poll = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------T Sleep + T Startup_PLL + T Startup_Sig_Proc + T Bitcheck
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To save current it is recommended CLK be disabled during RX polling mode. IP does not include
the current of the Microcontroller_Interface IVSINT. If CLK is enabled during the RX polling mode
the current consumption is calculated as follows:
I S_Poll = I Poll + I VSINT
During TSleep, TStartup_PLL and TStartup_Sig_Proc the transceiver is not sensitive to a transmitter signals. To guarantee the reception of a transmitted command the transmitter must start the
telegram with an adequate preburst. The required length of the preburst TPreburst depends on the
polling parameters TSleep, TStartup_PLL, TStartup_Sig_Proc and TBit-check. Thus, TBit-check depends on the
actual bit rate and the number of bits (NBit-check) to be tested.
T Preburst ≥ T Sleep + T Startup_PLL + T Startup_Sig_Proc + T Bitcheck
14.1.2
Sleep Mode
The length of period TSleep is defined by the 5-bit word sleep in control register 4, the extension
factor XSleep defined by the bit XSleep in control register 4 and the basic clock cycle TDCLK. It is calculated to be:
T Sleep = Sleep × 1024 × T DCLK × X Sleep
In US and European applications, the maximum value of TSleep is about 38 ms if XSleep is set to 1
(which is done by setting the bit XSleep in control register 4 to 0). The time resolution is about
1.2 ms in that case. The sleep time can be extended to about 300 ms by setting XSleep to 8
(which is done by setting XSleep in control register 4 to 1), the time resolution is then about
9.6 ms.
14.1.3
Start-up Mode
During TStartup_PLL the PLL is enabled and starts up. If the PLL is locked, the signal processing
circuit starts up (TStartup_Sig_Proc). After the start-up time all circuits are in stable condition and
ready to receive.
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Figure 14-1. Flow Chart RX Polling Mode/RX Mode
Start RX Polling Mode
Sleep Mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic
is enabled.
Output level on Pin RX_ACTIVE -> Low; IS = IIDLE_X
TSleep = Sleep × 1024 × TDCLK × XSleep
Sleep:
XSleep:
TDCLK:
Defined by bits Sleep0 ... Sleep4 in Control
Register 4
Defined by bit XSleep in Control Register 4
Basic clock cycle
TStartup_PLL:
798.5 × TDCLK (typ)
TStartup_Sig_Proc:
930 × TDCLK
546 × TDCLK
354 × TDCLK
258 × TDCLK
Start RX Mode
Start-up Mode:
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE -> High; IS = IStartup_PLL_X ;TStartup_PLL
Start-up signal processing:
The signal processing circuit are enabled.
Output level on pin RX_ACTIVE -> High; IS = IStartup_Sig_Proc_X ;
TStartup_Sig_Proc
Bit-check Mode:
The incomming data stream is analyzed. If the timing indicates a valid transmitter
signal, the control bit CLK_ON and OPM0 are set to 1 and the transceiver is set
to receiving mode. Otherwise it is set to Sleep mode or to Start-up mode.
Output level on pin RX_ACTIVE -> High
IS = IStartup_Sig_Proc_X
TBit-check
NO
Bit check
ok ?
YES
OPM0=1
?
NO
Set CLK_ON = 1
Set OPM0 = 1
YES
NO
NO
TSLEEP=0
?
YES
T_MODE = 0 AND
P_MODE = 0
?
YES
Set IRQ
Receiving Mode:
The incomming data stream is passed via the TX/RX Data Buffer or via pin
SDO_TMDO to the connected microcontroller. If an bit error occurs the
transceiver is set back to Start-up mode.
Output level on pin RX_ACTIVE -> High
IS = IS_RX
T_MODE = 1
NO
and level on pin CS =
inactive ?
Start bit
detected ?
NO
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
Is defined by the selected baud rate range and
TDCLK. The baud-rate range is defined by bit
Baud0 and Baud1 in Control Register 6.
TBit-check:
Depends on the result of the bit check.
If the bit check is ok, TBit-check depends on the
number of bits to be checked (NBit-check) and
on the utilized data rate.
If the bit check fails, the average time period for
that check depends on the selected baud-rate
range and on TXDCLK. The baud-rate range is
defined by bit Baud0 and Baud1 in Control
Register6.
If the transparent mode is not active and the
transceiver detects a bit error after a successful
bit check and before the start bit is detected pin
IRQ will be set to high and the transceiver is set
back to start-up mode.
YES
YES
RX data stream
available on pin
SDO_TMDO
RX data stream is
written into the TX/RX
Data Buffer
Bit error ?
NO
YES
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14.1.4
Bit-check Mode
In Bit-check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distance between 2 signal edges are continuously compared to a programmable time window. The maximum count of this edge to edge test before the transceiver
switches to receiving mode is also programmable.
14.1.5
Bit-check Configuration
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The
maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBit-check in
control register 5. This implies 0, 6, 12 and 18 edge to edge checks respectively. If NBit-check is
set to a higher value, the transceiver is less likely to switch to receiving mode due to noise. In the
presence of a valid transmitter signal, the Bit-check takes less time if NBit-check is set to a lower
value. In RX polling mode, the Bit-check time is not dependent on NBit-check if no valid signal is
present. Figure 14-2 shows an example where 3 bits are tested successful.
Figure 14-2. Timing Diagram for Complete Successful Bit-check
(Number of checked bits: 3)
RX_ACTIVE
Bit-check ok
Bit-check
1/2 bit
1/2 bit
1/2 bit
1/2 bit
1/2 bit
1/2 bit
Demod_Out
TStartup_Sig_Proc
TBit-check
Start-up mode
Bit-check mode
Receiving mode
According to Figure 14-3, the time window for the Bit-check is defined by two separate time limits. If the edge to edge time tee is in between the lower Bit-check limit TLim_min and the upper
Bit-check limit TLim_max, the check will be continued. If tee is smaller than limit TLim_min or exceeds
TLim_max, the Bit-check will be terminated and the transceiver switches to sleep mode.
Figure 14-3. Valid Time Window for Bit-check
1/fSignal
Demod_Out
tee
TLim_min
TLim_max
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4829C–RKE–09/05
For the best noise immunity it is recommended to use a low span between TLim_min and TLim_max.
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
“11111...” or a “10101...” sequence in Manchester or bi-phase is a good choice concerning that
advice. A good compromise between sensitivity and susceptibility to noise regarding the
expected edge to edge time tee is a time window of ±38%. To get the maximum sensitivity the
time window should be ±50% and then NBit-check ≥ 6. Using preburst patterns that contain various
edge to edge time periods, the Bit-check limits must be programmed according to the required
span.
The Bit-check limits are determined by means of the formula below:
TLim_min = Lim_min × TXDCLK
TLim_max = (Lim_max -1) × TXDCLK
Lim_min is defined by the bits Lim_min 0 to Lim_min 5 in control register 5.
Lim_max is defined by the bits Lim_max 0 to Lim_max 5 in control register 6.
Using the above formulas, Lim_min and Lim_max can be determined according to the required
TLim_min, TLim_max and TXDCLK. The time resolution defining TLim_min and TLim_max is TXDCLK. The
minimum edge to edge time tee is defined according to the section “Receiving Mode” on page 58.
The lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is
Lim_max = 63.
Figure 14-4, Figure 14-5 and Figure 14-6 on page 57 illustrate the Bit-check for the Bit-check
limits Lim_min = 14 and Lim_max = 24. The signal processing circuits are enabled during
TStartup_PLL and TStartup_Sig_Proc. The output of the ASK/FSK demodulator (Demod_Out) is undefined during that period. When the Bit-check becomes active, the Bit-check counter is clocked
with the cycle TXDCLK.
Figure 14-4 shows how the Bit-check proceeds if the Bit-check counter value CV_Lim is within
the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 14-5 on
page 57 the Bit-check fails as the value CV_Lim is lower than the limit Lim_min. The Bit-check
also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 14-6 on page 57.
Figure 14-4. Timing Diagram During Bit-check
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Bit-check ok
Bit-check ok
Bit-check
1/2 bit
1/2 bit
1/2 bit
Demod_Out
Bit-check counter
0
TStartup_Sig_Proc
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 10 11 12131415 1 2 3 4 5 6 7
TXDCLK
Start-up mode
56
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Bit-check mode
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Figure 14-5. Timing Diagram for Failed Bit-check (Condition CV_Lim < Lim_min)
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Bit check failed (CV_Lim < Lim_min)
Bit-check
1/2 bit
Demod_Out
Bit-check counter
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112
TStartup_Sig_Proc
Start-up mode
0
TBit-check
TSleep
Bit-check mode
Sleep mode
Figure 14-6. Timing Diagram for Failed Bit-check (Condition: CV_Lim ≥ Lim_max)
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Bit-check failed (CV_Lim ≥ Lim_min)
Bit-check
1/2 bit
Demod_Out
Bit-check counter
14.1.6
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112 131415161718192021222324
0
TStartup_Sig_Proc
TBit-check
TSleep
Start-up mode
Bit-check mode
Sleep mode
Duration of the Bit-check
If no transmitter is present during the Bit-check, the output of the ASK/FSK demodulator delivers
random signals. The Bit-check is a statistical process and TBit-check varies for each check. Therefore, an average value for TBit-check is given in the electrical characteristics. TBit-check depends on
the selected baud rate range and on TXDCLK. A higher baud-rate range causes a lower value for
TBit-check resulting in a lower current consumption in RX polling mode.
In the presence of a valid transmitter signal, TBit-check is dependent on the frequency of that signal, fSignal, and the count of the bits, NBit-check. A higher value for NBit-check thereby results in a
longer period for TBit-check requiring a higher value for the transmitter pre-burst TPreburst.
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4829C–RKE–09/05
14.1.7
Receiving Mode
If the Bit-check was successful for all bits specified by NBit-check, the transceiver switches to
receiving mode. To activate a connected microcontroller, bit CLK_ON in control register 3 is set
to 1. An interrupt is issued at pin IRQ if the control bits T_MODE = 0 and P_MODE = 0.
If the transparent mode is active (T_MODE = 1) and the level on pin CS is inactive (no data
transfer via the serial interface), the RX data stream is available on pin SDO_TMDO (Figure
14-7).
Figure 14-7. Receiving Mode (TMODE = 1)
Preburst
Byte 1
Startbit
Bit-check ok
Byte 2
Byte 3
Demod_Out
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
SDO_TMDO
Bit-check mode
Receiving mode
If the transparent mode is inactive (T_MODE = 0), the received data stream is buffered in the
TX/RX data buffer (see Figure 14-8 on page 59). The TX/RX data buffer is only usable for
Manchester and Bi-phase coded signals. It is permanently possible to transfer the data from the
data buffer via the 4-wire serial interface to a microcontroller (see Figure 13-1 on page 47).
Buffering of the data stream:
After a successful Bit-check, the transceiver switches from Bit-check mode to receiving mode. In
receiving mode the TX/RX data buffer control logic is active and examines the incoming data
stream. This is done, like in the Bit-check, by subsequent time frame checks where the distance
between two edges is continuously compared to a programmable time window as illustrated in
Figure 14-8 on page 59. Only two distances between two edges in Manchester and Bi-phase
coded signals are valid (T and 2T).
The limits for T are the same as used for the Bit-check. They can be programmed in control
register 5 and 6 (Lim_min, Lim_max).
The limits for 2T are calculated as follows:
Lower limit of 2T:
Lim_min_2T = ( Lim_min + Lim_max ) – ( Lim_max – Lim_min ) ⁄ 2 T Lim_min_2T = Lim_min_2T × T XDCLK
Upper limit of 2T:
Lim_max_2T = ( Lim_min + Lim_max ) + ( Lim_max – Lim_min ) ⁄ 2
T Lim_max_2T = (Lim_max_2T – 1 ) × T XDCLK
If the result of Lim_min_2T or Lim_max_2T is not an integer value, it will be round up.
If the TX/RX data buffer control logic detects the start bit, the data stream is written in the TX/RX
data buffer byte by byte. The start bit is part of the first data byte and must be different from the
bits of the preburst. If the preburst consists of a sequence of “00000...”, the start bit must be a 1.
If the preburst consists of a sequence of “11111...”, the start bit must be a 0.
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If the data stream consists of more than 16 bytes, a buffer overflow occurs and the TX/RX data
buffer control logic overwrites the bytes already stored in the TX/RX data buffer. So it is very
important to ensure that the data is read in time so that no buffer overflow occurs in that case
(see Figure 13-1 on page 47). There is a counter that indicates the number of received bytes in
the TX/RX data buffer (see section “Transceiver Configuration” on page 47). If a byte is transferred to the microcontroller, the counter is decremented, if a byte is received, the counter is
incremented. The counter value is available via the 4-wire serial interface.
An interrupt is issued if the counter while counting forwards reaches the value defined by the
control bits IR0 and IR1 in control register 1.
Figure 14-8. Receiving Mode (TMODE = 0)
Preburst
Bit-check ok
T
Byte 1
Startbit
Byte 2
Byte 3
2T
Demod_Out
'0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '0' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'
Bit-check mode
Receiving mode
TX/RX Data Buffer
Byte 16, Byte 32, ...
Byte 15, Byte 31, ...
Byte 14, Byte 30, ...
Byte 13, Byte 29, ...
Byte 12, Byte 28, ...
Byte 11, Byte 27, ...
Byte 10, Byte 26, ...
Byte 9, Byte 25, ...
Byte 8, Byte 24, ...
Byte 7, Byte 23, ...
Byte 6, Byte 22, ...
Byte 5, Byte 21, ...
Byte 4, Byte 20, ...
1 0 1 1 0 0
Byte 3, Byte 19, ...
1 1 1 0 0 1 1 0 Byte 2, Byte 18, ...
0 1 0 0 0 0 0 1 Byte 1, Byte17, ...
MSB
LSB
Readable via 4-wire serial interface
If the TX/RX data buffer control logic detects a bit error, an interrupt is issued and the transceiver
is set back to the start-up mode (see Figure 14-1 on page 54 and Figure 14-9).
a) tee < TLim_min or TLim_max < tee < TLim_min_2T or tee > TLim_max_2T
b) Logical error (no edge detected in the bit center)
Bit error:
Note:
The byte consisting of the bit error will not be stored in the TX/RX data buffer. Thus it is not available via the 4-wire serial interface.
Writing the control register 1, 4, 5, 6 or 7 during receiving mode resets the TX/RX data buffer
control logic and the counter which indicates the number of received bytes. If the bits OPM0 and
OPM1 are still 1 and OPM2 is still 0 after writing to a control register, the transceiver changes to
the start-up mode (start-up signal processing).
Figure 14-9. Bit Error (TMODE = 0)
Bit error
Demod_Out
Byte n-1
Byte n
Receiving mode
Byte n+1
Bit-check ok
Preburst
Start-up mode Bit-check mode
Byte 1
Receiving mode
59
4829C–RKE–09/05
Table 14-2.
Mode
RX Demodulation Scheme
ASK/_NFSK
0
RX
1
14.1.8
T_MODE
RFIN
Bit in TX/RX
Data Buffer
Level on Pin
SDO_TMDO
0
fFSK_L → fFSK_H
1
X
0
fFSK_H → fFSK_L
0
X
1
fFSK_H
-
1
1
fFSK_L
-
0
0
fASK off → fASK on
1
X
0
fASK on → fASK off
0
X
1
fASK on
-
1
1
fASK off
-
0
Recommended Lim_min and Lim_max for Maximum Sensitivity
The sensitivity measurement in the section “Low-IF Receiver” on page 10, in Table 7-3 and
Table 7-4 on page 12 have been done with the Lim_min and Lim_max values according to Table
14-3. These values are optimized for maximum sensitivity. Note that since these Limits are optimized for sensitivity the number of checked bit NBit-check has to be at least 6 to prevent the circuit
from waking up too often in polling mode due to noise.
Table 14-3.
Recommended Lim_min and Lim_max Values for Different Baud Rates
fRF (fXTAL)/
MHz
1.0 kBaud
BR_Range_0
XLim = 1
315
(12.73193)
Lim_min = 13 (251 µs) Lim_min = 12 (121 µs) Lim_min = 11 (55 µs) Lim_min = 11 (28 µs)
Lim_max = 38 (715 µs) Lim_max = 34 (332 µs) Lim_max = 32 (156 µs) Lim_max = 32 (78 µs)
Lim_min = 11 (14 µs)
Lim_max = 32 (39 µs)
433.92
(13.25311)
Lim_min = 13 (251 µs) Lim_min = 11 (106 µs) Lim_min = 11 (53 µs) Lim_min = 11 (27 µs)
Lim_max = 38 (715 µs) Lim_max = 32 (299 µs) Lim_max = 32 (150 µs) Lim_max = 32 (75 µs)
Lim_min = 11 (13 µs)
Lim_max = 32 (37 µs)
868.3
(13.41191)
Lim_min = 13 (248 µs) Lim_min = 12 (115 µs) Lim_min = 11 (52 µs) Lim_min = 11 (26 µs)
Lim_max = 38 (706 µs) Lim_max = 34 (315 µs) Lim_max = 32 (148 µs) Lim_max = 32 (74 µs)
Lim_min = 11 (13 µs)
Lim_max = 32 (37 µs)
60
2.4 kBaud
BR_Range_0
XLim = 0
5 kBaud
BR_Range_1
XLim = 0
10 kBaud
BR_Range_2
XLim = 0
20 kBaud
BR_Range_3
XLim = 0
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
14.2
TX Operation
The transceiver is set to TX operation by using the bits OPM0, OPM1 and OPM2 in the control
register 1.
Table 14-4.
Control Register 1
OPM2
OPM1
OPM0
Function
0
0
1
TX mode
Before activating the TX mode, the TX parameters (baud rate, modulation scheme...) must be
selected as illustrated in Figure 14-10 on page 62. The baud rate depends on Baud 0 and
Baud 1 in control register 6 and TX0 to TX5 in control register 7 (see section “Control Register”
on page 37). The modulation is selected with ASK_NFSK in control register 4. The FSK frequency deviation is fixed to about ±19 kHz (see Table 9-1 on page 30). If P_Mode is set to 1, the
Manchester modulator is disabled and pattern mode is active (NRZ, see Table 14-5 on page
64).
After the transceiver is set to TX mode the start-up mode is active and the PLL is enabled. If the
PLL is locked, the TX mode is active.
If the transceiver is in start-up or TX mode, the TX/RX data buffer can be loaded via the 4-wire
serial interface. After N bytes are in the buffer and the TX mode is active, the transceiver starts
transmitting automatically (beginning with the MSB). Bit 0 to Bit 4 in the command Write TX/RX
Data Buffer defines the value N (0 ≤ N ≤ 16; see section “Command Structure” on page 49).
While transmitting, it is permanently possible to load new data in the TX/RX data buffer. To prevent a buffer overflow or interruptions during transmitting the user must ensure that data is
loaded at the same speed as it is transmitted.
There is a counter that indicates the number of bytes to be transmitted (see section “Transceiver
Configuration” on page 47). If a byte is loaded, the counter is incremented, if a byte is transmitted, the counter is decremented. The counter value is available via the 4-wire serial interface. An
IRQ is issued if the counter reaches the value defined by the control bits IR0 and IR1 in control
register 1.
Note:
Writing to the control register 1, 4, 5, 6 or 7 during TX mode, resets the TX/RX data buffer and the
counter which indicates the number of bytes to be transmitted.
If T_Mode in control register 1 is set to 1, the transceiver is in TX transparent mode. In this mode
the TX/RX data buffer is disabled and the TX data stream must be applied on pin SDI_TMDI.
Figure 14-10 on page 62 illustrates the flow chart of the TX transparent mode.
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4829C–RKE–09/05
Figure 14-10. TX Operation (T_MODE = 0)
Write Control Register 8
FE_MODE:
PWSELECT:
PWSET0 ... PWSET4:
Set FE_MODE = 1
Set PWSELECT = 1 to reduce
the output power with SETPWR.
adjust SETPWR. Don't care if
PWSELECT = 0.
Write Control Register 7
POUT_SELECT, POUT_DATA: Application defined.
TX0 ... TX5:
Select the baud rate
Write Control Register 6
Baud1, Baud0:
Select Baudrate Range
Lim_max0 ... Lim_max5:
Don't care
Write Control Register 5
Bitchk1, Bitchk0:
Don't care
Lim_min0 ... Lim_min5:
Don't care
Write Control Register 4
ASK/_NFSK:
Select modulation.
Sleep0 ... Sleep4:
Don't care
XSleep:
Don't care
XLim:
Don't care
Write Control Register 3
FR7, FR8, FR9:
Adjust fRF
CLK_EN, CLK_ON:
Application defined.
Write Control Register 2
FR0 ...FR6:
P_mode:
Write Control Register 1
IR1, IR0:
PLL_MODE:
FS:
OPM2, OPM1, OPM0:
T_mode:
Adjust fRF
Enable or disable the
Manchester modulator
Select an event which activates
an interrupt
Set PLL_MODE = 0
Select operating frequency
Set OPM2 = 0, OPM1 = 0 and
OPM0 = 1
Set T_mode = 0
Write TX/RX Data Buffer (max. 16 byte)
N
Idle Mode
Start-up Mode (TX)
TStartup = 331.5 × TDCLK
Pin IRQ=1 ?
Y
N
TX Mode
Write TX/RX Data Buffer (max. 16 - number of bytes still in
the TX/RX Data Buffer)
Command: Delete_IRQ
N
TX more Data Bytes
?
Y
Pin IRQ=1 ?
Y
Write Control Register 1
OPM2, OPM1, OPM0:
Set IDLE
Idle Mode
62
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4829C–RKE–09/05
ATA5823/ATA5824
Figure 14-11. TX Transparent Mode (T_MODE = 1)
Write Control Register 8
FE_MODE:
PWSELECT:
PWSET0 ... PWSET4:
Set FE_MODE = 1
Set PWSELECT = 1 to reduce
the output power with SETPWR.
Adjust SETPWR. Don't care if
PWSELECT = 0.
Write Control Register 7
POUT_SELECT, POUT_DATA: Application defined.
TX0 ... TX5:
Don't care.
Write Control Register 6
Baud1, Baud0:
Don't care.
Lim_max0 ... Lim_max5:
Don't care.
Write Control Register 5
Bitchk1, Bitchk0:
Don't care.
Lim_min0 ... Lim_min5:
Don't care.
Write Control Register 4
ASK/_NFSK:
Select modulation.
Sleep0 ... Sleep4:
Don't care.
XSleep:
Don't care.
XLim:
Don't care.
Write Control Register 3
FR7, FR8, FR9:
Adjust fRF
CLK_EN, CLK_ON:
Application defined.
Write Control Register 2
FR0 ...FR6:
Adjust fRF
P_mode:
Don't care.
Write Control Register 1
IR1, IR0:
Don't care.
PLL_MODE:
Set PLL_MODE = 0
FS:
Select operating frequency
OPM2, OPM1, OPM0:
Set OPM2 = 0, OPM1 = 0 and
OPM0 = 1.
T_mode:
Set T_mode = 1
Idle Mode
Start-up Mode (TX)
TStartup = 331.5 × TDCLK
Apply TX Data on Pin SDI_TMDI
TX Mode
Write Control Register 1
OPM2, OPM1, OPM0:
Set IDLE
Idle Mode
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4829C–RKE–09/05
Table 14-5.
Mode
TX Modulation Schemes
ASK/_NFSK
P_Mode
T_Mode
Bit in TX/RX
Data Buffer
Level on Pin
SDI_TMDI
RFOUT
0
0
1
X
fFSK_L → fFSK_H
0
0
0
X
fFSK_H → fFSK_L
1
0
1
X
fFSK_H
1
0
0
X
fFSK_L
X
1
X
1
fFSK_H
X
1
X
0
fFSK_L
0
0
1
X
fASK off → fASK on
0
0
0
X
fASK on → fASK off
1
0
1
X
fASK on
1
0
0
X
fASK off
X
1
X
1
fASK on
X
1
X
0
fASK off
0
TX
1
14.3
Full-duplex Operation
The transceiver is set to full-duplex mode (FD mode) by using the bits OPM0, OPM1 and OPM2
in the control register 1. In FD mode 2 transceiver exchange the content of the TX buffer simultaneously. One transceiver must be configured as master and one as slave.
Table 14-6.
Control Register 1
OPM2
OPM1
OPM0
Function
1
0
1
Full-duplex mode (Master)
1
1
1
Full-duplex mode (Slave)
Before activating FD mode in both transceivers, the baud rate must be selected in control
register 6 (Baud1 = 0, Baud0 = 1). Additionally, in the slave the limits for the Bit-check and the
number of bits to be checked during the Bit-check NBit-check must be adjusted in control register 5
and 6 (Lim_min0 ... Lim_min5, Lim_max0 ... Lim_max5, BitChk0, BitChk1).
After activating the FD mode in control register 1, both transceivers are in the startup mode. During the startup mode, in master and slave, the TX data stream can be written in the TX buffer.
In the master the TX data stream consists of preburst, startbit, synchronization pattern (3 bytes)
and maximally 8 bytes of data. The preburst contains a sequence of “11111...”. The minimum
applicable preburst length is 15 bits and can be extended in 8 bit steps up to 95 bits. The value
of the start bit is fixed and must be a 0. The position of the start bit is the LSB in the last byte of
the preburst. The synchronization pattern contains 3 bytes with a fixed value (Byte1: FF hex,
Byte2: 00 hex, Byte3: 00 hex). The data block is user defined and contains maximally 8 bytes. If
the preburst contains more than 39 bits the area for the data block will be equally reduced (Figure 14-12 on page 65.)
In the slave the TX data stream consists of the synchronization pattern (3 bytes) and also maximally 8 bytes of data. The synchronization pattern contains 3 bytes with a fixed value (Byte1:
00 hex, Byte2: 7F hex, Byte3: FF hex). The data block is user defined and contains maximally
8 bytes (Figure 14-12 on page 65). The length of the data block must be equal in the master and
slave.
64
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4829C–RKE–09/05
ATA5823/ATA5824
If the time TStartup-PLL-fd (798.5 × TDCLK) is elapsed the PLL is enabled and locked.
The master activates the power amplifier (PA) and starts transmitting the preburst, startbit, synchronization pattern and data block, when the PLL is locked and at least N bytes are in the TX
Buffer. Bit 0 to bit 4 in the command Write TX/RX Data Buffer defines the value N (0 ≤ N ≤ 16;
see section “Command Structure” on page 49).
If the PLL is locked, the slave activates the PA and enables the analog signal processing. After
TStartup-sig-proc-fd (546 × TDCLK) the analog signal processing is settled and the slave begins with
the Bit-check. If the Bit-check was successful, the start bit was detected and at least N Bytes are
in the TX Buffer, the slave starts transmitting the synchronization pattern and the data block.
While transmitting the synchronization pattern, a synchronization procedure synchronizes both
transceivers. Thus master and slave are synchronized while transmitting the data block.
If the TX buffer is empty, an interrupt will be issued and the PA will be switched off after the time
TDelay (168 × TDCLK). TDelay is implemented because of different internal delays in the RX signal
path in master and slave.
While transmitting the data block, the receiving data is EX-OR-ed with the transmitting data and
the result is written in the RX Buffer. Thus, after the FD operation the TX data of the slave is in
the RX buffer of the master and the TX data of the master is in the RX Buffer of the slave.
After recognizing the interrupt, the microcontroller can read out the received data from the
TX/RX data buffer. During writing the command “Read TX/RX Data Buffer” the number of
received bytes in the buffer is issued on pin SDO_TMDO.
After reading the TX/RX Data Buffer the transceiver should be set to the IDLE mode.
Figure 14-12. TX Buffer FD Mode
TX Buffer Slave
TX Buffer Master
MSB
Preburst (FF hex)
Preburst (FF hex)
Preburst (FF hex)
Preburst (FF hex)
Preburst and Start bit (FE hex)
Synchronization Byte 1 (FF hex)
Synchronization Byte 2 (00 hex)
Synchronization Byte 3 (00 hex)
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Data Byte 8
1
1
1
1
1
1
0
0
x
x
x
x
x
x
x
x
1
1
1
1
1
1
0
0
x
x
x
x
x
x
x
x
1
1
1
1
1
1
0
0
x
x
x
x
x
x
x
x
1
1
1
1
1
1
0
0
x
x
x
x
x
x
x
x
1
1
1
1
1
1
0
0
x
x
x
x
x
x
x
x
1
1
1
1
1
1
0
0
x
x
x
x
x
x
x
x
1
1
1
1
1
1
0
0
x
x
x
x
x
x
x
x
LSB
MSB
1
1
1
1
0
1
0
0
x
x
x
x
x
x
x
x
0
0
1
x
x
x
x
x
x
x
x
39 Bits Preburst
1 Start bit
3 Bytes Synchronization Pattern
8 Bytes Data
LSB
0
1
1
x
x
x
x
x
x
x
x
0
1
1
x
x
x
x
x
x
x
x
0
1
1
x
x
x
x
x
x
x
x
0
1
1
x
x
x
x
x
x
x
x
0
1
1
x
x
x
x
x
x
x
x
0
1
1
x
x
x
x
x
x
x
x
0
1
1
x
x
x
x
x
x
x
x
Synchronization Byte 1 (00 hex)
Synchronization Byte 2 (7F hex)
Synchronization Byte 3 (FF hex)
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Data Byte 8
3 Bytes Synchronization Pattern
8 Bytes Data
65
4829C–RKE–09/05
The timing of the FD mode is illustrated in Figure 14-13 on page 67. A proper data transfer takes
place if the FD mode is enabled in the slave before it is enabled in the master. If the FD mode is
enabled in the master before it is enabled in the slave, a maximum delay TFD_sync is allowed for a
proper operation. TFD_sync depends on the preburst length and the number of bits to be checked
during the Bit-check. This is calculated as follows:
TFD_sync < TPreburst - TStartup-sig-proc-fd - TBit-check-min
Table 14-7.
TBit-check-min
NBit-check
TBit-check-min
3
4 × 168 × TDCLK
6 (recommended)
7 × 168 × TDCLK
9
10 × 168 × TDCLK
This means, to get a extended time period for enabling the FD mode, increase the preburst
length in the master and reduce NBit-check in the slave. The reference points for TFD_sync are the
sampling edge (pin SCK) for the LSB while writing control register 1.
For a proper operation in the slave, a wake-up due to noise must be prevent (bit check + start bit
ok). To achieve this for the slave the following adjustments are recommended:
1. Set NBIT-check ≥ 6
2. Start FD mode in master and slave as simultaneously as possible.
66
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
Figure 14-13. Timing Full-duplex Mode
Master
Enable FD Mode
Startup
(TStartup_PLL_fd =
798.5 × TDCLK)
Slave
TFD_sync
Enable FD Mode
PA enabled and at least
N Byte in TX Buffer
Startup
(TStartup_PLL_fd = 798.5 × TDCLK)
PA enabled
Startup Analog Signal
Processing
(TStartup_sig_proc_fd = 546 × TDCLK)
n Bits Preburst
(TPreburst =
n × 168 × TDCLK)
TBitcheck_min
Startbit
(TStartbit =
168 × TDCLK)
Bit-check
(TBit-check)
Start bit
At least N Byte in TX Buffer
Synchronization
(TSync =
24 × 168 × TDCLK)
Synchronization
Master and Slave synchron
n Bits Data
(TData =
n × 168 × TDCLK)
Data
Delay
(TDelay = 168 × TDCLK)
Delay
Pin IRQ = 1; PA disabled
Read Data from RX
Buffer
Set transceiver to
IDLE Mode
Pin IRQ = 1; PA disabled
Read Data from RX Buffer
Set transceiver to IDLE Mode
t
67
4829C–RKE–09/05
Figure 14-14. Flow FD mode (Master)
Write Control Register 8
FE_MODE:
PWSELECT:
PWSET0 ... PWSET4:
Set FE_MODE = 1
Don't care
Adjust SETPWR to reduce the
output power
Write Control Register 7
POUT_SELECT, POUT_DATA: Application defined.
TX0 ... TX5:
Don't care
Write Control Register 6
Baud1, Baud0:
Set BAUD1 = 0, BAUD0 = 1
Lim_max0 ... Lim_max5:
Don't care
Write Control Register 5
Bitchk1, Bitchk0:
Don't care
Lim_min0 ... Lim_min5:
Don't care
Write Control Register 4
ASK/_NFSK:
Dont' care
Sleep0 ... Sleep4:
Don't care
XSleep:
Don't care
XLim:
Don't care
Write Control Register 3
FR7, FR8, FR9:
Adjust fRF
CLK_EN, CLK_ON:
Application defined
Write Control Register 2
FR0 ...FR6:
Adjust fRF
P_MODE:
Don't care
Write Control Register 1
IR1, IR0:
Don't care
PLL_MODE:
Application defined
FS:
Select operating frequency
OPM2, OPM1, OPM0:
Set OPM2 = 1, OPM1 = 0,
OPM0 = 1
T_MODE:
T_MODE = 0
Write TX/RX Buffer
(preburst, startbit, synchronization pattern, data block)
(max. 16 byte)
N
Idle Mode
Start-up FD Mode (Master)
TStartup_PLL_fd = 798.5 × TDCLK
FD Mode
(Master)
Pin IRQ=1 ?
Y
Read TX/RX Buffer
Write Control Register 1
OPM2, OPM1, OPM0:
Set IDLE
Idle Mode
68
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
Figure 14-15. Flow FD Mode (Slave)
Write Control Register 8
FE_MODE:
PWSELECT:
PWSET0 ... PWSET4:
Set FE_MODE = 1
Don't care
Adjust SETPWR to reduce the
output power
Write Control Register 7
POUT_SELECT, POUT_DATA: Application defined
TX0 ... TX5:
Don't care
Write Control Register 6
Baud1, Baud0:
BAUD1 = 0, BAUD0 = 1
Lim_max0 ... Lim_max5:
Lim_max5 = 1, Lim_max4 = 0,
Lim_max3 = 0, Lim_max2 = 0,
Lim_max1 = 0, Lim_max0 = 0
Write Control Register 5
Bitchk1, Bitchk0:
Bitchk1 = 1, Bitchk0 = 0
Lim_min0 ... Lim_min5:
Lim_min5 = 0, Lim_min4 = 0,
Lim_min3 = 1, Lim_min2 = 0,
Lim_min1 = 1, Lim_min0 = 1
Write Control Register 4
ASK/_NFSK:
Dont' care
Sleep0 ... Sleep4:
Don't care
XSleep:
Don't care
XLim:
Don't care
Write Control Register 3
FR7, FR8, FR9:
adjust fRF
CLK_EN, CLK_ON:
application defined
Write Control Register 2
FR0 ...FR6:
Adjust fRF
P_MODE:
Don't care
Write Control Register 1
IR1, IR0:
Don't care
PLL_MODE:
Application defined
FS:
Select operating frequency
OPM2, OPM1, OPM0:
Set OPM2 = 1, OPM1 = 1,
OPM0 = 1
T_MODE:
T_MODE = 0
Idle Mode
Start-up FD Mode (Slave)
TStartup_PLL_fd = 798.5 × TDCLK
Write TX/RX Buffer
(Synchronization pattern, data block)
(max. 9 byte)
TStartup-sig-proc-fd = 546 × TDCLK
N
Pin IRQ=1 ?
Y
FD Mode
(Slave)
Read TX/RX Buffer
Write Control Register 1
OPM2, OPM1, OPM0:
Set IDLE
Idle Mode
69
4829C–RKE–09/05
14.4
Interrupts
Via pin IRQ, the transceiver signals different operating conditions to a connected microcontroller. If a specific operating condition occurs, pin IRQ is set to a high level.
If an interrupt occurs, it is recommended to delete the interrupt immediately by reading the status register, thus the next possible interrupt doesn’t get lost. If the Interrupt pin doesn’t switch to
a low level by reading the status register, the interrupt was triggered by the RX/TX data buffer. In
this case, read or write the RX/TX data buffer according to Table 14-8.
Table 14-8.
Interrupt Handling
Operating Conditions Which Sets Pin IRQ
to High Level
Operations Which Sets Pin IRQ to Low Level
Events in Status Register
State transition of status bit N_Power_On
(0 → 1; 1 → 0)
Appearance of status bit Power_On
(0 → 1)
Read status register or
Command delete IRQ
Events During TX Operation (T_MODE = 0)
1, 2, 4 or 12 bytes are in the TX data buffer or
the TX data buffer is empty (depends on IR0
and IR1 in control register 1)
Write TX data buffer or
Write control register 1 or
Write control register 4 or
Write control register 5 or
Write control register 6 or
Write control register 7 or
Command delete IRQ
Events During RX Operation (T_MODE = 0)
1, 2, 4 or 12 received bytes are in the RX data
buffer or a receiving error is occurred (depends
on IR0 and IR1 in control register 1)
Successful Bit-check (P_MODE = 0)
Read RX data buffer or
Write control register 1 or
Write control register 4 or
Write control register 5 or
Write control register 6 or
Write control register 7 or
Command delete IRQ
Events During FD Operation
TX data buffer empty
70
Read RX data buffer or
Write control register 1 or
Write control register 4 or
Write control register 5 or
Write control register 6 or
Write control register 7 or
Command delete IRQ
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
15. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Max.
Unit
150
°C
–55
+125
°C
Tamb
–40
+105
°C
Supply voltage VS2
VMaxVS2
–0.3
+7.2
V
Supply voltage VS1
VMaxVS1
–0.3
+4
V
VMaxVSINT
–0.3
+5.5
V
ESD (Human Body Model ESD S.5.1)
every pin
HBM
–2.5
+2.5
kV
ESD (Machine Model JEDEC A115A)
every pin
MM
–200
+200
V
ESD (Field Induced Charge Device Model ESD
STM 5.3.1-1999)
every pin
FCDM
–500
500
V
Maximum input level, input matched to 50Ω
Pin_max
10
dBm
Junction temperature
Tj
Storage temperature
Tstg
Ambient temperature
Supply voltage VSINT
Min.
16. Thermal Resistance
Parameters
Junction ambient
Symbol
Value
Unit
RthJA
25
K/W
71
4829C–RKE–09/05
17. Electrical Characteristics: General
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
Test Conditions
Pin(1)
Symbol
Min.
ATA5824
V433_N868 = GND
4, 10
fRF
RF operating frequency ATA5824
range
V433_N868 = AVCC
4, 10
ATA5823
V433_N868 = AVCC
No. Parameters
Max.
Unit
Type*
867
870
MHz
A
fRF
433
435
MHz
A
4, 10
fRF
314
316
MHz
A
VVS1 = VVS2 = VVSINT = 3V
(battery)
17, 18,
27
IS_OFF
< 10
nA
A
VVS2 = VVSINT = 5V (car)
17, 27
IS_OFF
< 10
nA
A
XTO running
VVS1 = VVS2 = VVSINT = 3V
(battery)
CLK disabled
17, 18,
27
IS_IDLE
260
µA
B
XTO running
VVS2 = VVSINT = 5V (car)
CLK disabled
17, 27
IS_IDLE
350
µA
B
System start-up time
From OFF mode to IDLE
mode including reset and
XTO start-up
(see Figure 12-4 on page 46)
XTAL: Cm = 5 fF,
C0 = 1.8 pF, Rm =15Ω
TPWR_ON_IRQ_1
0.3
ms
C
1.5
RX start-up time
From IDLE mode to receiving
mode
NBit-check = 3
Baud Rate = 20 kBaud,
BR_Range_3
(see Figure 14-1 on page 54
and Figure 14-2 on page 55)
TStartup_PLL +
TStartup_Sig_Proc
+ TBit-check
1.39
ms
A
1.6
TX start-up time
From IDLE mode to TX mode
(see Figure 14-10 on page
62)
TStartup
0.4
ms
A
1
1.1
1.2
1.3
1.4
Typ.
RX_TX_IDLE Mode
Supply current
OFF mode
Supply current
IDLE mode
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
72
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
2
2.1
2.2
2.3
2.4
2.5
Pin(1)
Symbol
fRF = 433.92 MHz and
fRF = 315 MHz
17, 18,
27
IS_RX
fRF = 868.3 MHz
17, 18,
27
TSleep = 49.45 ms
XSLEEP = 8, Sleep = 5
Baud Rate = 20 kBaud FSK,
CLK disabled
Test Conditions
Min.
Typ.
Max.
Unit
Type*
10.5
mA
A
IS_RX
10.3
mA
A
17, 18,
27
IS_Poll
484
µA
C
Baud Rate 20 kBaud
(4)
SREF_FSK
–103.5
–105.5
–107.0
dBm
B
Baud Rate 2.4 kBaud
(4)
SREF_FSK
–107.0
–109.0
–110.5
dBm
B
Baud Rate 10 kBaud
(4)
PREF_ASK
–109.5
–111.5
–113.0
dBm
B
Baud Rate 2.4 kBaud
(4)
PREF_ASK
–113.5
–115.5
–117.0
dBm
B
(4)
∆SREF1
dB
B
Receiver/RX Mode
Supply current RX
mode
Supply current
RX polling mode
Input sensitivity FSK
fRF = 433.92 MHz
Input sensitivity ASK
fRF = 433.92 MHz
Sensitivity change at
fRF = 315 MHz
fRF = 868.3 MHz
compared to
fRF = 433.92 MHz
FSK deviation
fDEV = ±19.5 kHz
limits according to Table
14-3 on page 60, BER = 10-3
Tamb = 25°C
ASK 100% level of carrier,
limits according to Table
14-3 on page 60, BER = 10-3
Tamb = 25°C
fRF = 433.92 MHz
to fRF = 315 MHz
–1.0
fRF = 433.92 MHz to
fRF = 868.3 MHz
S = SREF_ASK + ∆SREF1
S = SREF_FSK + ∆SREF1
+2.7
FSK fDEV = ±19.5 kHz
∆fOFFSET ≤ ±75 kHz
2.6
Sensitivity change
versus temperature,
supply voltage and
frequency offset
ASK 100%
∆fOFFSET ≤ ±75 kHz
S = SREF_ASK + ∆SREF1 +
∆SREF2
S = SREF_FSK + ∆SREF1 +
∆SREF2
(4)
∆SREF2
+4.5
–1.5
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
73
4829C–RKE–09/05
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
2.7
2.8
2.9
2.10
RSSI output
Test Conditions
Pin(1)
Symbol
Dynamic range
(4), 36
DRSSI
Lower level of range
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
(4), 36
PRFIN_Low
Upper level of range
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
(4), 36
PRFIN_High
Gain
(4), 36
Output voltage range
(4), 36
Output resistance RSSI RX mode
pin
TX mode
Maximum frequency
offset in FSK mode
Supported FSK
frequency deviation
2.11 System noise figure
36
Maximum frequency
difference of fRF between
receiver and transmitter in
FSK mode (fRF is the center
frequency of the FSK signal
with
fDEV = ±19.5 kHz)
PRF_IN ≤ +10 dBm
PRF_IN ≤ PRFIN_High
(see Figure 7-2 on page 12)
(4)
With up to 2 dB
loss of sensitivity.
Note that the tolerable
frequency offset is for
fDEV = ±28 kHz, 8.5 kHz
lower than for
fDEV = ±19.5 kHz hence
∆fOFFSET2 = ±66.5 kHz
fRF = 315 MHz
Min.
5.5
OVRSSI
350
RRSSI
8
32
Typ.
Unit
Type*
70
dB
A
–116
–115
–112
dBm
dBm
dBm
–46
–45
–42
dBm
dBm
dBm
8.0
10
40
Max.
A
A
10.5
mV/dB
A
1100
mV
A
12.5
50
kΩ
C
kHz
B
kHz
B
dB
B
∆fOFFSET1
∆fOFFSET2
–69
–75
(4)
fDEV
±14
(4)
NF
5.5
fRF = 433.92 MHz
(4)
NF
6.5
dB
B
fRF = 868.3 MHz
(4)
NF
9.7
dB
B
fIF
227
kHz
A
fIF
223
kHz
A
fIF
226
kHz
A
fRF = 315 MHz
2.12 Intermediate frequency fRF = 433.92 MHz
fRF = 868.3 MHz
+69
+75
±19.5
±28
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
74
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
2.13 System bandwidth
This value is for
information only!
Note that for crystal and
system frequency offset
calculations, ∆fOFFSET must
be used.
SBW
(4)
220
kHz
A
IIP2
+50
dBm
C
(4)
IIP3
–22
dBm
C
(4)
IIP3
–21
dBm
C
(4)
IIP3
–17
dBm
C
(4)
I1dBCP
–31
dBm
C
fRF = 433.92 MHz
(4)
I1dBCP
–30
dBm
C
fRF = 868.3 MHz
(4)
I1dBCP
–27
dBm
C
4
Zin_LNA
(44 – j233)
Ω
C
fRF = 868.3 MHz
∆fmeas1 = 10 MHz
fRF = 315 MHz
this values are for
information only, for blocking
System outband input behavior see Figure 7-3 on
2.16
1 dB compression point page 15 to Figure 7-7 on
page 17
fRF = 315 MHz
Min.
Typ.
Max.
fRF = 433.92 MHz
4
Zin_LNA
(32 – j169)
Ω
C
fRF = 868.3 MHz
4
Zin_LNA
(21 – j78)
Ω
C
BER < 10 , ASK: 100%
(4)
PIN_max
+10
–10
dBm
C
FSK: fDEV = ±19.5 kHz
(4)
PIN_max
+10
–10
dBm
C
f < 1 GHz
(4)
–57
dBm
C
f >1 GHz
(4)
–47
dBm
C
-3
2.19 LO spurious at LNA_IN fRF = 315 MHz
2.20 Image rejection
(4)
Type*
∆fmeas1 = 1.8 MHz
∆fmeas2 = 3.6 MHz
System outband
2.15 3rd-order input intercept fRF = 315 MHz
point
fRF = 433.92 MHz
Allowable peak RF
2.18 input level, ASK and
FSK
Symbol
Unit
∆fmeas1 = 1.800 MHz
System out-band
2.14 2nd-order input intercept ∆fmeas2 = 2.026 MHz
point with respect to fIF fIF = ∆fmeas2 – ∆fmeas1
2.17 LNA input impedance
Pin(1)
(4)
–100
dBm
C
fRF = 433.92 MHz
(4)
–98
dBm
C
fRF = 868.3 MHz
(4)
–85
dBm
C
Within the complete image
band
fRF = 315 MHz
(4)
25
30
dB
A
fRF = 433.92 MHz
(4)
25
30
dB
A
fRF = 868.3 MHz
(4)
20
25
dB
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
75
4829C–RKE–09/05
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
2.21
Useful signal to
interferer ratio
Pin(1)
Symbol
(4)
SNRFSK0-2
FSK BR_Range_3
(4)
SNRFSK3
4
6
dB
B
ASK (PRF < PRFIN_High)
(4)
SNRASK
10
12
dB
B
kHz
B
dBC
C
dBC
C
Test Conditions
Maximum frequency
offset in ASK mode
Typ.
Max.
Unit
Type*
2
3
dB
B
Peak level of useful signal to
peak level of interferer for
BER < 10-3 with any
modulation scheme of
interferer.
FSK BR_Ranges 0, 1, 2
2.22
Min.
Maximum frequency
difference of fRF between
Receiver and transmitter in
ASK mode
PRF_IN ≤+10 dBm
PRF_IN ≤PRF_IN_High
∆fOFFSET1
∆fOFFSET2
–79
–85
+79
+85
According to ETSI
regulations, the sensitivity
(BER = 10-3) is reduced by
3 dB if a continuous wave
blocking signal at ±∆f is
∆PBlock higher than the useful
signal level
(Baud Rate = 20 kBaud,
FSK, fDEV ±19.5 kHz,
Manchester code)
2.23 Blocking
fRF = 315 MHz
∆f ±0.75 MHz
∆f ±1.0 MHz
∆f ±1.5 MHz
∆f ±5.0 MHz
∆f ±10.0 MHz
Blocking behavior see Figure
7-3 to Figure 7-5 on page 15
fRF = 433.92 MHz
∆f ±0.75 MHz
∆f ±1.0 MHz
∆f ±1.5 MHz
∆f ±5.0 MHz
∆f ±10.0 MHz
Blocking behavior see Figure
7-3 to Figure 7-5 on page 15
(4)
(4)
∆PBLOCK
∆PBLOCK
55
57
60
66
73
54
56
59
65
67
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
76
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
2.24 CDEM
3
3.1
Test Conditions
Pin(1)
fRF = 868.3 MHz
∆f ±0.75 MHz
∆f ±1.0 MHz
∆f ±1.5 MHz
∆f ±5.0 MHz
∆f ±10.0 MHz
Blocking behavior see Figure
7-3 to Figure 7-5 on page 15
(4)
capacitor connected to pin
37 (CDEM)
37
Symbol
Min.
Typ.
Max.
49
52
56
64
67
∆PBLOCK
–5%
15
+5%
Unit
Type*
dBC
C
nF
D
Power Amplifier/TX Mode
Supply current TX
mode power amplifier
OFF
fRF = 868.3 MHz
17,18,
27
IS_TX_PAOFF
6.50
mA
A
fRF = 433.92 MHz and
fRF = 315 MHz
17,18,
27
IS_TX_PAOFF
6.95
mA
A
(10)
PREF1
dBm
B
PA on/0 dBm
fRF = 315 MHz
17, 18,
27
IS_TX_PAON1
8.5
mA
B
fRF = 433.92 MHz
17, 18,
27
IS_TX_PAON1
8.6
mA
B
fRF = 868.3 MHz
17, 18,
27
IS_TX_PAON1
9.6
mA
B
VVS1 = VVS2 = 3V
Tamb = 25°C
VPWR_H = GND
fRF = 315 MHz
RR_PWR = 56 kΩ
RLopt = 2.5 kΩ
3.2
Output power 1
fRF = 433.92 MHz
RR_PWR = 56 kΩ
RLopt = 2.3 kΩ
–2.5
0
+2.5
fRF = 868.3 MHz
RR_PWR = 30 kΩ
RLopt = 1.3 kΩ
RF_OUT matched to RLopt//
j/(2 × π × fRF × 1.0 pF)
3.3
Supply current TX
mode power amplifier
ON 1
0 dBm
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
77
4829C–RKE–09/05
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
(10)
PREF2
3.5
5.0
6.5
dBm
B
PA on/5 dBm
fRF = 315 MHz
17, 18,
27
IS_TX_PAON2
10.3
mA
B
fRF = 433.92 MHz
17, 18,
27
IS_TX_PAON2
10.5
mA
B
fRF = 868.3 MHz
17, 18,
27
IS_TX_PAON2
11.2
mA
B
(10)
PREF3
dBm
B
Test Conditions
VVS1 = VVS2 = 3 V
Tamb = 25°C
VPWR_H = GND
fRF = 315 MHz
RR_PWR = 30 kΩ
RLopt = 1.0 kΩ
3.4
Output power 2
fRF = 433.92 MHz
RR_PWR = 27 kΩ
RLopt = 1.1 kΩ
fRF = 868.3 MHz
RR_PWR = 16 kΩ
RLopt = 0.5 kΩ
RF_OUT matched to RLopt//
j/(2 × π × fRF × 1.0 pF)
3.5
Supply current TX
mode power amplifier
ON 2
5 dBm
VVS1 = VVS2 = 3 V
Tamb = 25°C
VPWR_H = AVCC
fRF = 315 MHz
RR_PWR = 30 kΩ
RLopt = 0.38 kΩ
3.6
Output power 3
fRF = 433.92 MHz
RR_PWR = 27 kΩ
RLopt = 0.36 kΩ
8.5
10
11.5
fRF = 868.3 MHz
RR_PWR = 20 kΩ
RLopt = 0.22 kΩ
RF_OUT matched to RLopt//
j/(2 × π × fRF × 1.0 pF)
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
78
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
3.7
3.8
3.9
3.10
Supply current TX
mode power amplifier
ON 3
10 dBm
4.1
4.2
4.3
Symbol
PA on/10dBm
fRF = 315 MHz
17, 18,
27
IS_TX_PAON3
fRF = 433.92 MHz
17, 18,
27
fRF = 868.3 MHz
Unit
Type*
15.7
mA
B
IS_TX_PAON3
15.8
mA
B
17, 18,
27
IS_TX_PAON3
17.3
mA
B
(10)
∆PREF
–0.8
–1.5
dB
B
Tamb = –40°C to +105°C
Pout = PREFX + ∆PREF
x = 1, 2 or 3
Output power variation
V
= VVS2 = 3.0V
for full temperature and VS1
VVS1 = VVS2 = 2.7V
supply voltage range
Noise floor power
amplifier
Min.
Typ.
Max.
(10)
∆PREF
–2.5
dB
B
VVS1 = VVS2 = 2.4V
(10)
∆PREF
–3.5
dB
C
VVS1 = VVS2 = 2.15V
(10)
∆PREF
–4.5
dB
B
10
ZRF_OUT_RX
(36 – j502)
Ω
C
10
ZRF_OUT_RX
(19 – j366)
Ω
C
10
ZRF_OUT_RX
(2.8 – j141)
Ω
C
At ±10 MHz/at 5 dBm
fRF = 868.3 MHz
(10)
LTX10M
–125
dBC/Hz
C
fRF = 433.92 MHz
(10)
LTX10M
–126
dBC/Hz
C
fRF = 315 MHz
(10)
LTX10M
–128
dBC/Hz
C
kHz
C
fRF = 315 MHz
Impedance RF_OUT in
fRF = 433.92 MHz
RX mode
fRF = 868.3 MHz
3.11 ASK modulation rate
4
Pin(1)
Test Conditions
This corresponds to
10 kBaud Manchester coding
and 20 kBaud NRZ coding
fData_ASK
1
10
Full-duplex Mode fRF = 315 MHz and fRF = 433.92 MHz
Supply current
FD mode 1
Pout = –10 dBm
RR_PWR = 22 kΩ
PWSET=13
Load optimized for
+5 dBm!
17,18,
27
IS_FD1
11.9
mA
B
Supply current
FD mode 2
Pout = –5 dBm
RR_PWR = 22 kΩ
PWSET=20
Load optimized for
+5 dBm!
17,18,
27
IS_FD2
12.5
mA
B
Supply current
FD mode 3
Pout = 0 dBm
RR_PWR = 22 kΩ
PWSET=27
Load optimized for
+5 dBm!
17,18,
27
IS_FD3
13.7
mA
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
79
4829C–RKE–09/05
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
Test Conditions
Pin(1)
Symbol
Supply current
FD mode 4
Pout = 5 dBm
RR_PWR = 22 kΩ
PWSET=31
Load optimized for
+5 dBm!
17,18,
27
IS_FD4
Input sensitivity FD
mode
VVS1 = VVS2 = 3 V
Tamb = 25°C,
PER = 5%
P([email protected]):
–30 dBm
–35 dBm
–40 dBm
–45 dBm
–50 dBm
Baud rate 5 kBaud
(4)
SREFRX_FD
Sensitivity change
FD mode
VVS1 = VVS2 = 2.15V to 3.6V
Coupling Phase 0° to 360°
Tamb = –40°C to +105°C
Frequency offset max.
±50 kHz
S = SREFRX_FD + ∆SREFRX_FD
(4)
4.7
Output Power FD1
VVS1 = VVS2 = 3V
Tamb = 25°C
RR_PWR = 22 kΩ
PWSET = 13
Load optimized for
+5 dBm!
No. Parameters
4.4
Min.
Typ.
Max.
15.2
Unit
Type*
mA
B
dBm
B
–88.5
–93.5
–97.5
–100.5
–101.5
–91
–96
–100
–103
–104
–92.5
–97.5
–101.5
–104.5
–105.5
∆SREFRX_FD
–3
0
5
dB
B
(10)
PREFTX_FD1
–12.5
–10
–7.5
dBm
B
4.8
Output Power FD1
variation for full
temperature range
VVS1 = VVS2 = 3V
Tamb = –40°C to 105°C
RR_PWR = 22 kΩ
PWSET = 13
P = PREFTX_FD1 + ∆PREFTX_FD1
(10)
∆PREFTX_FD1
–3
–1.5
2
dB
B
4.9
VVS1 = VVS2 = 2.15V to 3.6V
Output Power FD1
Tamb = –40°C to 105°C
variation for full
R
= 22 kΩ
temperature and supply R_PWR
PWSET = 13
voltage range
P = PREFTX_FD1 + ∆PREFTX_FD1
(10)
∆PREFTX_FD1
–5.5
2.5
dB
B
(10)
PREFTX_FD2
–7.5
–2.5
dBm
B
4.5
4.6
4.10 Output Power FD2
VVS1 = VVS2 = 3V
Tamb = 25°C
RR_PWR = 22 kΩ
PWSET = 20
Load optimized for
+5 dBm!
–5
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
80
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
VVS1 = VVS2 = 3V
Tamb = –40°C to 105°C
RR_PWR = 22 kΩ
PWSET = 20
P = PREFTX_FD2 + ∆PREFTX_FD2
(10)
∆PREFTX_FD2
–2.5
–1.2
1
dB
B
VVS1 = VVS2 = 2.15V to 3.6V
Output Power FD2
Tamb = –40°C to 105°C
variation for full
R
= 22 kΩ
4.12
temperature and supply R_PWR
PWSET = 20
voltage range
P = PREFTX_FD2 + ∆PREFTX_FD2
(10)
∆PREFTX_FD2
–4.5
1.5
dB
B
4.13 Output Power FD3
VVS1 = VVS2 = 3V
Tamb = 25°C
RR_PWR = 22 kΩ
PWSET = 27
Load optimized for
+5 dBm!
(10)
PREFTX_FD3
–2.5
0
2.5
dBm
B
Output Power FD3
4.14 variation for full
temperature range
VVS1 = VVS2 = 3V
Tamb = –40°C to 105°C
RR_PWR = 22 kΩ
PWSET = 27
P = PREFTX_FD3 + ∆PREFTX_FD3
(10)
∆PREFTX_FD3
–1.5
–0.8
0.5
dB
B
VVS1 = VVS2 = 2.15V to 3.6V
Output Power FD3
Tamb = –40°C to 105°C
variation for full
R
= 22 kΩ
4.15
temperature and supply R_PWR
PWSET = 27
voltage range
P = PREFTX_FD3 + ∆PREFTX_FD3
(10)
∆PREFTX_FD3
–4.5
1
dB
B
4.16 Output Power FD4
VVS1 = VVS2 = 3V
Tamb = 25°C
RR_PWR = 22 kΩ
PWSET = 31
Load optimized for
+5 dBm!
(10)
PREFTX_FD4
3.5
5
6.5
dBm
B
Output Power FD4
4.17 variation for full
temperature range
VVS1 = VVS2 = 3V
Tamb = –40°C to 105°C
RR_PWR = 22 kΩ
PWSET = 31
P = PREFTX_FD4 + ∆PREFTX_FD4
(10)
∆PREFTX_FD4
–1.5
–0.8
0.5
dB
B
VVS1 = VVS2 = 2.15V to 3.6V
Output Power FD4
Tamb = –40°C to 105°C
variation for full
R
= 22 kΩ
4.18
temperature and supply R_PWR
PWSET = 31
voltage range
P = PREFTX_FD4 + ∆PREFTX_FD4
(10)
∆PREFTX_FD4
–4.5
1
dB
B
No. Parameters
Test Conditions
Output Power FD2
4.11 variation for full
temperature range
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
81
4829C–RKE–09/05
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
5
5.1
Test Conditions
Pin(1)
Pulling at nominal
temperature and supply
voltage
fXTAL = resonant frequency of
the XTAL
C0 ≥ 1.0 pF
Rm ≤ 120Ω
24, 25
Symbol
Min.
Typ.
Max.
Unit
Type*
∆fXTO1
–50
–100
fXTAL
+50
+100
ppm
A
ms
B
800
µs
A
3.8
pF
D
21.2
pF
B
+2
ppm
C
XTO
Pulling XTO due to
XTO, CL1 and CL2
tolerances
Cm ≤ 7.0 fF
Cm ≤ 14 fF
5.2
At start-up, after start-up the
Transconductance XTO
amplitude is regulated to
at start
VPPXTAL
5.3
XTO start-up time
C0 ≤ 2.2 pF
Cm < 14 fF
Rm ≤ 120Ω
24, 25 TPWR_ON_IRQ_1
5.4
Maximum C0 of XTAL
Required for stable operation
with internal load capacitors
24, 25
C0max
5.5
Internal capacitors
CL1 and CL2
24, 25
CL1, CL2
14.8
5.6
1.0 pF ≤ C0 ≤ 2.2 pF
Pulling of radio
Cm = ≤ 14 fF
frequency fRF due to
Rm ≤ 120Ω
XTO, CL1 and CL2
PLL adjusted with FREQ at
versus temperature and
nominal temperature and
supply changes
supply voltage
4, 10
∆fXTO2
–2
V(XTAL1, XTAL2)
peak-to-peak value
24, 25
VPPXTAL
700
mVpp
C
V(XTAL1)
peak-to-peak value
24
VPPXTAL
350
mVpp
C
24, 25
gm, XTO
19
300
18 pF
Cm = 5 fF, C0 = 1.8 pF
Rm =15 Ω
5.7
Amplitude XTAL after
start-up
5.8
Real part of XTO
impedance at start-up
C0 ≤ 2.2 pF, small signal start
impedance, this value is
important for crystal
oscillator startup
24, 25
ReXTO
–2000
–1500
Ω
B
5.9
Maximum series
resistance Rm of XTAL
after start-up
C0 ≤2.2 pF
Cm ≤14 fF
24, 25
Rm_max
15
120
Ω
B
5.10
Nominal XTAL load
resonant frequency
fRF = 868.3 MHz
fRF = 433.92 MHz
fRF = 315 MHz
24, 25
fXTAL
13.41191
13.25311
12.73193
MHz
MHz
MHz
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
82
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
Pin(1)
Symbol
30
fCLK
fRF = 868.3 MHz
CLK division ratio = 3
CLK has nominal 50% duty
cycle
30
fCLK
5.11 External CLK frequency fRF = 433.92 MHz
CLK division ratio = 3
CLK has nominal 50% duty
cycle
30
fRF = 315 MHz
CLK division ratio = 3
CLK has nominal 50% duty
cycle
VDC(XTAL1, XTAL2)
XTO running
(IDLE mode, RX mode and
TX mode)
No. Parameters
DC voltage after
5.12
start-up
6
Test Conditions
Min.
Typ.
Max.
Unit
Type*
MHz
D
4.471
MHz
D
fCLK
4.418
MHz
D
30
fCLK
4.244
MHz
D
24, 25
VDCXTO
–30
me
C
19
SETPWR
45.8
kΩ
B
19
SETPWRTOL
f XTO
f CLK = ---------3
–150
Programmable Internal Resistor SETPWR
SETPWR = 800Ω +
(31 – PWSET) × 3 kΩ
6.1
SETPWR in
TX- and FD mode
6.2
Tolerance of SETPWR
versus temperature and
supply voltage range
7
7.1
PWSET = 16
(see Table 12-25 on page
43)
–20%
±500Ω
+20%
±500Ω
B
Synthesizer
Spurious TX mode
At ±fCLK, CLK enabled
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
SPTX
At ±fXTO
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
SPTX
< –75
< –75
–74
–73
–70
–65
dBC
dBC
A
A
B
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
83
4829C–RKE–09/05
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
7.2
Spurious RX mode
Test Conditions
Pin(1)
Symbol
At ±fCLK, CLK enabled
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
SPRX
At ±fXTO
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
SPRX
LTX20k
Min.
Typ.
Max.
< –75
< –75
< –75
Unit
dBC
–74
–72
–68
Type*
A
A
B
dBC
A
dBC/Hz
A
7.3
In loop phase noise
TX mode
Measured at 20 kHz distance
to carrier
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
7.4
Phase noise at 1M
RX mode
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
LRX1M
–121
–120
–113
dBC/Hz
A
7.5
Phase noise at 1M
TX mode
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
LTX1M
–113
–111
–108
dBC/Hz
A
7.6
Phase noise at 10M
RX mode
Noise floor
LRX10M
< –132
dBC/Hz
B
7.7
Loop bandwidth PLL
TX mode
Frequency where the
absolute value loop gain is
equal to 1
fLoop_PLL
70
kHz
B
7.8
Frequency deviation
TX mode
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fDEV_TX
±18.65
±19.41
±19.64
kHz
D
7.9
Frequency resolution
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
∆fStep_PLL
777.1
808.9
818.6
Hz
D
kHz
B
7.10 FSK modulation rate
8
8.1
4, 10
This corresponds to
20 kBaud Manchester coding
and 40 kBaud NRZ coding
fData_FSK
–83
–78
–73
1
20
RX/TX Switch
Impedance RX mode
RX mode, pin 38 with short
connection to GND,
fRF = 0 Hz (DC)
39
ZSwitch_RX
23000
Ω
A
fRF = 315 MHz
39
ZSwitch_RX
(11.3 – j214)
Ω
C
fRF = 433.92 MHz
39
ZSwitch_RX
(10.3 – j153)
Ω
C
fRF = 868.3 MHz
39
ZSwitch_RX
(8.9 – j73)
Ω
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
84
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
17. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and VVS2
= 4.4V to 5.6V, VVSINT = 4.4V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C,
fRF = 433.92 MHz (battery application) unless otherwise specified. Details about current consumption, timing and digital pin properties
can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
8.2
9
Impedance TX mode
Pin(1)
Symbol
TX mode, pin 38 with short
connection to GND,
fRF = 0Hz (DC)
39
ZSwitch_TX
fRF = 315 MHz
39
fRF = 433.92 MHz
fRF = 868.3 MHz
Test Conditions
Min.
Typ.
Max.
Unit
Type*
5
Ω
A
ZSwitch_TX
(4.8 + j3.2)
Ω
C
39
ZSwitch_TX
(4.5 + j4.3)
Ω
C
39
ZSwitch_TX
(5 + j9)
Ω
C
5.25
V
A
Microcontroller Interface
27, 28,
29, 30,
31, 32,
33, 34,
35
9.1
Voltage range for
microcontroller
interface
9.2
fCLK < 4.5 MHz
CL = 10 pF
CLK output rise and fall CL = Load capacitance on
time
pin CLK
2.15V ≤ VVSINT ≤ 5.25V
20% to 80% VVSINT
30
2.15
trise
20
30
ns
B
tfall
20
30
ns
B
CLK enabled
9.3
9.4
( C CLK + C L ) × V VSINT × f XTO
I VSINT = --------------------------------------------------------------------------3
CLK disabled
Current consumption of
the microcontroller
CL = Load capacitance on
interface
pin CLK
(All interface pins, except pin
CLK, are in stable conditions
and unloaded)
Internal equivalent
capacitance
Used for current calculation
27
30, 27
IVSINT
CCLK
B
< 10 µA
8
pF
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 7-1 on page 11 with
component values according to Table 7-2 on page 12 (RFIN) and RF_OUT matched to 50Ω according to Figure 7-12 on
page 22 with component values according to Table 7-7 on page 22 (RFOUT).
85
4829C–RKE–09/05
18. Electrical Characteristic: Battery Application
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.15V to 3.6V typical values at VVS1 = VVS2 = 3V and
Tamb = 25°C. Application according to Figure 3-1 on page 6 or Figure 5-1 on page 8. fRF = 315.0 MHz/ 433.92 MHz/868.3 MHz unless
otherwise specified. Microcontroller interface current IVSINT has to be added.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS1
IIDLE_VS1,2 or
IRX_VS1,2 or
IStartup_PLL_VS1,2 or
ITX_VS1,2 or
IFD1,2_VS1,2
VS2
10
Battery Application
10.1
Supported voltage
range (every mode
except high power TX
mode)
battery application
PWR_H = GND
17, 18
VVS1, VVS2
2.15
3.6
V
A
10.2
Supported voltage
range (high power TX
mode)
battery application
PWR_H = AVCC
17, 18
VVS1, VVS2
2.7
3.6
V
A
10.3
Supply voltage for
microcontroller
interface
27
VVSINT
2.15
5.25
V
A
10.4
Supply current
OFF mode
17,18,
27
IS_OFF
2
350
nA
A
17, 18
IIDLE_VS1, 2
330
570
µA
A
270
490
µA
B
VVS1,2 = VVSINT ≤ 3.6VIS
+
IOFF_VSINT
_OFF = IOFF_VS1,2
VVS1 = VVS2 ≤ 3V
10.5
Current in IDLE mode
on pin VS1 and VS2
CLK enabled
CLK disabled
10.6
Supply current
IDLE mode
CLK enabled
17,
18, 27
IS_IDLE
10.7
Current in RX mode
on pin VS1and VS2
VVS1 = VVS2 ≤ 3V
17, 18
IRX_VS1, 2
10.8
Supply current
RX mode
CLK enabled
17,
18, 27
IS_RX
10.9
Current during
TStartup_PLL on pin VS1
and VS2
VVS1 = VVS2 ≤ 3V
17, 18
IStartup_PLL_VS1, 2
10.10
Current in
RX polling mode on
pin VS1 and VS2
10.11
Supply current
RX polling mode
I
Poll
IS_IDLE = IIDLE_VS1,2 + IVSINT
10.5
14
mA
A
IS_RX = IRX_VS1, 2 + IVSINT
8.8
11.5
mA
C
× T
+I
× T
+I
× (T
+T
)
I
IDLE_VS1,2
Sleep Startup_PLL_VS1,2
Startup_PLL RX_VS1,2
Startup_Sig_Proc
Bit check
= ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------T
+T
+T
+T
Sleep
Startup_PLL
Startup_Sig_Proc
Bitcheck
17,
18, 27
IS_Poll
IPoll = IP + IVSINT
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
86
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
18. Electrical Characteristic: Battery Application (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.15V to 3.6V typical values at VVS1 = VVS2 = 3V and
Tamb = 25°C. Application according to Figure 3-1 on page 6 or Figure 5-1 on page 8. fRF = 315.0 MHz/ 433.92 MHz/868.3 MHz unless
otherwise specified. Microcontroller interface current IVSINT has to be added.
No.
Parameters
Test Conditions
10.12
Current in TX mode
on pin VS1 and VS2
VVS1 = VVS2 ≤ 3V
315 MHz/5 dBm
315 MHz/10 dBm
433.92 MHz/5 dBm
433.92 MHz/10 dBm
868.3 MHz/5 dBm
868.3 MHz/10 dBm
10.13
Supply current
TX mode
Pin
Symbol
Min.
Typ.
Max.
10.3
15.7
10.5
15.8
11.2
17.3
13.4
20.5
13.5
20.5
14.5
22.5
Unit
Type*
mA
B
17, 18
ITX_VS1_VS2
17,
18, 27
IS_TX
Current in Full-duplex
mode
Pout = –10 dBm
VVS1 = VVS2 ≤ 3V
RR_PWR = 22 kΩ
PWSET = 13
Load optimized for
+5 dBm!
17,
18, 27
IFD1_VS1_VS2
11.9
16.5
mA
B
Current in Full-duplex
mode
Pout = –5 dBm
VVS1 = VVS2 ≤ 3V
RR_PWR = 22 kΩ
PWSET= 20
Load optimized for
+5 dBm!
17,
18, 27
IFD2_VS1_VS2
12.5
17.4
mA
B
11.3
Current in Full-duplex
mode
Pout = 0 dBm
VVS1 = VVS2 ≤ 3V
RR_PWR = 22 kΩ
PWSET = 27
Load optimized for
+5 dBm!
17,
18, 27
IFD3_VS1_VS2
13.7
18.3
mA
B
11.4
Supply current
Full-duplex mode
17,
18, 27
IS_FD
11
11.1
11.2
IS_TX = ITX_VS1_VS 2 + IVSINT
Full-duplex Mode
IS_FD = IFD1,2,3_VS1_VS2 + IVSINT
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
87
4829C–RKE–09/05
19. Electrical Characteristics: Car Application
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS2 = 4.4V to 5.6V, VVSINT = 4.4V to 5.25V. Typical values at
VVS2 = 5V and Tamb = 25°C. Application according to Figure 4-1 on page 7. fRF = 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise
specified. Microcontroller interface current IVSINT has to be added.
No.
Parameters
12
Car Application
12.1
Supported voltage
range
12.2
Supply voltage for
microcontrollerinterface
12.3
Supply current
OFF mode
Test Conditions
Pin
Symbol
Min.
Typ.
IIDLE_VS2 or
IRX_VS2 or
IStartup_PLL_VS2 or
ITX_VS2 or
IFD3,4_VS2
Car application
VVS2 = VVSINT ≤ 5.25VIS
+
IOFF_VSINT
_OFF = IOFF_VS2
Max.
Unit
Type*
VS2
17
VVS2
4.4
5.6
V
A
27
VVSINT
2.15
5.25
V
A
17,27
IS_OFF
0.5
6
µA
A
17
IIDLE_VS2
430
600
µA
A
360
520
µA
B
VVS2 ≤5V
12.4
Current in IDLE mode
on pin VS2
CLK enabled
CLK disabled
12.5
Supply current IDLE
mode
CLK enabled
17,
27
IS_IDLE
IS_IDLE = IIDLE_VS2 + IVSINT
12.6
Current in RX mode
on pin VS2
VVS2 = 5V
17
IRX_VS2
10.8
12.7
Supply current RX
mode
CLK enabled
17,
27
IS_RX
12.8
Current during
TStartup_PLL on pin VS2
VVS2 = 5V
17
IStartup_PLL_VS2
12.9
Current in
RX Polling mode on
pin VS2
12.10
Supply current RX
polling mode
12.11
Current in TX mode
on pin VS2
12.12
Supply current TX
mode
14.5
mA
B
IS_RX = IRX_VS2 + IVSINT
9.1
12
mA
C
I IDLE_VS2 × T Sleep + I Startup_PLL_VS2 × T Startup_PLL + I RX_VS2 × ( T Startup_Sig_Proc + T Bit check )
I Poll "" = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------T Sleep + T Startup_PLL + T Startup_Sig_Proc + T Bit check
17,
27
VVS2 = 5V
315 MHz/5dBm
315 MHz/10dBm
433.92 MHz/5dBm
433.92 MHz/10dBm
868.3 MHz/5dBm
868.3 MHz/10dBm
IS_Poll
17
ITX_VS2
17,
27
IS_TX
IS_Poll = IPoll + IVSINT
10.7
16.2
10.9
16.3
11.6
17.8
13.9
21.0
14.0
21.0
15.0
23.0
mA
B
IS_TX = ITX_VS2 + IVSINT
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
88
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
19. Electrical Characteristics: Car Application (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS2 = 4.4V to 5.6V, VVSINT = 4.4V to 5.25V. Typical values at
VVS2 = 5V and Tamb = 25°C. Application according to Figure 4-1 on page 7. fRF = 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise
specified. Microcontroller interface current IVSINT has to be added.
No.
Parameters
13
Full-duplex Mode
Test Conditions
Pin
Symbol
Current in Full-duplex
mode
Pout = –5 dBm
VVS2 = 5V
RR_PWR = 22 kΩ
PWSET = 19
Load optimized for
+5 dBm!
17,
27
Current in Full-duplex
mode
Pout = 0 dBm
VVS2 = 5V
RR_PWR = 22 kΩ
PWSET = 26
Load optimized for
+5 dBm!
13.3
Current in Full-duplex
mode
Pout = 5 dBm
VVS2 = 5V
RR_PWR = 22 kΩ
PWSET = 31
Load optimized for
+5 dBm!
13.4
Supply current
Full-duplex mode
13.1
13.2
Min.
Typ.
Max.
Unit
Type*
IFD4_VS2
12.7
16.9
mA
B
17,
27
IFD5_VS2
13.8
18.4
mA
B
17,
27
IFD6_VS2
15.6
20.8
mA
B
17,
27
IS_FD
IS_FD = IFD4,5,6_VS2 + IVSINT
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
89
4829C–RKE–09/05
20. Digital Timing Characteristics
All parameters refer to GND and are valid for Tamb = –40°C to +105°C. VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and
VVS2 = VVSINT = 4.4V to 5.25V (car application), typical values at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C unless otherwise specified.
No.
Parameters
14
Basic Clock Cycle of the Digital Circuitry
14.1
Test Conditions
Basic clock cycle
Pin
Symbol
Min.
TDCLK
Typ.
Max.
Unit
Type*
16/fXTO
16/fXTO
µs
A
8
4
2
1
× TDCLK
8
4
2
1
× TDCLK
µs
A
16
8
4
2
× TDCLK
16
8
4
2
× TDCLK
µs
A
Sleep ×
XSleep×
1024 ×
TDCLK
Sleep ×
XSleep×
1024 ×
TDCLK
ms
A
798.5 ×
TDCLK
µs
A
XLIM = 0
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
14.2
Extended basic clock
cycle
TXDCLK
XLIM = 1
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
15
RX Mode/RX Polling Mode
Sleep and XSleep are
defined in control
register 4
15.1
Sleep time
15.2
Start-up PLL RX mode From IDLE mode
15.3
15.4
Start-up signal
processing
Time for Bit-check
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
TSleep
798.5 ×
TDCLK
TStartup_PLL
TStartup_Sig_Proc
930
546
354
258
× TDCLK
TBit_check
3/fSignal
6/fSignal
9/fSignal
930
546
354
258
× TDCLK
A
Average time during
polling. No RF signal
applied.
fSignal = 1/(2 × tee)
Signal data rate
Manchester
(Lim_min and Lim_max
up to ±50% of tee,
see Figure 14-3 on page
55)
Bit-check time for a valid
input signal fSignal
NBit-check = 0
NBit-check = 3
NBit-check = 6
NBit-check = 9
1/fSignal
3.5/fSignal
6.5/fSignal
9.5/fSignal
ms
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
90
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
20. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C. VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and
VVS2 = VVSINT = 4.4V to 5.25V (car application), typical values at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C unless otherwise specified.
No.
15.5
Parameters
Test Conditions
Baud-rate range
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Pin
Symbol
BR_Range
Min.
Typ.
Max.
Unit
Type*
kBaud
A
µs
A
500
250
125
62.5
µs
B
331.5
× TDCLK
µs
A
2.5
5.0
10.0
20.0
1.0
2.0
4.0
8.0
XLIM = 0
15.6
Minimum time period
between edges at pin
SDO_TMDO in RX
transparent mode
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
31
TDATA_min
10 ×
TXDCLK
TDATA
200
100
50
25
XLIM = 1
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
15.7
16
16.1
17
Edge-to-edge time
period of the data signal
for full sensitivity in RX
mode
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
TX Mode
Start-up time
From IDLE mode
331.5
× TDCLK
TStartup
Configuration of the Transceiver with 4-wire Serial Interface
17.1
CS set-up time to rising
edge of SCK
17.2
SCK cycle time
17.3
SDI_TMDI set-up time
to rising edge of SCK
17.4
33, 35
TCS_setup
1.5
× TDCLK
µs
A
33
TCycle
2
µs
A
32, 33
TSetup
250
ns
C
SDI_TMDI hold time
from rising edge of SCK
32, 33
THold
250
ns
C
17.5
SDO_TMDO enable
time from rising edge of
CS
31, 35
TOut_enable
250
ns
C
17.6
SDO_TMDO output
delay from falling edge
of SCK
31, 35
TOut_delay
250
ns
C
17.7
SDO_TMDO disable
time from falling edge of
CS
31, 33
TOut_disable
250
ns
C
17.8
CS disable time period
35
TCS_disable
1.5
× TDCLK
µs
A
17.9
Time period SCK low to
CS high
33, 35
TSCK_setup1
250
ns
C
CL = 10 pF
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
91
4829C–RKE–09/05
20. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C. VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and
VVS2 = VVSINT = 4.4V to 5.25V (car application), typical values at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C unless otherwise specified.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
17.10
Time period SCK low to
CS low
33, 35
TSCK_setup2
250
ns
C
17.11
Time period CS low to
SCK high
33, 35
TSCK_hold
250
ns
C
ms
B
µs
A
18
18.1
Start Time Push Button N_PWR_ON and PWR_ON
Timing of wake-up via PWR_ON or N_PWR_ON
PWR_ON high to
positive edge on pin
IRQ (Figure 12-4 on
page 46)
From OFF mode to
IDLE mode, applications
according to Figure 3-1
on page 6, Figure 4-1
on page 7, Figure 5-1
on page 8 and Figure
6-1 on page 9
XTAL:
Cm < 14 fF (typ. 5 fF)
C0 < 2.2 pF (typ. 1.8 pF)
Rm ≤ 120Ω (typ. 15Ω)
battery application
C1 = C2 = C3 = 68 nF
C5 = C7 = 10 nF
0.3
29, 40
TPWR_ON_IRQ_1
0.45
car application
C1 = C3 = C4 = 68 nF
C2 = 2.2 µF
C5 = 10 nF
18.2
PWR_ON high to
positive edge on pin
IRQ (Figure 12-4 on
page 46)
From every mode
except OFF mode
29, 40
0.8
TPWR_ON_IRQ_2
1.3
2 × TDCLK
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
92
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
20. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C. VVS1 = VVS2 = VVSINT = 2.15V to 3.6V (battery application), and
VVS2 = VVSINT = 4.4V to 5.25V (car application), typical values at VVS1 = VVS2 = VVSINT = 3V and Tamb = 25°C unless otherwise specified.
No.
18.3
Parameters
N_PWR_ON low to
positive edge on pin
IRQ (Figure 12-2 on
page 44)
Test Conditions
Pin
Symbol
Min.
Push button debounce
time
Max.
0.3
0.8
Unit
Type*
ms
B
From OFF mode to
IDLE mode, applications
according to Figure 3-1
on page 6, Figure 4-1
on page 7, Figure 5-1
on page 8 and Figure
6-1 on page 9
XTAL:
Cm < 14 fF (typ 5 fF)
C0 < 2.2 pF (typ 1.8 pF)
Rm ≤ 120Ω (typ 15Ω)
battery application
C1 = C2 = 68 nF
C3 = C4 = 68 nF
C5 = 10 nF
29, 45
TN_PWR_ON_IRQ
0.45
car application
C1 = C4 = 68 nF
C2 = C3 = 2.2 µF
C5 = 10 nF
18.4
Typ.
Every mode except OFF
29, 45
mode
1.3
TDebounce
8195
× TDCLK
8195
× TDCLK
µs
A
TStartup_PLL_fd
798.5
× TDCLK
798.5
× TDCLK
µs
A
TStartup_Sig_Proc_fd
546
× TDCLK
546
× TDCLK
µs
A
TBIT_fd
168
× TDCLK
168
× TDCLK
µs
A
19
Full-duplex Mode
19.1
Start-up PLL in
Full-duplex mode
From IDLE mode
19.2
Start-up signal
processing FD mode
Data rate is fixed for
full-duplex operation
19.3
Time per information Bit Data rate is fixed for
in Full-duplex mode
full-duplex operation
19.4
Switch OFF Delay
Time from last
transmitted bit to switch
of the power amplifier
TDelay
168
× TDCLK
168
× TDCLK
µs
A
Synchronization Time
Time after startbit
detection to begin of
payload data
transmission
TSync
24
× TBIT-fd
24
× TBIT-fd
µs
A
19.5
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
93
4829C–RKE–09/05
21. Digital Port Characteristics
All parameter refer to GND and valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.15V to 3.6V (battery application) and VVS2 = 4.4V to
5.25V (car application) typical values at VVS1 = VVS2 = 3V (battery application) and Tamb = 25°C unless otherwise specified.
VVSINT = 2.15V to 5.25V can be used independent from VVS1 and VVS2 in the case the microcontroller uses an different supply voltage.
No.
Parameters
20
Digital Ports
20.1
20.2
20.3
Test Conditions
Pin
Symbol
CS input
V
= 2.15V to 5.25V
- low level input voltage VSINT
35
VIl
- high level input voltage VVSINT = 2.15V to 5.25V
35
VIh
SCK input
V
= 2.15V to 5.25V
- low level input voltage VSINT
33
VIl
- high level input voltage VVSINT = 2.15V to 5.25V
33
VIh
SDI_TMDI input
V
= 2.15V to 5.25V
- low level input voltage VSINT
32
VIl
- high level input voltage VVSINT = 2.15V to 5.25V
32
VIh
Min.
Typ.
Max.
Unit
Type*
0.2
× VVSINT
V
A
V
A
V
A
V
A
V
A
V
A
0.8
× VVSINT
0.2
× VVSINT
0.8
× VVSINT
0.2
× VVSINT
0.8
× VVSINT
20.4
TEST1 input
TEST1 input must
always be directly
connected to GND
20
0
0
V
20.5
TEST2 input
TEST2 input must
always be direct
connected to GND
23
0
0
V
0.2
× VVSINT
V
A
V
A
V
A
V
A
0.2
× VDVCC
V
A
VDVCC
V
A
0.2
× VDVCC
V
A
VDVCC
V
A
0.2
× VDVCC
V
A
VDVCC
V
A
20.6
20.7
20.8
20.9
20.10
PWR_ON input
V
= 2.15V to 5.25V
- low level input voltage VSINT
40
VIl
- high level input voltage VVSINT = 2.15V to 5.25V
40
VIh
VVSINT = 2.15V to 5.25V
N_PWR_ON input
Internal pull-up resistor
- low level input voltage
of 50 kΩ ±20%
45
VIl
VVSINT = 2.15V to 5.25V
- high level input voltage Internal pull-up resistor
of 50 kΩ ±20%
45
VIh
CS_POL input
-low level input voltage
22
VIl
- high level input voltage
22
VIh
SCK_POL input
- low level input voltage
43
VIl
- high level input voltage
43
VIh
SCK_PHA input
- low level input voltage
44
VIl
- high level input voltage
44
VIh
0.8
× VVSINT
0.2
× VVSINT
0.8
× VVSINT
0.8
× VDVCC
0.8
× VDVCC
0.8
× VDVCC
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
94
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
21. Digital Port Characteristics (Continued)
All parameter refer to GND and valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.15V to 3.6V (battery application) and VVS2 = 4.4V to
5.25V (car application) typical values at VVS1 = VVS2 = 3V (battery application) and Tamb = 25°C unless otherwise specified.
VVSINT = 2.15V to 5.25V can be used independent from VVS1 and VVS2 in the case the microcontroller uses an different supply voltage.
No.
20.11
20.12
20.13
Parameters
Pin
Symbol
433_N868 input
- low level input voltage
6
VIl
- high level input voltage
6
VIh
PWR_H input
- low level input voltage
9
VIl
- high level input voltage
9
VIh
VVSINT = 2.15V to 5.25V
SDO_TMDO output
- saturation voltage low ISDO_TMDO = 250 µA
31
Vol
VVSINT = 2.15V to 5.25V
ISDO_TMDO = –250 µA
31
Voh
IRQ output
VVSINT = 2.15V to 5.25V
- saturation voltage low IIRQ = 250 µA
29
Vol
VVSINT = 2.15V to 5.25V
IIRQ = –250 µA
29
Voh
VVSINT = 2.15V to 5.25V
ICLK = 100 µA
CLK output
internal series resistor of
- saturation voltage low
1 kΩ for spurious
reduction in PLL
30
Vol
VVSINT = 2.15V to 5.25V
ICLK = –100 µA
- saturation voltage high internal series resistor of
1 kΩ for spurious
reduction in PLL
30
Voh
POUT output
VVSINT = 2.15V to 5.25V
- saturation voltage low IPOUT = 250 µA
28
Vol
0.15
POUT output
VVSINT = 5V
- saturation voltage low IPOUT = 1000 µA
28
Vol
0.4
POUT output
VVSINT = 2.15V to 5.25V
- saturation voltage high IPOUT = –1500 µA
28
Voh
RX_ACTIVE output
I
= 25 µA
- saturation voltage low RX_ACTIVE
46
Vol
RX_ACTIVE output
I
= –1500 µA
- saturation voltage high RX_ACTIVE
46
Voh
- saturation voltage high
20.14
- saturation voltage high
20.15
20.16
20.17
20.18
TEST3 output
Test Conditions
TEST3 output must
always be directly
connected to GND
34
Min.
Typ.
1.7
1.7
0.15
VVSINT –
0.4
VVSINT –
0.4
0
0.25
V
A
AVCC
V
A
0.25
V
A
AVCC
V
A
0.4
V
B
V
B
V
B
V
B
V
B
V
B
0.4
V
B
0.6
V
B
V
B
V
B
V
B
0.4
0.4
VVSINT –
0.15
VVSINT –
0.15
0.25
VAVCC –
0.5
Type*
VVSINT –
0.15
0.15
VVSINT –
0.4
Unit
VVSINT –
0.15
0.15
VVSINT –
0.4
Max.
0.4
VAVCC –
0.15
0
V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
95
4829C–RKE–09/05
22. Ordering Information
Extended Type Number
Package
Remarks
ATA5823-PLQW
QFN48
7 mm x 7 mm, Pb-free
ATA5824-PLQW
QFN48
7 mm x 7 mm, Pb-free
23. Package Information
96
ATA5823/ATA5824
4829C–RKE–09/05
ATA5823/ATA5824
24. Table of Contents
Features ..................................................................................................... 1
Applications .............................................................................................. 2
Benefits...................................................................................................... 2
General Description .................................................................................. 2
1
Pin Configuration ..................................................................................... 3
2
Typical Key Fob Application for Bi-directional RKE ............................. 6
3
Typical Car Application for Bi-directional RKE ..................................... 7
4
Typical Key Fob Application for Full-duplex PEG ................................ 8
5
Typical Car Application for Full-duplex PEG ........................................ 9
6
RF Transceiver in Half-duplex Mode .................................................... 10
7
RF Transceiver in Full-duplex Mode .................................................... 25
8
XTO .......................................................................................................... 27
9
Power Supply ......................................................................................... 31
10 Microcontroller Interface ....................................................................... 35
11 Digital Control Logic .............................................................................. 35
12 Transceiver Configuration .................................................................... 47
13 Operation Modes .................................................................................... 52
14 Absolute Maximum Ratings .................................................................. 71
15 Thermal Resistance ............................................................................... 71
16 Electrical Characteristics: General ...................................................... 72
17 Electrical Characteristic: Battery Application ..................................... 86
18 Electrical Characteristics: Car Application ......................................... 88
19 Digital Timing Characteristics .............................................................. 90
20 Digital Port Characteristics ................................................................... 94
21 Ordering Information ............................................................................. 96
22 Package Information .............................................................................. 96
97
4829C–RKE–09/05
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