Features • • • • • • • • Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (Pout Typically 23 dBm) Ramp-controlled Output Power Low-noise Preamplifier (NF Typically 2.1 dB) Biasing for External PIN Diode T/R Switch Current-saving Standby Mode Few External Components Packages: – PSSO20 – QFN20 with Extended Performance 1. Description The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like Bluetooth® and WDCT. Bluetooth/ISM 2.4-GHz Front-End IC T7024 Due to the ramp-control feature and a very low quiescent current, an external switch transistor for VS is not required. Figure 1-1. Block Diagram RX_ON PU VS_LNA TX TX/RX/ standby Control SWITCH_OUT R_SWITCH RX LNA_OUT LNA_IN LNA RAMP V1_PA V2_PA PA_IN V3_PA_OUT PA 4533H–BLURF–07/07 2. Pin Configuration Pinning PSSO20 GND VS_LNA GND LNA_IN GND 19 RX_ON SWITCH_OUT 2 18 LNA_OUT GND 3 10 17 GND LNA_IN 4 V3_PA_OUT V3_PA_OUT V3_PA_OUT GND RAMP 16 PA_IN VS_LNA 5 T7024 GND 6 2 Pinning QFN20 20 PU R_SWITCH 1 Table 2-1. Figure 2-2. 15 V1_PA V3_PA_OUT 7 14 GND V3_PA_OUT 8 13 V2_PA V3_PA_OUT 9 12 V2_PA GND 10 11 RAMP 9 8 7 6 11 5 12 4 T7024 13 3 2 14 1 15 SWITCH_OUT R_SWITCH PU RX_ON LNA_OUT 16 17 18 19 20 V2_PA V2_PA GND V1_PA PA_IN Figure 2-1. Pin Description Pins PSSO20 Pins QFN20 Symbol 1 4 R_SWITCH 2 5 SWITCH_OUT Function Resistor to GND sets the PIN diode current Switched current output for PIN diode 3 6 GND 4 7 LNA_IN Low-noise amplifier input Ground 5 9 VS_LNA Supply voltage input for low-noise amplifier 6 8 GND 7 11 V3_PA_OUT Inductor to power supply and matching network for power amplifier output 8 12 V3_PA_OUT Inductor to power supply and matching network for power amplifier output 9 13 V3_PA_OUT Inductor to power supply and matching network for power amplifier output 10 10 GND Ground Ground 11 15 RAMP Power ramping control input 12 16 V2_PA Inductor to power supply for power amplifier 13 17 V2_PA Inductor to power supply for power amplifier 14 14 GND 15 19 V1_PA Supply voltage for power amplifier 16 20 PA_IN Power amplifier input 17 18 GND Ground 18 1 LNA_OUT 19 2 RX_ON 20 3 PU Slug Slug GND Ground Low-noise amplifier output RX active high Power-up active high Ground T7024 4533H–BLURF–07/07 T7024 3. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Supply voltage Pins VS_LNA, V1_PA, V2_PA, V3_PA_OUT VS 6 V Junction temperature Tj 150 °C Storage temperature Tstg –40 to +125 °C RF input power LNA PinLNA 5 dBm RF input power PA PinPA 10 dBm Symbol Value Unit Junction ambient PSSOP20, slug soldered on PCB RthJA 19 K/W Junction ambient QFN20, slug soldered on PCB RthJA 27 K/W Electrostatic sensitive device. Observe precautions for handling. 4. Thermal Resistance Parameters 5. Handling Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test requirement (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test requirement (MM) in accordance to EIA/JESD22-A115A. 6. Operating Range All voltages are referred to ground (pins GND and slug). Power supply points are VS_LNA, V1_PA, V2_PA, V3_PA_OUT. The table represents the sum of all supply currents depending on the TX/RX mode. Parameters Symbol Min. Typ. Max. Unit Supply voltage Pins V1_PA, V2_PA and V3_PA_OUT VS 2.7 3.0 4.6 V Supply voltage, pin VS_LNA VS 2.7 3.0 5.5 V Supply current TX, PSSO20 QFN20 Supply current RX IS IS IS 190 165 8 mA mA mA IS_standby 10 µA Standby current, PU = 0 Ambient temperature Tamb –25 +25 +85 °C 3 4533H–BLURF–07/07 7. Electrical Characteristics Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25°C Parameters Power Amplifier Test Conditions Symbol Min. VS 2.7 Typ. Max. 3.0 4.6 Unit (1) Supply voltage Pins V1_PA, V2_PA, V3_PA_OUT Supply current TX, PSSO20 TX, QFN20 IS_TX IS_TX RX (PA off), VRAMP ≤ 0.1V IS_RX 10 µA IS_standby 10 µA 2.5 GHz Standby current Standby 190 165 Frequency range TX f 2.4 Gain-control range TX ∆Gp 60 42 Power gain maximum TX, pin PA_IN to V3_PA_OUT Gp 28 30 Power gain minimum TX, pin PA_IN to V3_PA_OUT Gp –40 Ramping voltage maximum TX, power gain (maximum) Pin RAMP VRAMP max 1.7 Ramping voltage minimum TX, power gain (minimum) Pin RAMP VRAMP min Ramping current maximum TX, VRAMP = 1.75V, pin RAMP IRAMP max Power-added efficiency TX, PSSO20 TX, QFN20 PAE PAE 30 35 35 40 Saturated output power TX, input power = 0 dBm referred to pins V3_PA_OUT Psat 22 23 Input matching(2) TX, pin PA_IN Load VSWR < 1.5:1 Output matching(2) TX, pins V3_PA_OUT Load VSWR < 1.5:1 TX, pins V3_PA_OUT TX, pins V3_PA_OUT Harmonics at Psat = 23 dBm 1.75 V mA mA dB 33 dB –17 dB 1.83 V 0.1 V 0.5 mA % % 24 dBm 2 fo –30 dBc 3 fo –30 dBc IS_O_standby 1 µA RX IS_O_RX 1 µA TX at 100Ω IS_O_100 T/R Switch Driver (Current Programming by External Resistor from R_SWITCH to GND) Standby, pin SWITCH_OUT Switch-out current output IS_O_1k2 7 mA TX at 33 kΩ IS_O_33k 17 mA IS_O_R 19 mA (3) Supply voltage All, pin VS_LNA VS Supply current RX IS Notes: mA TX at 1.2 kΩ TX at ∞ Low-noise Amplifier 1.7 2.7 3.0 5.5 V 8 9 mA 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50Ω. 2. With external matching network, load impedance 50Ω. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-16 on page 11. Please note, that for RX_ON below 1.4V the T/R switch driver switches to TX mode. 4 T7024 4533H–BLURF–07/07 T7024 7. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25°C Parameters Test Conditions Supply current (LNA and control logic) TX (control logic active) Pin VS_LNA Standby current Standby, pin VS_LNA Frequency range RX Symbol Min. IS_standby RX, pin LNA_IN to LNA_OUT Gp 15 Noise figure RX, PSSO20 RX, QFN20 NF NF Gain compression RX, referred to pin LNA_OUT rd 3 -order input interception point Input matching RX (4) RX, pin LNA_IN Output matching(4) RX, pin LNA_OUT Logic Input Levels (RX_ON, PU) 0.5 mA 10 µA 2.5 GHz 16 19 dB 2.5 2.1 2.8 2.3 dB dB O1dB –9 –7 –6 dBm IIP3 –16 –14 –13 dBm VSWRin 2:1 VSWRout 2:1 (5) High input level = ‘1’ pins RX_ON and PU ViH 2.4 Low input level = ‘0’ ViL 0 High input current = ‘1’ ViH = 2.4V IiH Low input current = ‘0’ IiL Notes: Unit 1 2.4 Power gain Max. IS f (5) Typ. VS, LNA 40 V 0.5 V 60 µA 0.2 µA 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50Ω. 2. With external matching network, load impedance 50Ω. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-16 on page 11. Please note, that for RX_ON below 1.4V the T/R switch driver switches to TX mode. 8. Control Logic PA and LNA/Antenna Switch Driver PU RX_ON Ramp(1) PA LNA Antenna Switch Driver Operation Mode 0 0 0 off off off standby 0 0 1 on off off (2) 0 1 0 off on off (3) 0 1 1 on on off (4) 1 0 0 off off on (4) 1 0 1 on off on TX 1 1 0 off on off RX 1 1 1 on on off (5) Notes: 1. “0” = VRAMP ≤ 0.1V, “1” = VRAMP typically 1.75V, 1.3V < VRAMP < 1.83V controls gain and output power, compare Figure 9-6 on page 7 and Figure 9-10 on page 9 2. Only for special operation, e.g. only PA operation, no LNA/switch driver operation 3. Only for special operation, e.g. no switch driver operation 4. Only for special operation 5. Only for special operation, e.g. separate TX/RX antennas, TX and RX operation at the same time 5 4533H–BLURF–07/07 9. Typical Operating Characteristics Figure 9-1. LNA (PSSO20): Gain and Noise Figure versus Frequency 20 8 7 Gain 6 5 NF 10 4 3 5 NF (dB) Gain (dB) 15 2 1 0 2000 2200 2400 2600 0 3000 2800 Frequency (MHz) Figure 9-2. LNA (N20): Gain and Noise Figure versus Frequency 25 5 20 4 15 3 NF 10 2 5 1 0 2000 2200 2400 2600 NF (dB) Gain (dB) Gain 0 3000 2800 Frequency (MHz) Figure 9-3. LNA: NF and Gain versus Temperature 2.5 2.0 NF VS = 3 V Relative gain, relative NF (dB) 1.5 1.0 0.5 0.0 -0.5 Gain -1.0 -1.5 -2.0 -2.5 -40 -20 0 20 40 60 80 Temperature (°C) 6 T7024 4533H–BLURF–07/07 T7024 Figure 9-4. LNA: Typical Switch-out Current versus Rswitch 20 IS_O(mA) 16 12 8 4 0 1 10 100 1000 10000 100000 1000000 10000000 Rswitch(Ω) Figure 9-5. PA (PSSO20): Output Power and PAE versus Supply 50 250 40 220 PAE 30 190 Pout 20 160 f = 2.4 GHz Vramp = 1.75 V PinPA = 0 dBm 10 130 0 2.7 3.1 3.5 3.9 IS_TX (mA) Pout (dBm), PAE (%) I_S_TX 4.3 100 4.7 Supply Voltage (V) Figure 9-6. PA (PSSO20): Output Power and PAE versus Ramp Voltage 50 250 200 Pout 10 150 -10 100 IS_TX (mA) Pout (dBm), PAE (%) PAE 30 f = 2.4 GHz VS = 3 V PinPA = 0 dBm I_S_TX -30 50 -50 0 1.2 1.4 1.6 1.8 2.0 Vramp (V) 7 4533H–BLURF–07/07 PA (PSSO20): Output Power and PAE versus Input Power Pout (dBm), PAE (%), Gp (dB) 40 250 PAE Gain 30 200 20 150 I_S_TX 10 100 VS = 3 V f = 2.4 GHz Vramp = 1.75 V PinPA = 0 dBm 0 IS_TX (mA) Figure 9-7. 50 Pout -10 -40 0 -30 -20 -10 0 10 Input Power (dBm) PA (PSSO20): Output Power and PAE versus Frequency Pout (dBm), PAE (%) 50 250 I_S_TX 40 200 PAE 30 150 Pout 20 100 VS = 3 V Vramp = 1.7 V PinPA = 0 dBm 10 0 2400 2420 2440 2460 IS_TX (mA) Figure 9-8. 50 0 2500 2480 Frequency (MHz) PA (QFN20): Output Power and PAE versus Supply Voltage Pout (dBm), PAE (%) 50 250 40 220 PAE I_S_TX 30 190 Pout 20 f = 2.4 GHz Vramp = 1.8 V PinPA = 0 dBm 10 130 0 2.7 3.1 3.5 3.9 160 IS_TX (mA) Figure 9-9. 4.3 100 4.7 Supply Voltage (V) 8 T7024 4533H–BLURF–07/07 T7024 Figure 9-10. PA (QFN20) Output Power and PAE versus Ramp Voltage 50 250 Pout 30 200 10 150 -10 100 IS_TX (mA) Pout (dBm), PAE (%) PAE f = 2.4 GHz VS = 3 V PinPA = 0 dBm I_S_TX -30 50 -50 0 1.2 1.4 1.6 1.8 2.0 Vramp (V) 50 300 PAE 40 250 Gain 30 20 200 150 I_S_TX VS = 3 V f = 2.4 GHz Vramp = 1.8 V PinPA = 0 dBm 10 IS_TX (mA) Pout (dBm), PAE (%), Gp (dB) Figure 9-11. PA (QFN20): Output Power and PAE versus Input Power 100 0 50 Pout -10 -40 0 -30 -20 -10 0 10 Input Power (dBm) Figure 9-12. PA (QFN20): Output Power and PAE versus Frequency 50 250 200 I_S_TX 30 150 Pout 20 VS = 3 V Vramp = 1.8 V PinPA = 0 dBm 10 0 2400 100 IS_TX (mA) Pout (dBm), PAE (%) PAE 40 50 2420 2440 2460 2480 0 2500 Frequency (MHz) 9 4533H–BLURF–07/07 Figure 9-13. LNA: Supply Current versus Temperature Supply current (mA) 8.0 7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 -40 -20 0 20 40 60 80 Temperature (°C) Figure 9-14. PA (PSSO20): Supply Current versus Iramp and Temperature Supply current (mA) 200 180 160 -40°C 140 120 40°C 100 0°C 80 60 40 80°C 20 0 0.1 1.0 10.0 100.0 1000.0 Iramp (µA) Figure 9-15. PA (PSSO20, QFN20): Pout versus VRAMP and Temperature 30 f = 2.4 GHz VS = 3 V Pin = 0 dBm 20 Pout (dBm) 5 10 25 0 -15 80 -10 -40°C -20 1.0 1.2 1.4 1.6 1.8 Vramp (V) 10 T7024 4533H–BLURF–07/07 T7024 Figure 9-16. (PSSO20, QFN20): LNA Gain (dB) versus RX_ON (V) 20.0 15.0 10.0 Gain (dB) 5.0 VS = 3 V 0.0 -5.0 -10.0 -15.0 -20.0 -25.0 1.0 1.5 2.0 2.5 3.0 RX_ON (V) 10. Input/Output Circuits Figure 10-1. Input Circuit PA_IN/V1_PA V1_PA PA_IN GND Figure 10-2. Input Circuit RAMP/V1_PA V1_PA RAMP 11 4533H–BLURF–07/07 Figure 10-3. Input Circuit V2_PA V2_PA GND Figure 10-4. Input/Output Circuit V3_PA_OUT V3_PA_OUT GND Figure 10-5. Input Circuit SWITCH_OUT/R_SWITCH V1_PA SWITCH_OUT R_SWITCH GND 12 T7024 4533H–BLURF–07/07 T7024 Figure 10-6. Input Circuit LNA_IN/VS_LNA VS_LNA LNA_IN GND Figure 10-7. Input Circuit PU/RX_ON VS_LNA LNA_IN / PU Figure 10-8. Output Circuit LNA_OUT VS_LNA LNA_OUT GND 13 4533H–BLURF–07/07 Figure 10-9. Typical Application T7024 (PSSO20 Package) LNA OUT PA IN 5.6nH V1_PA 3.9nH RX ON 3p3 V2_PA PU 3.9p 20 19 18 17 16 15 14 13 12 11 PA ramp 1 2 3 4 5 6 7 8 9 10 T7024 harm. termination 1p5 R1 is selected with DIL-switch Pin-diode replaced by LED on application-board 14 R1 1.8p 15nH LNA IN V3_PA VS_LNA Switch Out PA OUT 0p8 Blocking capacitors depending on application T7024 4533H–BLURF–07/07 T7024 Figure 10-10. Typical Application T7024 (QFN20 Package) LNA OUT PA IN V1_PA V2_PA 2.2p 1 2 3 4 5 RX ON PU R1 is selected with DIL-switch 3p3 1p R1 Var 20 19 18 17 16 15 14 T7024 13 12 11 6 7 8 9 10 PA ramp harm. termination 2p2 0p8 1.8p 18nH LNA IN Pin-diode replaced by LED on application-board Switch Out V3_PA VS_LNA PA OUT blocking capacitors depending on application 11. Ordering Information Extended Type Number Package Remarks T7024-TRSY PSSO20 Tube, Pb-free 830 pcs. T7024-TRQY PSSO20 Taped and reeled, Pb-free 4000 pcs. T7024-PGPM QFN20 Taped and reeled Pb free, halogen free 1500 pcs. T7024-PGQM QFN20 Taped and reeled Pb free, halogen free 6000 pcs. Demoboard-T7024-PGM QFN20 Evaluation board QFN 1 Evaluation board PSSO 1 Demoboard-T7024-TR PSSO20 MOQ 15 4533H–BLURF–07/07 12. Package Information ∅ 0.4 A B 2.15 Package: PSSO20 Dimensions in mm 2.6 6.75 max. 6.45±0.15 6.7 max. 4.4±0.1 0.15 A C 0.25 0.12 0.575 0.18 max. 0.05+0.09 1.3 B 5.4±0.2 (20x) 0.65 5.85 20 A 11 technical drawings according to DIN specifications Drawing-No.: 6.543-5078.01-4 Issue: 1; 05.06.01 1 16 10 T7024 4533H–BLURF–07/07 T7024 13. Package Information PB Free Package: QFN 20 - 5 x 5 Exposed pad 3.1 x 3.1 Dimensions in mm Not indicated tolerances ± 0.05 0.9±0.1 5 +0 3.1 0.05-0.05 16 20 20 15 1 1 11 0.6 0.28 5 5 10 technical drawings according to DIN specifications 6 0.65 nom. Drawing-No.: 6.543-5094.01-4 2.6 Issue: 1; 19.12.02 17 4533H–BLURF–07/07 14. Recommended PCB Land Pattern Figure 14-1. Recommended PCB Land Pattern B E D A C F Table 14-1. Recommended PCB Land Pattern Signs Sign A Description Size Distance of vias 1.6 mm B Size of slug pattern 3.1 mm C Distance slug to pins 0.33 mm D Diameter of vias 1 mm E Width of pin pattern 0.3 mm F Distance of pin pattern 0.33 mm 15. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 18 Revision No. History 4533H-BLURF-07/07 • Put datasheet in a new template • Page 1: Block diagram changed • Page 13: Figure 10-8 changed T7024 4533H–BLURF–07/07 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support Sales Contact [email protected] www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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