Features • All-in-one Design • • • • • • • – MIDI Control Processor – Synthesis – Compatible Effects: Reverb and Chorus – Microphone Echo Processing (Two Channels) – Programmable Spatial Effect or Four-channel Surround – 4-band Stereo Equalizer High-quality Synthesis – Maximum 48-voice Polyphony and Reverb/Chorus (34 if all Features on) – 24 dB Resonant Filter per Voice – 16-bit Samples – Alternate Loop – Internal Computations on 28 Bits Crisp MIDI Response: Built-in 16-bit Processor Runs at 38.4 MHz High-quality Sound Post-processing – 13 Delay Lines for Stereo Reverb – Programmable Stereo Echo for Microphone – Spatial Effect/Surround Allows Wide Stereo Image for Strong Sound Presence Top Technology – Synthesizer Chip Set: ATSAM9703 + 32-Mbit ROM + 32K x 8 RAM + DAC or Codec – Single 9.6 MHz Crystal with Built-in PLL – 100-lead TQFP Space Saver Package Standard Firmware includes Top-quality CleanWave™ Sound Set and Other Sample Sets under Special Conditions Typical Applications: Karaokes, Musical instruments, Battery-operated Instruments Pin- and Function-compatible with ATSAM9503, with Additional Features: – Lower Consumption – 3.3V Core Supply, 3V to 5.5V Periphery Supply – Up to 8 Channels Audio-in Note: Sound Synthesis ATSAM9703 Professional Integrated Synthesizer Pin-to-pin replacement for ATSAM9503 requires 3.3V core supply VC3. Description The highly-integrated architecture of the ATSAM9703 device combines a specialized high-performance RISC digital signal processor and a general-purpose 16-bit CISC control processor on a single chip. An on-chip memory management unit allows the digital signal processor and the control processor to share external ROM and RAM devices. The ROM bus width should be 16 bits, while the SRAM can be selected to be 8 or 16 bits wide. When using an 8-bit SRAM, fast type (static cache) should be selected as two SRAM cycles will be done in one ROM cycle duration. Running at 300 million operations per second (MOPS), the digital signal processor supports high-quality PCM synthesis as well as most important functions like reverb, chorus, surround effect and equalizer. By adding an additional stereo DAC, four- channel audio surround can be obtained as well. Computer Karaoke manufacturers will enjoy the built-in high-quality dual-microphone echo processing. Dream ® licenses a 32-Mbit jumper-configurable firmware ROM, CleanWave32 ™, which includes high-quality General MIDI-compliant synthesis with many additional sounds and drumsets. Please refer to the corresponding CleanWave32 datasheet. Other sample sets are available under special conditions. More information, including licensing, can be obtained from any Atmel sales office. Smaller capacity firmware is also available for more cost-sensitive or portable applications. Rev. 1710C–DRMSD–12/02 1 ATSAM9703 Configuration The firmware can also be modified to fit customer specifications. An ATSAM9703-based development/prototyping board is available and includes the ATSAM9703, 32 Mbits of EPROM memory, 32K words of SRAM, a codec and one DAC, providing four channels of audio Out and a stereo line input (ref. 9703DVB). The ATSAM9703 internal sound definition format is compatible with the ATSAM9407 sound studio IC. Therefore it is possible to develop specific sounds for the ATSAM9703 by using the development tools of the ATSAM9407. The ATSAM9703 operates from a “low” frequency 9.6 MHz typical crystal. A built-in PLL raises this frequency to a 38.4 MHz internal clock which controls the two processors. Care has been taken that Output pin signals change only when necessary. This minimizes RFI (radio frequency interferences) and power consumption. Minimizing RFI is mostly important in order to comply with standards such as FCC, CSA and CE. The core power supply for the ATSAM9703 should be 3.3V ± 10%, while the periphery supports supply from 3V to 5.5V (5V ± 10% for TTL-compatible applications). Therefore, by selecting 3.3V ROM, SRAM and DAC, it is possible to develop low-power/low-voltage portable applications. Figure 1. Typical Hardware Configuration CleanWave ROM MIDI IN 2 RAM ATSAM9703 CODEC Audio Out Microphone Microphone ATSAM9703 1710C–DRMSD–12/02 ATSAM9703 Pin Description Pins by Function Table 1. Power Supply Group Pin Name Pin Number Type Function GND 2, 6, 8, 16, 20, 22, 26, 28, 38, 46, 49, 53, 59, 71, 75, 82, 83, 94 PWR Digital Ground All pins should be connected to a ground plane. VCC 1, 7, 15, 21, 27, 37, 48, 52, 58, 70, 74, 81, 95 PWR Power Supply, 3V to 5.5V All pins should be connected to a VCC plane. VC3 9, 19, 24, 77 PWR Core Power Supply, 3.3V ± 10 %. All pins should be connected to +3.3V. If 3.3V is not available, then it can be derived from 5V by two 1N41418 diodes in series. Pin Number Type Function 17 IN Table 2. Serial MIDI Pin Name MIDI IN Serial TTL MIDI IN. All controls are received by this pin. Table 3. External ROM/RAM Group Pin Name Pin Number Type Function WA[24:0] 47, 50, 51, 54 - 57, 60 - 69, 72, 73, 76, 78 - 80, 84, 85 OUT External ROM/RAM address for up to 32M words (64 MB) of memory. ROM memory holds firmware and PCM data. RAM memory holds working variables and effect delay lines. WD[15:0] 86 - 93, 96 -100, 3 - 5 I/O External ROM/RAM data. Holds read data from ROM or RAM when WOE is low, write data to RAM when WWE is low. WCS0 34 OUT External ROM chip select, active low. WCS1 35 OUT External RAM chip select, active low. WOE 36 OUT External ROM/RAM Output enable, active low. WWE 33 OUT External RAM write, active low RBS 25 OUT RAM byte select. Used as lower address from RAM when 8-bit wide RAM is connected. Pin Number Type Function CLBD 23 OUT Digital audio bit clock WSBD 32 OUT Digital audio left/right select DABD0 30 OUT Digital audio main stereo Output DABD1 31 OUT Auxiliary digital stereo Output. Reserved for surround effects. DAAD 29 IN Table 4. Digital Audio Group Pin Name Digital audio two channels input. Up to eight channels of audio can be input to the chip by using pins P1 to P3 alternate function. 3 1710C–DRMSD–12/02 Table 5. Miscellaneous Group Pin Name Pin Number Type X1 X2 12, 11 – 9.6 MHz crystal connection. An external 9.6 MHz clock can also be used on X1 (3.3V input). X2 cannot be used to drive external circuits. LFT 10 – PLL external RC network. RESET 13 IN Reset input, active low. This is a Schmidt trigger input, allowing direct connection of an RC network. PDWN 14 IN Power down, active low. When power down is active, then all Output pins will be floated. The crystal oscillator will be stopped. To exit from power down, PDWN should be high and RESET applied. 43, 44, 45 IN Test pins. Should be grounded. P[3:0] 39, 40, 41, 42 I/O General-purpose I/O pins. As inputs, can be used to configure the software. P1 to P3 can also be used as three additional stereo serial inputs (six audio channels). RUN 18 OUT When high, indicates that the synthesizer is up and running. May be used as a RESET input for an external DAC. TEST[2:0] 4 Function ATSAM9703 1710C–DRMSD–12/02 ATSAM9703 Pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 WD12 WD11 WD10 WD9 WD8 VCC GND WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 WA25 WA23 GND GND VCC WA22 WA21 WA20 VC3 WA19 Figure 2. ATSAM9703 Pinout in 100-lead TQFP Package 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GND VCC WA18 WA17 GND VCC WA16 WA15 WA14 WA13 WA12 WA11 WA10 WA9 WA8 WA7 GND VCC WA6 WA5 WA4 WA3 GND VCC WA2 GND VCC GND DAAD DABD0 DABD1 WSBD WWE WCS0 WCS1 WOE VCC GND P0 P1 P2 P3 TEST0 TEST1 TEST2 GND WA0 VCC GND WA1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC GND WD13 WD14 WD15 GND VCC GND VC3 LFT X2 X1 RESET PDWN VCC GMD MIDI_IN RUN VC3 GND VCC GND CBD VC3 RBS 5 1710C–DRMSD–12/02 Mechanical Dimensions Figure 3. 100-lead Thin Plastic Quad Flat Pack 16.10(0.634) 15.90(0.626) PIN 1 ID 0.27(0.011) 0.17(0.007) 0.50(0.02) 1.45(0.057) 1.35(0.053) 14.10(0.555) 13.90(0.547) 0.75(0.030) 0.45(0.018) 6 0.15(0.006) 0.05(0.002) ATSAM9703 1710C–DRMSD–12/02 ATSAM9703 Absolute Maximum Ratings Table 6. Absolute Maximum Ratings Ambient Temperature (Power Applied)..........-40°C to + 85°C Storage Temperature......................................-65°C to + 160°C Voltage on any pin (except X1)....................-0.5V to VCC + 0.5V Supply Voltage.....................................................-0.5V to + 6.5V VC3 Supply Voltage................................................-0.5V t0 +4.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect device reliability. Maximum IOL per I/O pin...................................................10mA Note: All voltages with respect to 0V, GND = 0V) Recommended Operating Conditions Table 7. Recommended Operating Conditions Symbol Note: Parameter/Condition Min Typ Max Unit VCC Supply Voltage(1) 3 3.3/5.0 5.5 V VC3 Supply Voltage 3 3.3 3.6 V TA Operating Ambient Temperature 0 70 °C 1. When using 3.3V supply in a 5V environment, care must be taken that pin voltage does not exceed VCC + 0.5V. DC Characteristics Table 8. DC Characteristics (TA = 25°C, VC3 = 3.3V ± 10%) Symbol Parameter/Condition VCC Min Typ Max Unit VIL Low Level Input Voltage 3.3 5.0 -0.5 -0.5 1.0 1.7 V V VIH High Level Input Voltage 3.3 5.0 2.3 3.3 VCC + 0.5 VCC + 0.5 V V VOL Low Level Output Voltage (IOL = -3.2 mA) 3.3 5.0 0.45 0.45 V V VOH High Level Output Voltage (IOH = 0.8 mA) 3.3 5.0 ICC Power Supply Current (Crystal Freq. = 9.6 MHz) 3.3 5.0 Power Down Supply Current 2.8 4.5 V V 70 25 90 35 mA mA 70 100 µA 7 1710C–DRMSD–12/02 Timings All timing conditions: TA = 25°C, VCC = 5V, VC = 3.3V, all Outputs exept X2 and LFT load capacitance = 30 pF, crystal frequency or external clock at X1 = 9.6 MHz. External ROM Timing Figure 4. ROM Read Cycle tRC WCS0 tCSOE WA[24:0] tPOE WOE tOE WD[15:0] tDF tACE Table 9. Timing Parameters Symbol Parameter Min tRC Read Cycle Time 130 tCSOE Chip Select Low/Address Valid to WOE low 45 tPOE Output Enable Pulse Width tACE Chip Select/Address Access Time 125 ns tOE Output Enable Access Time 70 ns tDF Chip select or WOE High to Input Data High-Z 0 External RAM Timing Typ Max Unit ns 80 78 ns ns 50 ns Figure 5. 16-bit SRAM Read Cycle tRC WCS1 tCSOE WA[24:0] tPOE WOE WWE tOE WD[15:0] 8 tDF tACE ATSAM9703 1710C–DRMSD–12/02 ATSAM9703 Figure 6. 16-bit SRAM Write Cycle tWC WCS1 tCSWE WA[24:0] WOE tWP WWE tDW tDH WD[15:0] Table 10. Timing Parameters Symbol Parameter Min Typ Max Unit tRC Read Cycle Time 130 tCSOE Chip Select Low/Address Valid to WOE Low 45 tPOE Output Enable Pulse Width tACE Chip Select/Address Access Time 125 ns tOE Output Enable Access Time 70 ns tDF Chip Select or WOE High to Input Data High-Z 0 tWC Write Cycle Time 130 ns tCSWE Write enable Low from CS or Address or WOE 40 ns tWP Write Pulse Width tDW Data Out Setup Time 95 ns tDH Data Out Hold Time 10 ns ns 80 78 ns 50 104 ns ns ns 9 1710C–DRMSD–12/02 Figure 7. 8-bit SRAM Read Cycle tRC WCS1 tCSOE WA[24:0] tPOE WOE WWE tORB tACE RBS tOE tACH tDF Low WD[7:0] High Figure 8. 8-bit SRAM Write Cycle t WC WCS1 tCSWE WA[24:0] WOE t WP t WP WWE tAS RBS tDW1 tDH1 WD[7:0] tDH2 tDW2 Low High Table 11. Timing Parameters Symbol Parameter Min tRC Word Read Cycle Time 130 tCSOE Chip Select Low/Address Valid to WOE Low 45 tPOE Output Enable Pulse Width tACE Chip Select/Address Low Byte Access Time 70 ns tOE Output Enable Low Byte Access Time 20 ns 10 Typ Max Unit ns 80 78 ns ns ATSAM9703 1710C–DRMSD–12/02 ATSAM9703 Table 11. Timing Parameters (Continued) Symbol Parameter tORB Output Enable Low Byte Select High tACH Byte Select High Byte access Time 45 tDF Chip select or WOE High to Input High-Z 0 tWC Word Write Cycle Time 130 ns tCSWE 1st WWE Low from CS or Address or WOE 40 ns tWP Write (Low and High Byte) Pulse Width 20 ns tDW1 Data Out Low Byte Setup Time 25 ns tDH1 Data Out Low Byte Hold Time 20 ns tAS RBS High to Second Write Pulse 8 ns tDW Data Out High Byte Setup Time 40 ns tDH2 Data Out High Byte Hold Time 10 ns Digital Audio Min Typ Max 26 Unit ns ns 50 ns Figure 9. Digital Audio Timing tCW tCW tCLBD WSBD CLBD DABD0 DABD1 DAAD P[3:1] (1) Note: tSOD tSOD 1. When used as alternate audio in. Table 12. Timing Parameters Symbol Parameter Min Typ tCW CLBD Rising to WSBD Change 200 ns tSOD DABD Valid Prior/After CLBD Rising 200 ns tCLBD CLBD Cycle Time 416.67 Max Unit ns 11 1710C–DRMSD–12/02 Digital Audio Frame Figure 10. Digital Audio Frame Format WSBD (I2S) (1) WSBD (1) (Japanese) CLBD (2) (2) DABD0 DABD1 DAAD (3) (2) P[3:1] (4) (3) d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 MSB LSB (16 bits) LSB (20 bits) MSB LSB (18 bits) Notes: 12 1. Selection between I2S and Japanese format is a firmware option. 2. When connected to codecs such as CS4216 or CS4218, D[11:0] can be used to hold independent auxiliary information on left and right words. Refer to the corresponding codec data sheets for details. Auxiliary information is available on DABD0 and DAAD. 3. DAAD, P[3:1] are 16 bits only. 4. When used as an alternate audio in. ATSAM9703 1710C–DRMSD–12/02 ATSAM9703 Reset and Power-down During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which can take abOut 20 ms. A typical RC/diode power-up network can be used. After the low-to-high transition of RESET, the following occurs: • The synthesis enters an idle state. • The RUN Output is set to zero. • Firmware execution starts from address 0100H in ROM space (WCS0 low). If PDWN is asserted low, then all I/Os and Outputs will be floated and the crystal oscillator and PLL will be stopped. The chip enters a deep power-down sleep mode. To exit power-down, PDWN has to be asserted high, then RESET applied. Recommended Board Layout As for all HCMOS high-integration ICs, some rules of board layout should be followed for reliable operation: • GND, VCC, VC3 distribution, decouplings All GND, VCC, V C3 pins should be connected. GND + V CC planes are strongly recommended below the ATSAM9703. The board GND + VCC distribution should be in grid form. For 5V VCC operation, if 3.3V is not available, then VC3 can be connected to VCC by two 1N4148 diodes in serial. This guarantees a minimum voltage drop of 1.2V. Recommended VCC decoupling is 0.1 µF at each corner of the IC with an additional 10 µF decoupling close to the crystal. VC3 requires a single 0.1 µF decoupling close to the IC. • Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-CR and the ATSAM9703 should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from ATSAM9703. • Analog Section A specific AGND ground plane should be provided, which connects by a single trace to the GND ground. No digital signals should cross the AGND plane. Refer to the codec vendor recommended layOut for correct implementation of the analog section. • Unused Inputs Unused inputs should always be connected. A floating input can cause internal oscillation inside the IC, which can destroy the device by dramatically increasing the power consumption. If the power-down feature is to be used, care should be taken that no pin is left floating during power down. Usually, a 1 MΩ ground return is sufficient. 13 1710C–DRMSD–12/02 Recommended Crystal Compensation and LFT Filter Figure 11. Crystal Compensation and LFT Filter C1 12 X1 22 pF X1 9.6 MHz C4 11 X2 22 pF 10 LFT 18 Note: 14 23 32 29 DABD0 DABD1 DAAD PDWN CLBD C3 10 nF 14 RUN VCC WSBD R1 100Ω C2 2.2 nF 31 30 The X2 Output cannot be used to drive another circuit. ATSAM9703 1710C–DRMSD–12/02 ATSAM9703 CleanWave32™ ROM Firmware (Ref. GMS973201) • ROM includes Firmware and PCM Data • Full GM implementation with Top-quality Additional Sounds – 128 General MIDI Sounds – 189 Variation Sounds including Sound Effects – 9 Drum Sets + 1 SFX Set • Powerful MIDI implementation • Built-in Compatible Reverb and Chorus • Built-in Four-band Parametric Equalizer, Fully Controllable by MIDI • Built-in Spatial Effect with MIDI Control • Microphone Echo Processing Figure 12. CleanWave 32 ROM Firmware Description MIDI Reverb Synthesizer ROM CleanWave32 (GMS973201) RAM 32k x 16 Chorus Front EQ Surround Back ATSAM9503 CODEC PCM3001 or Equivalent MIKE 1 Echo Processor MIKE 2 Hardware (option, requires additional DAC) Function For detailed information about sound list and MIDI implementation, please request the CleanWave32 user’s manual. Reference Design ATSAM9703DVB ATSAM9703 + 2 x 16-Mbit EPROMs + 2 x 32k x 8 SRAMs + Codec + DAC ATSAM9703DVB can be used for CleanWave32 evaluation or other specific applications requiring not more than 4 Mb of PCM data. 15 1710C–DRMSD–12/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ATMEL ® and Dream ® are the registered trademarks of Atmel; CleanWave32™ is the trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1710C–DRMSD–12/02 0M