INTEGRATED CIRCUITS SSTVN16859 13-bit 1:2 SSTL_2 registered buffer for DDR Product data sheet Philips Semiconductors 2004 Jul 15 Philips Semiconductors Product data sheet 13-bit 1:2 SSTL_2 registered buffer for DDR SSTVN16859 such as DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. FEATURES • Stub-series terminated logic for 2.5 V VDD (SSTL_2) • Designed for PC1600–PC2700 (at 2.5 V) and PC3200 (at 2.6 V) applications • Pin and function compatible with JEDEC standard SSTV16859 • Supports SSTL_2 signal inputs as per JESD 8–9 • Flow-through architecture optimizes PCB layout • ESD classification testing is done to JEDEC Standard JESD22. The device data inputs consist of different receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential (CK and CK) to be compatible with DRAM devices that are installed on the DIMM. Data are registered at the crossing of CK going HIGH, and CK going LOW. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device has an asynchronous input pin (RESET), which when held to the LOW state, resets all registers and all outputs to the LOW state. Protection exceeds 2000 V to HBM per method A114. • Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA. • Supports efficient low power standby operation • Full DDR solution when used with PCKVF857 • Available in 56-terminal HVQFN packages The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. DESCRIPTION The SSTVN16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V for PC1600 – PC2700 applications or between 2.5 V and 2.7 V for PC3200 applications. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven LOW. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the outputs will remain LOW. The SSTVN16859 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns SYMBOL tPHL/tPLH CI TYPICAL UNIT Propagation delay; CK to Qn PARAMETER CL = 30 pF; VDD = 2.5 V CONDITIONS 1.7 ns Input capacitance VCC = 2.5 V 2.8 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES 56-Terminal Plastic HVQFN 2004 Jul 15 TEMPERATURE RANGE ORDER CODE DWG NUMBER 0 °C to +70 °C SSTVN16859BS SOT684-1 2 Philips Semiconductors Product data sheet 13-bit 1:2 SSTL_2 registered buffer for DDR D12 VDDI VDDQ D11 45 44 43 D13 47 LOGIC DIAGRAM 46 VDDQ Q13A 50 GND Q12A 51 48 Q11A 52 49 Q9A Q10A 53 VDDQ 55 54 Q8B 56 56-TERMINAL CONFIGURATION SSTVN16859 RESET 1 42 D10 CK Q6A 2 41 D9 CK Q5A 3 40 D8 Q4A 4 39 D7 Q3A 5 38 RESET Q2A 6 37 GND Q1A 7 36 Q13B 8 35 CK VDDQ 9 34 VDDQ 33 VDDI Q11B 11 32 VREF Q10B 12 31 D6 27 VREF 45 FUNCTION TABLE (each flip flop) 1, 2, 3, 4, 5, 6, 7, 50, 51, 52, 53, 54, 56 Q13A–Q1A Data output 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22 Q13B–Q1B Data output 9, 17, 23, 27, 34, 44, 49, 55 VDDQ Power supply voltage 26, 33, 45 VDDI Power supply voltage 37, 48 GND Ground 24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47 D1–D13 32 VREF 35, 36 CK, CK Positive and negative master clock input RESET Asynchronous reset input: resets registers and disables data and clock differential input receivers OUTPUT INPUTS TERMINAL DESCRIPTION SYMBOL Q1B SW00750 SW01040 TERMINAL NUMBER R 35 to 12 other channels D3 28 VDDQ VDDI 26 D1 24 D2 25 VDDQ 23 22 Q1B 21 Q2B Q3B 20 Q4B 19 Q5B 18 VDDQ 17 29 D4 Q6B 16 30 D5 Q8B 14 Q7B 15 Q9B 13 C1 49 32 D1 Q1A 48 CK Q12B 10 2004 Jul 15 16 1D Q7A 51 51 CK CK H ↑ # L L H ↑ # H H H L or H L or H X Q0 L X or floating X or floating X or floating L H = HIGH voltage level L = LOW voltage level ↓ = HIGH-to-LOW transition ↑ = LOW-to-HIGH transition X = Don’t care NAME AND FUNCTION Data input: clocked in on the crossing of the rising edge of CK and the falling edge of CK Input reference voltage 3 D Q RESET Philips Semiconductors Product data sheet 13-bit 1:2 SSTL_2 registered buffer for DDR SSTVN16859 ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER VDD Supply voltage range VI Input voltage range VO IIK LIMITS CONDITION MIN MAX UNIT –0.5 +3.6 V Notes 2 and 3 –0.5 VDD + 0.5 V Output voltage range Notes 2 and 3 –0.5 VDD + 0.5 V Input clamp current VI < 0 V or VI > VDD — ±50 mA IOK Output clamp current VO < 0 V or VO > VDD — ±50 mA IO Continuous output current VO = 0 V to VDD — ±50 mA Continuous current through each VDD or GND — ±100 mA Storage temperature range –65 +150 °C Tstg NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 3. This value is limited to 3.6 V maximum. 4. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. RECOMMENDED OPERATING CONDITIONS1 SYMBOL PARAMETER VDD Supply voltage VREF Reference voltage g (VREF = VDD/2) VTT Termination voltage CONDITIONS PC1600–PC2700 PC3200 MIN TYP MAX UNIT VDD — 2.7 V 1.15 1.25 1.35 V 1.25 1.3 1.35 V VREF – 40 mV VREF VREF + 40 mV V VI Input voltage 0 — VDD V VIH AC HIGH-level input voltage Data inputs VREF + 310 mV — — V VIL AC LOW-level input voltage Data inputs — — VREF – 310 mV V VIH DC HIGH-level input voltage Data inputs VREF + 150 mV — — V VIL DC LOW-level input voltage Data inputs — — VREF – 150 mV V VIH HIGH-level input voltage RESET 1.7 — VDD V VIL LOW-level input voltage 0.0 — 0.7 V VICR Common-mode input range CK, CK 0.97 — 1.53 V CK, CK VID Differential input voltage 360 — — mV IOH HIGH-level output current — — –16 mA IOL LOW-level output current — — 16 mA Tamb Operating free-air temperature range 0 — +70 °C NOTE: 1. The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW. 2004 Jul 15 4 Philips Semiconductors Product data sheet 13-bit 1:2 SSTL_2 registered buffer for DDR SSTVN16859 DC ELECTRICAL CHARACTERISTICS—PC1600–PC2700 Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VIK II = –18 mA, VDD = 2.3 V 2004 Jul 15 TYP MAX UNIT — –1.2 — — 1.95 — — IOL = 100 µA, VDD = 2.3 V to 2.7 V — — 0.2 IOL = 16 mA, VDD = 2.3 V — — 0.35 All inputs VI = VDD or GND, VDD = 2.7 V — — ±5 Static standby RESET = GND — — 0.01 Static operating RESET = VDD, VI = VIH(AC) or VIL(AC) — — 45 Dynamic operating – clock only RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. — 15 — µA/ clock MHz Dynamic operating – per each data input RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. — 9 — µA/ clock MHz/ data input Data inputs VI = VREF ± 310 mV, VDD = 2.5 V 2.5 2.8 3.5 CK and CK VICR = 1.25 V, VI(PP) = 360 mV, VDD = 2.5 V 2.5 3.2 3.5 RESET VI = VDD or GND, VDD = 2.5 V — 2.4 3.5 IOH = –16 mA, VDD = 2.3 V IDDD Ci MIN — VOL O IDD Tamb = 0 °C to +70 °C VDD – 0.2 IOH = –100 µA, VDD = 2.3 V to 2.7 V VOH O II TEST CONDITIONS IO = 0 mA; VDD = 2.7 V IO = 0 mA; VDD = 2.7 V 5 V V V µA mA pF Philips Semiconductors Product data sheet 13-bit 1:2 SSTL_2 registered buffer for DDR SSTVN16859 DC ELECTRICAL CHARACTERISTICS—PC3200 Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VIK II = –18 mA, VDD = 2.5 V 2004 Jul 15 TYP MAX UNIT — –1.2 — — 1.95 — — IOL = 100 µA, VDD = 2.5 to 2.7 V — — 0.2 IOL = 16 mA, VDD = 2.5 V — — 0.35 All inputs VI = VDD or GND, VDD = 2.7 V — — ±5 Static standby RESET = GND — — 0.01 Static operating RESET = VDD, VI = VIH(AC) or VIL(AC) — — 45 Dynamic operating – clock only RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. — 15 — µA/ clock MHz Dynamic operating – per each data input RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. — 9 — µA/ clock MHz/ data input Data inputs VI = VREF ± 310 mV, VDD = 2.6 V 2.5 2.8 3.5 CK and CK VICR = 1.25 V, VI(PP) = 360 mV, VDD = 2.6 V 2.5 3.2 3.5 RESET VI = VDD or GND, VDD = 2.6 V — 2.4 3.5 IOH = –16 mA, VDD = 2.5 V IDDD Ci MIN — VOL O IDD Tamb = 0 °C to +70 °C VDD – 0.2 IOH = –100 µA, VDD = 2.5 to 2.7 V VOH O II TEST CONDITIONS IO = 0 mA; VDD = 2.7 V IO = 0 mA; VDD = 2.7 V 6 V V V µA mA pF Philips Semiconductors Product data sheet 13-bit 1:2 SSTL_2 registered buffer for DDR SSTVN16859 TIMING REQUIREMENTS—PC1600–PC2700 Over recommended operating conditions; Tamb = 0 °C to +70 °C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL fclock PARAMETER TEST CONDITIONS VDD = 2.5 V ± 0.2 V MIN MAX UNIT Clock frequency — 200 MHz tw Pulse duration, CK, CK HIGH or LOW 2.5 — ns tact Differential inputs active time Notes 1, 2 — 22 ns Differential inputs inactive time Notes 1, 3 — 22 ns tinact tsu th Setup time, fast slew rate (see Notes 4 and 6) Setup time, slow slew rate (see Notes 5 and 6) Hold time, fast slew rate (see Notes 4 and 6) Hold time, slow slew rate (see Notes 5 and 6) 0.65 Data before CK↑, CK↑ CK↓ ns 0.75 0.75 CK↑ CK↓ Data after CK↑, ns 0.9 NOTES: 1. This parameter is not necessarily production tested. 2. Data inputs must be below a minimum time of tact max, after RESET is taken HIGH. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET is taken LOW. 4. For data signal input slew rate ≥ 1 V/ns. 5. For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. 6. CK, CK signals input slew rates are ≥ 1 V/ns. TIMING REQUIREMENTS—PC3200 Over recommended operating conditions; Tamb = 0 °C to +70 °C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL fclock PARAMETER TEST CONDITIONS Clock frequency VDD = 2.6 V ± 0.1 V UNIT MIN MAX — 210 MHz tw Pulse duration, CK, CK HIGH or LOW 2.5 — ns tact Differential inputs active time Notes 1, 2 — 22 ns Differential inputs inactive time Notes 1, 3 — 22 ns tinact tsu th Setup time, fast slew rate (see Notes 4 and 6) Setup time, slow slew rate (see Notes 5 and 6) Hold time, fast slew rate (see Notes 4 and 6) Hold time, slow slew rate (see Notes 5 and 6) 0.65 CK↑ CK↓ Data before CK↑, ns 0.75 0.65 CK↑ CK↓ Data after CK↑, ns 0.8 NOTES: 1. This parameter is not necessarily production tested. 2. Data inputs must be below a minimum time of tact max, after RESET is taken HIGH. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET is taken LOW. 4. For data signal input slew rate ≥ 1 V/ns. 5. For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. 6. CK, CK signals input slew rates are ≥ 1 V/ns. 2004 Jul 15 7 Philips Semiconductors Product data sheet 13-bit 1:2 SSTL_2 registered buffer for DDR SSTVN16859 SWITCHING CHARACTERISTICS—PC1600–PC2700 Over recommended operating conditions; Tamb = 0 °C to +70 °C; VDD = 2.3 V – 2.7 V. Class I, VREF = VTT = VDD × 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS O FROM (INPUT) SYMBOL O TO (OUTPUT) fmax VDD = 2.5 V ± 0.2 V UNIT MIN MAX 200 — MHz tpd CK and CK Q 1.1 2.5 ns tpdMSS CK and CK Q — 2.9 ns RESET Q 1.1 5 ns tPHL SWITCHING CHARACTERISTICS—PC3200 Over recommended operating conditions; Tamb = 0 °C to +70 °C; VDD = 2.5 V – 2.7 V. Class I, VREF = VTT = VDD × 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS O FROM (INPUT) SYMBOL O TO (OUTPUT) VDD = 2.6 V ± 0.1 V MIN fmax 220 — MHz 1.1 1.8 ns Q — 2.1 ns Q 1.1 5 ns tpd CK and CK Q tpdMSS CK and CK RESET tPHL PARAMETER MEASUREMENT INFORMATION TEST CIRCUIT VTT RL = 50 Ω from output under test TEST POINT CL = 30 pF see Note 1 SW02124 Figure 1. Load circuitry NOTE: 1. CL includes probe and jig capacitance. 2004 Jul 15 8 UNIT MAX Philips Semiconductors Product data sheet 13-bit 1:2 SSTL_2 registered buffer for DDR SSTVN16859 AC WAVEFORMS LVCMOS RESET LVCMOS RESET VDD VDD/2 VDD/2 tinact VIH Input VDD/2 tact VIL 90% IDD 10% tPHL SW00752 VOH Output Waveform 1. Inputs active and inactive times (see Note 1) VTT VOL tW SW00755 VIH INPUT VREF Waveform 4. Propagation delay times VREF VIL Timing input SW00753 VI(PP) VICR Waveform 2. Pulse duration tsu TIMING INPUT VICR VICR VIH VI(PP) Input tPLH th VREF VREF VIL tPHL SW00756 VOH OUTPUT Waveform 5. Setup and hold times VTT VOL SW00754 Waveform 3. Propagation delay times NOTES: 1. IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ± 20% (unless otherwise specified). 3. The outputs are measured one at a time with one transition per measurement. 4. VTT = VREF = VDD/2 5. VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 6. VIL = VREF – 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 7. tPLH and tPHL are the same as tpd. 2004 Jul 15 9 Philips Semiconductors Product data sheet 13-bit 1:2 SSTL_2 registered buffer for DDR SSTVN16859 HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm 2004 Jul 15 10 SOT684-1 Philips Semiconductors Product data sheet 13-bit 1:2 SSTL_2 registered buffer for DDR SSTVN16859 REVISION HISTORY Rev Date Description _1 20040715 Product data sheet (9397 750 13716) Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data sheet Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data sheet Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data sheet Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 07-04 For sales offices addresses send e-mail to: [email protected]. Document order number: Philips Semiconductors 2004 Jul 15 11 9397 750 13716