ATMEL ATA8401-6AQY

Features
• Integrated PLL Loop Filter
• ESD Protection (4 kV HBM/200V MM; Except Pin 2: 4 kV HBM/100V MM)
also at ANT1/ANT2
• High Output Power (8.0 dBm) with Low Supply Current (9.0 mA)
• Modulation Scheme ASK/FSK
•
•
•
•
•
•
•
– FSK Modulation is Achieved by Connecting an Additional Capacitor Between the
XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller
Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply
Single Li-cell for Power Supply
Supply Voltage 2.0V to 4.0V in the Temperature Range of –40°C to +85°C
Package TSSOP8L
Single-ended Antenna Output with High Efficient Power Amplifier
CLK Output for Clocking the Microcontroller
One-chip Solution with Minimum External Circuitry
ATA8401
Applications
•
•
•
•
•
•
•
UHF ASK/FSK
Industrial
Transmitter
Industrial/Aftermarket Remote Keyless Entry Systems
Alarm, Telemetering, and Energy Metering Systems
Remote Control Systems for Consumer and Industrial Markets
Access Control Systems
Home Automation
Home Entertainment
Toys
1. Description
The ATA8401 is a PLL transmitter IC, which has been developed for the demands of
RF low-cost transmission systems for industrial applications at data rates up to
50 kBaud ASK and 32 kBaud FSK modulation scheme. The transmitting frequency
range is 310 MHz to 350 MHz. It can be used in both FSK and ASK systems.
Figure 1-1.
System Block Diagram
UHF ASK/FSK
Remote control transmitter
UHF ASK/FSK
Remote control receiver
1 Li cell
ATA8401
Keys
Encoder
ATARx9x
ATA3741/
ATA3745/
ATA5743/
ATA5744/
ATA8201
PLL
Antenna
XTO
Control
Microcontroller
IF Amp
Antenna
VCO
LNA
1 to 3
Demod
PLL
LNA
XTO
VCO
4984B–INDCO–11/08
2. Pin Configuration
Figure 2-1.
Pinning TSSOP8L
ATA8401
CLK
PA_ENABLE
ANT2
ANT1
Table 2-1.
Pin
1
2
3
4
8
7
6
5
ENABLE
GND
VS
XTAL
Pin Description
Symbol
Function
Configuration
VS
1
CLK
Clock output signal for microcontroller
The clock output frequency is set by the
crystal to fXTAL/4
100Ω
CLK
100Ω
PA_ENABLE
2
PA_ENABLE
50 kΩ
UREF = 1.1V
Switches on power amplifier used for
ASK modulation
20 µA
ANT1
3
ANT2
Emitter of antenna output stage
4
ANT1
Open collector antenna output
ANT2
2
ATA8401
4984B–INDCO–11/08
ATA8401
Table 2-1.
Pin
Pin Description (Continued)
Symbol
Function
Configuration
VS
1.5 kΩ
5
XTAL
VS
1.2 kΩ
Connection for crystal
XTAL
182 µA
6
7
VS
GND
8
ENABLE
Supply voltage
Ground
See ESD protection circuitry (see Figure 4-5 on page 9)
See ESD protection circuitry (see Figure 4-5 on page 9)
ENABLE
Figure 2-2.
200 kΩ
Enable input
Block Diagram
ATA8401
Power up/down
f
CLK
ENABLE
4
1
8
f
32
PA_ENABLE
GND
2
7
PDF
CP
ANT2
VS
6
3
LF
ANT1
4
PA
VCO
XTO
5
XTAL
PLL
3
4984B–INDCO–11/08
3. General Description
This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmitters to be assembled. The VCO is locked to 32 fXTAL, and therefore a 9.8438 MHz crystal is
needed for a 315 MHz transmitter. All other PLL and VCO peripheral elements are integrated.
The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are needed as external elements.
The crystal oscillator together with the PLL typically needs < 3 ms until the PLL is locked and the
CLK output is stable. There is a wait time of ≥ 3 ms until the CLK is used for the microcontroller
and the PA is switched on.
The power amplifier is an open-collector output delivering a current pulse, which is nearly independent from the load impedance. The delivered output power is therefore controllable via the
connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50 Ω. A high
power efficiency of η= Pout/(IS,PA VS) of 40% for the power amplifier results when an optimized
load impedance of ZLoad = (255 + j192) Ω is used at 3V supply voltage.
4. Functional Description
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode, consuming only a very
small amount of current, so that a lithium cell used as power supply can work for several years.
With ENABLE = H the XTO, PLL, and the CLK driver are switched on. If PA_ENABLE remains
L, only the PLL and the XTO are running, and the CLK signal is delivered to the microcontroller.
The VCO locks to 32 times the XTO frequency.
With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver, and the power amplifier are
on. The power amplifier can be switched on and off with PA_ENABLE. This is used to perform
the ASK modulation.
4.1
ASK Transmission
The ATA8401 is activated by ENABLE = H. PA_ENABLE must remain L for typically ≥ 3 ms,
then the CLK signal can be taken to clock the microcontroller and the output power can be modulated by means of the PA_ENABLE pin. After transmission, PA_ENABLE is switched to L and
the microcontroller switches back to internal clocking. The ATA8401 is switched back to standby
mode with ENABLE = L.
4.2
FSK Transmission
The ATA8401 is activated by ENABLE = H. PA_ENABLE must remain L for typically ≥ 3 ms,
then the CLK signal can be taken to clock the microcontroller, and the power amplifier is
switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND with
an open-drain output port, thus changing the reference frequency of the PLL. If the switch is
closed, the output frequency is lower than if the switch is open. After transmission, PA_ENABLE
is switched to L, and the microcontroller switches back to internal clocking. The ATA8401 is
switched back to standby mode with ENABLE = L.
The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the following tolerances are considered.
4
ATA8401
4984B–INDCO–11/08
ATA8401
Figure 4-1.
Tolerances of Frequency Modulation
VS
CStray1
CStray2
LM
C4
XTAL
CM
RS
C0
Crystal equivalent circuit
C5
CSwitch
Using C4 = 8.2 pF ±5%, C5 = 10 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray capacitances on each side of the crystal of CStray1 = CStray2 = 1 pF ±10%, a parallel capacitance of the
crystal of C0 = 3.2 pF ±10%, and a crystal with CM = 13 fF ±10%, typically results in an FSK deviation of ±21.5 kHz with worst case tolerances of ±16.25 kHz to ±28.01 kHz.
4.3
CLK Output
An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOS
compatible if the load capacitance is lower than 10 pF.
4.3.1
Clock Pulse Take-over
The clock of the crystal oscillator can be used for clocking the microcontroller. A special feature
of Atmel®’s ATARx9x is that it starts with an integrated RC-oscillator to switch on the ATA8401
with ENABLE = H, and after 3 ms assumes the clock signal of the transmission IC, so that the
message can be sent with crystal accuracy.
4.3.2
Output Matching and Power Setting
The output power is set by the load impedance of the antenna. The maximum output power is
achieved with a load impedance of ZLoad,opt = (255 + j192)Ω. There must be a low resistive path
to VS to deliver the DC current.
The delivered current pulse of the power amplifier is 9 mA. The maximum output power is delivered to a resistive load of 400Ω if the 1.0 pF output capacitance of the power amplifier is
compensated by the load impedance.
An optimum load impedance of:
ZLoad = 400Ω || j/(2 × π 1.0 pF) = (255 + j192)Ω thus results for the maximum output power of
8 dBm.
The load impedance is defined as the impedance seen from the ATA8401’s ANT1, ANT2 into
the matching network. Do not confuse this large signal load impedance with a small signal input
impedance delivered as input characteristic of RF amplifiers and measured from the application
into the IC instead of from the IC into the application for a power amplifier.
Less output power is achieved by lowering the real parallel part of 400Ω where the parallel imaginary part should be kept constant.
Output power measurement can be done with the circuit shown in Figure 4-2. Note that the component values must be changed to compensate for the individual board parasitics until the
ATA8401 has the right load impedance ZLoad,opt = (255 + j192)Ω. Also the damping of the cable
used to measure the output power must be calibrated out.
5
4984B–INDCO–11/08
Figure 4-2.
Output Power Measurement at f = 315 MHz
VS
C1
1 nF
L1
56 nH
C2
ANT1
ZLopt
3.3 pF
ANT2
Note:
4.4
Z = 50Ω
Power
meter
Rin
50Ω
For 345 MHz C2 has to be changed to 2.7 pF
Application Circuit
A value of C3 = 68 nF/X7R is recommended for the supply-voltage blocking capacitor C3 (see
Figure 4-3 on page 7 and Figure 4-4 on page 8). C1 and C2 are used to match the loop antenna
to the power amplifier where C1 typically is 22 pF/NP0 and C2 is 10.8 pF/NP0 (18 pF + 27 pF in
series). For C2, two capacitors in series should be used to achieve a better tolerance value and
to have the possibility of realizing the ZLoad,opt using standard valued capacitors.
C1, together with the pins of ATA8401 and the PCB board wires, forms a series resonance loop
that suppresses the 1st harmonic. Therefore, the position of C1 on the PCB is important. Normally the best suppression is achieved when C1 is placed as close as possible to the pins ANT1
and ANT2.
The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop
antenna is too high.
L1 ([50 nH to 100 nH) can be printed on PCB. C4 should be selected so that the XTO runs on the
load resonance frequency of the crystal. Normally, a 15 pF load-capacitance crystal results in a
value of 12 pF.
6
ATA8401
4984B–INDCO–11/08
ATA8401
Figure 4-3.
ASK Application Circuit
S1
BPXY
VDD
ATARx9x
VS
1
S2
VSS
BPXY
20
BPXY
BPXY
OSC1
7
ATA8401
Power up/down
CLK
ENABLE
f
4
1
8
f
32
GND
PA_ENABLE
2
7
PDF
C3
C2
CP
VS
ANT2
3
6
VS
Loop
Antenna
LF
C1
XTAL
ANT1
4
PA
VCO
PLL
L1
XTO
XTAL
5
C4
VS
7
4984B–INDCO–11/08
Figure 4-4.
FSK Application Circuit
S1
BPXY
VDD
ATARx9x
VS
1
S2
VSS
BPXY
20
BP42/T2O
BPXY
18
BPXY
OSC1
7
ATA8401
Power up/down
CLK
ENABLE
f
4
1
8
f
32
PA_ENABLE
GND
2
7
PDF
C3
C2
CP
ANT2
VS
3
Loop
Antenna
6
VS
LF
C1
C5
ANT1
XTAL
4
PA
VCO
PLL
L1
XTO
XTAL
5
C4
VS
8
ATA8401
4984B–INDCO–11/08
ATA8401
Figure 4-5.
ESD Protection Circuit
VS
ANT1
CLK
PA_ENABLE
ANT2
XTAL
ENABLE
GND
5. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Maximum
Unit
Supply voltage
Symbol
VS
5
V
Power dissipation
Ptot
100
mW
Tj
150
°C
°C
Junction temperature
Minimum
Storage temperature
Tstg
–55
+85
Ambient temperature
Tamb
–55
+85
°C
(1)
Input voltage
VmaxPA_ENABLE
–0.3
Note:
1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V.
(VS + 0.3)
V
6. Thermal Resistance
Parameters
Junction ambient
Symbol
Value
Unit
RthJA
170
K/W
7. Electrical Characteristics
VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified.
Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Supply current
Power down,
VENABLE < 0.25V, –40°C to 85°C
VPA-ENABLE < 0.25V, 25°C
(100% correlation tested)
Supply current
Power up, PA off, VS = 3V,
VENABLE > 1.7V, VPA-ENABLE < 0.25V
Min.
Typ.
Max.
Unit
350
nA
nA
IS_Off
< 10
IS
3.7
4.8
mA
9
11.6
mA
Power up, VS = 3.0V,
IS_Transmit
VENABLE > 1.7V, VPA-ENABLE > 1.7V
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
Supply current
Note:
Symbol
9
4984B–INDCO–11/08
7. Electrical Characteristics (Continued)
VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified.
Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Output power
VS = 3.0V, Tamb = 25°C,
f = 315 MHz, ZLoad = (255 + j192)W
Output power variation for the full
temperature range
Tamb = 25°C,
VS = 3.0V
VS = 2.0V
Output power variation for the full
temperature range
Tamb = 25°C,
VS = 3.0V
VS = 2.0V,
POut = PRef + ΔPRef
Achievable output-power range
Selectable by load impedance
Spurious emission
fCLK = f0/128
Load capacitance at pin CLK = 10 pF
fO ±1 × fCLK
fO ±4 × fCLK
Other spurious are lower
Oscillator frequency XTO
(= phase comparator frequency)
fXTO = f0/32
fXTAL = resonant frequency of the XTAL,
CM ≤ 10 fF, load capacitance selected
accordingly
Tamb = 25°C
Symbol
Min.
Typ.
Max.
Unit
PRef
6.0
8.0
10.5
dBm
ΔPRef
ΔPRef
–1.5
–4.0
dB
dB
ΔPRef
ΔPRef
–2.0
–4.5
dB
dB
8.0
dBm
POut_typ
0
fXTO
PLL loop bandwidth
–55
–52
dBc
dBc
fXTAL
ppm
250
kHz
Phase noise of phase comparator
Referred to fPC = fXT0,
25 kHz distance to carrier
–116
–110
dBc/Hz
In-loop phase noise PLL
25 kHz distance to carrier
–86
–80
dBc/Hz
Phase noise VCO
At 1 MHz
At 36 MHz
–94
–125
–90
–121
dBc/Hz
dBc/Hz
350
MHz
Frequency range of VCO
fVCO
310
Clock output frequency (CMOS
microcontroller compatible)
Voltage swing at pin CLK
f0/128
CLoad ≤ 10 pF
Series resonance R of the crystal
V0h
V0l
VS × 0.8
Rs
Capacitive load at pin XT0
MHz
VS × 0.2
V
V
110
Ω
7
pF
FSK modulation frequency rate
Duty cycle of the modulation signal = 50%
0
32
kHz
ASK modulation frequency rate
Duty cycle of the modulation signal = 50%
0
50
kHz
Low level input voltage
High level input voltage
Input current high
0.25
ENABLE input
20
V
V
µA
0.25
VS(1)
5
V
V
µA
Low level input voltage
VIl
VIh
High level input voltage
IIn
Input current high
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
PA_ENABLE input
Note:
10
VIl
VIh
IIn
1.7
1.7
ATA8401
4984B–INDCO–11/08
ATA8401
8. Ordering Information
Extended Type Number
Package
MOQ
ATA8401-6AQY
TSSOP8L
5000 pcs
Remarks
Taped and reeled, Pb-free
9. Package Information
3±0.1
+0.06
0.31-0.07
0.65 nom.
3.8±0.3
4.9±0.1
+0.0
0.1±0.05
3±0.1
0.15-0.025
0.85±0.05
+0.05
1-0.15
Package: TSSOP 8L
Dimensions in mm
3 x 0.65 = 1.95 nom.
8
5
technical drawings
according to DIN
specifications
Drawing-No.: 6.543-5083.01-4
1
4
Issue: 2; 15.03.04
10. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4984B-INDCO-11/08
• Put datasheet in the newest template
• Section 4.3.1 “Clock Pulse Take-over” on page 5 changed
11
4984B–INDCO–11/08
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4984B–INDCO–11/08