ATMEL U2730B-N

Features
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Supply Voltage: 8.5 V
RF Frequency Range: 1400 MHz to 1550 MHz
IF Frequency Range: 150 MHz to 250 MHz
Enhanced IM3 Rejection
Overall Gain Control Range: 30 dB Typically
DSB Noise Figure: 10 dB
Gain-controlled Amplifier and L-band Mixer
Power-down Function for the Analog Part
On-chip Gain-control Circuitry
On-chip VCO, Typical Frequency 1261.568 MHz
Internal VCO Can Be Overdriven by an External LO
On-chip Frequency Synthesizer
– Fixed LO Divider Factor: 2464
– Nine Selectable Reference Divider Factors : 32, 33, 35, 36, 48, 49, 63, 64, 65
– A Reference Oscillator (Can Be Overdriven by an External Reference Signal)
– Tristate Phase Detector with Programmable Charge Pump
– Programmable Deactivation of Tuning Output
– Lock-status Indication
– Test Interface
Electrostatic sensitive device.
Observe precautions for handling.
L-band
Down-converter
for DAB
Receivers
U2730B-N
Preliminary
Description
The U2730B-N is a monolithically integrated L-band down-converter circuit fabricated
with Atmel’s advanced UHF5S technology. This IC covers all functions of an L-band
down-converter in a DAB receiver. The device includes a gain-controlled amplifier, a
gain-controlled mixer, an output buffer, a gain control block, a power save function for
the analog part, an L-band oscillator and a complete frequency syntheziser unit. The
frequency syntheziser block consists of a reference oscillator/buffer, a reference
divider, an RF divider, a tri-state phase detector, a loop filter amplifier, a lock detector,
a programmable charge pump, a test interface and a control interface.
4719A–DAB–05/03
1
Figure 1. Block Diagram
17
AGC
VCC1 VCC3 VCC4
IF
TH
19
3
18
20
Internal 5 V supply voltage
for frequency synthesizer
Analog
part
NRF
TANK
VREF
6, 7, 8, 21,
22, 23, 24
Voltage
stabilizer
Bandgap
26
25
14
PLCK
Lock
detector
20k
5
4
RF counter
: 2464
VCO
Power save
(analog part)
12
Reference
counter
: Nref
13
Test
interface
1
15
16
PSM
OSCB
OSCE
11
TI
CD
Charge
pump
200 m/300 m
Tristate
phase
detector
Power
down
2
GND
9
28
U
RF
VCC2
PD
Control
interface
10
27
2
CI SI1 SI2
U2730B-N
4719A–DAB–05/03
U2730B-N
Pin Configuration
Figure 2. Pinning SSO28
PSM
1
28 VCC4
SI2
2
27 SI1
VCC1
3
26 RF
VREF
4
25 NRF
TANK
5
24 GND
GND
6
23 GND
GND
7
22 GND
GND
8
21
GND
VCC2
9
20
VCC3
CI 10
19
IF
TI 11
18
AGC
CD 12
17 TH
PD 13
16
OSCE
PLCK 14
15
OSCB
3
4719A–DAB–05/03
Pin Description
4
Pin
Symbol
1
PSM
Function
Power save mode
2
SI2
3
VCC1
Control input
Supply voltage VCO
4
VREF
Reference pin of VCO
5
TANK
Tank pin of VCO
6, 7, 8, 21,
22, 23, 24
GND
Ground
9
VCC2
Supply voltage PLL
10
CI
Control input
11
TI
Test interface
12
CD
Active filter output
13
PD
Tristate charge pump output
14
PLCK
Lock-indication output (open collector)
15
OSCB
Input of internal oscillator/buffer
16
OSCE
Output of internal oscillator/buffer
17
TH
Threshold voltage of comparator
18
AGC
19
IF
20
VCC3
25
NRF
26
RF
RF input
27
SI1
Control input
28
VCC4
Charge-pump output of comparator, AGC input for amplifier and mixer
Intermediate frequency output
Supply voltage
RF input (inverted)
Supply voltage
U2730B-N
4719A–DAB–05/03
U2730B-N
Functional Description
The U2730B-N is an L-band down-converter circuit covering a gain-controlled amplifier,
a gain-controlled mixer, an output buffer, a gain control circuitry, an L-band oscillator
and a frequency synthesizer block. Designed for applications in a DAB receiver, the circuit down-converts incoming L-band signals in the frequency range of 1452 MHz to
1492 MHz to an IF frequency in a range of 190 MHz to 230 MHz which can be handled
by a subsequent DAB tuner. A block diagram of this circuit is shown in Figure 1.
Gain-controlled Amplifier RF signals applied to the 'RF' input pin are amplified by a gain-controlled amplifier. The
complementary pin NRF is not internally blocked, it is recommended to block this pin
carefully by an external capacitor. The gain-control voltage is generated by an internal
gain-control circuitry. The output signal of this amplifier is fed to a gain-controlled mixer.
Gain-controlled Mixer
and Output Buffer
The purpose of this mixer is to down-convert the L-band signal in the frequency range of
1452 MHz to 1492 MHz to an IF frequency in the range of about 190 MHz to 230 MHz.
Like the amplifier, the gain of the mixer is controlled by the gain-control circuitry. The IF
signal is buffered and filtered by a one-pole low-pass filter at a 3 dB frequency of about
500 MHz, and then it is fed to the single-ended output pin IF.
Gain-control Circuitry
The gain-control circuitry measures the signal power, compares it with a certain power
level and generates control voltages for the gain-controlled amplifier and mixer. An
equivalent circuit of this functional block is shown in Figure 6.
In order to meet this functionality, the output signal of the buffer amplifier is weakly
band-pass filtered (transition range of about 60 MHz to 550 MHz), rectified, low-pass filtered and fed to a comparator whose threshold can be defined by an external resistor,
RTH, at pin TH. By varying the value of this resistor, a power threshold of about -33 dBm
to -20 dBm can be selected. In order to achieve a good intermodulation ratio, it is recommended to keep the power threshold below -25 dBm. An appropriate application is
shown in Figure 3. Depending on the selection made by the comparator, a charge pump
charges or discharges a capacitor which is applied to the AGC pin. By varying this
capacitor, different time constants of the AGC loop can be realized. The voltage arising
at the AGC pin is used to control the gain setting of the gain-controlled amplifier and
mixer. The voltage at pin AGC is in the range of 5.75 V for maximum gain and 0.3 V for
minimum gain. This voltage can be use to control a dual-gate GaAs-FET in front of the
U2730B-N to achieve an extended AGC range. By applying an external voltage to the
AGC pin, the internal AGC loop can be overdriven.
Voltage-controlled
Oscillator
A voltage-controlled oscillator supplies a LO signal to the mixer. An equivalent circuit of
this oscillator is shown in Figure 7. In the application circuits Figure 8 and Figure 9, a
ceramic coaxial resonator is applied to the oscillator's TANK and VREF pins. It should
be noted that Vref has to be blocked carefully. Figure 9 shows a different application
where the oscillator is overdriven by an external oscillator. In any case, a DC path at a
low impedance must be established between the TANK and VREF pins. The output signal of the oscillator is fed to the LO divider block of the frequency synthesizer unit which
locks the VCO's frequency on the frequency of a reference oscillator. Figure 5 shows
the typical phase-noise performance of the oscillator in locked state.
5
4719A–DAB–05/03
Overall Properties of the
Signal Path
The overall gain of this circuit amounts to 24 dB, the gain-control range is about 30 dB.
With a new AGC concept in the amplifier and mixer, the U2730B-N reaches better intermodulation distances (DIM3) at higher IF output power levels.
Power Save Mode
For VPSM > 2 V (pin 1) the power consumption in the analog part (gain-controlled
amplifier and mixer and gain-controlled circuitry) is reduced by 80%. The VCO and the
PLL is not influenced by the power-down mode.
Frequency Synthesizer
The frequency synthesizer block consists of a reference oscillator, a reference divider, a
LO divider in order to divide the frequency of the internal oscillator, a tri-state phase
detector, a lock detector, a programmable charge pump, a loop filter amplifier, a control
interface and a test interface. The control interface is accessed by three control pins, CI,
SI1 and SI2. The test interface provides test signals which represent output signals of
the reference and the LO divider.
The purpose of this unit is to lock the frequency fVCO of the internal VCO on the frequency fref of the reference signal applied to the input pin OSCB phase-locked loop
according to the following relation:
fVCO = SF ´ fref /SFref
where: SF = 2464,
SFref is the scaling factor of the reference divider according to Table 1
Table 1. Scaling Factors of the Reference Frequency
Reference Oscillator
6
Voltage at Pin SI1
Voltage at Pin SI2
SFref
Reference Oscillator
Frequency
GND
OPEN
36
18.432 MHz
GND
VCC
33
–
GND
GND
48
24.576 MHz
OPEN
OPEN
65
–
OPEN
VCC
63
–
OPEN
GND
64
32.768 MHz
VCC
OPEN
35
17.920 MHZ
VCC
VCC
32
16.384 MHz
VCC
GND
49
–
An on-chip crystal oscillator generates the reference signal which is fed to the reference
divider. By connecting a quartz crystal to pins OSCE and OSCB according to Figure 10,
this oscillator generates a highly stable reference signal. The U2731B (Atmel’s one-chip
front-end IC) offers the reference signal at pin FREF. This reference signal (LC-filtered
to suppress harmonics) can be used to overdrive the oscillator. In this application (see
Figure 11) the reference signal has to be applied to the pin OSCB and the pin OSCE
must be left open.
U2730B-N
4719A–DAB–05/03
U2730B-N
Reference Divider
Nine different scaling factors of the reference divider can be selected by different voltage settings at the input pins SI1, SI2: 32, 33(1), 35, 36, 48, 49(1), 65(1), 64, 63(1). The
reference divider factors result in reference oscillator frequencies shown in Table 1.
Note:
1. These scaling factors result in an output frequency of the reference divider of
512 kHz. If harmonics of the Bd. 3 VCO are falling in the L-band reception band, this
spurious can influence the AGC of U2730B-N. That could be a problem for small
incoming signals. In this case it is possible to switch the reference divider from nref to
nref+1.
LO Divider
The LO divider is operated at the fixed division ratio 2464. Assuming the settings
described in the section “Reference Divider”, the oscillator's frequency is controlled to
be 1261.568 MHz in locked state and the output frequency of the RF divider is 512 kHz.
Phase Comparator,
Charge Pump and Loop
Filter
The tri-state phase detector causes the charge pump to source or to sink current at the
output pin PD depending on the phase relation of its input signals which are provided by
the reference and the RF divider respectively. By means of the control pin CI, two different values of this current can be selected, and furthermore the charge-pump current can
be switched off.
The input of the high-gain amplifier (output pin CD) which is implemented in order to
construct a loop filter, as shown in the application circuit, can be switched to GND by
means of the control pin CI (see Table 2). In the application circuit, the loop filter is completed by connecting the pins PD and CD by an appropriate RC network.
Lock Detector
An internal lock detector checks if the phase difference of the input signals of the phase
detector is smaller than approximately 250 ns in seven subsequent comparisons. If a
phase lock is detected, the open collector output pin PLCK is set to HIGH. It should be
noted that the output current of this pin must be limited by external circuitry as it is not
limited internally. If the voltage at the control pin CI is chosen to be half the supply voltage, or if this control pin is left open, the lock-detector function is deactivated and the
logical value of the PLCK output is undefined.
Test Interface
If the input control pin CI is left open (high impedance state), a test signal which monitors the output frequency of the reference divider appears at the output pin TI.
In analogy to the reference divider a test signal which monitors the output frequency of
the RF divider appears at the test interface output pin TI if the input control pin CI is connected to VCC/2.
Table 2. Control Interface (CI) Settings
CI
PD
PLCK
TI
GND
200 µA
ok
–
Vs
300 µA
ok
–
VCC/2
0 µA
Undefined
RF divider
Open
Connected to GND
Undefined
Reference divider
7
4719A–DAB–05/03
Absolute Maximum Ratings
Parameters
Pins
Supply voltage
3, 9, 20 and 28
RF input voltage
25 and 26
Voltage at pin AGC
18
Voltage at pin TH
17
Input voltage at pin TANK
(internal oscillator overdriven)
5
Symbol
Value
Unit
VCC
-0.3 to +9.5
V
VRF
750
mVpp
VAGC
0.5 to 6
V
VTH
-0.3 to +4.0
V
VTANK
1
Vpp
Current at IF output
19
IIF
4.0
mA
Reference input voltage (diff.)
15
OSCB
1
Vpp
Control input voltage
1, 2, 10 and 27
CI, SI1, SI2, PD
-0.3 to +9.5
V
PLCK output current
14
IPLCK
0.5
mA
PLCK output voltage
14
VPLCK
-0.3 to +5.5
V
Junction temperature
Tj
125
°C
Storage temperature
Tstg
-40 to +125
°C
Symbol
Value
Unit
Operating Range
Parameters
Pins
Supply voltage
3, 9, 20 and 28
VCC
8 to 9.35
V
Tamb
-40 to +85
°C
Symbol
Value
Unit
RthJA
50
K/W
Ambient Temperature
Thermal Resistance
Parameters
Junction ambient SSO28 (mod.)
Electrical Characteristics
Operating conditions: VCC = 8.5 V, Tamb = 25°C, see application circuit (Figure 8), unless otherwise specified
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Supply current (max. gain)
pRF = -60 dBm
VPSM < 0.5 V
IS,MAX
40
48
mA
A
Supply current (min. gain)
pRF = -10 dBm
VPSM < 0.5 V
IS,MIN
41
50
mA
B
Supply current
(power save mode)
pRF = -10 dBm
VPSM > 2 V
IS,PD
20
24
mA
A
24
dB
A
-8
dB
B
26 ® 19
Amplifier Mixer Pin 26
Maximum conversion gain
pRF = -60 dBm
gc,max
Minimum conversion gain
pRF = -15 dBm
gc,min
AGC range
Third order 2 tone
intermodulation ratio
pRF1 + pRF2 = -10 dBm
pRF1 + pRF2 = -15 dBm
20
Dgc
28
32
dB
A
dim3
30
35
35
40
dB
dB
B
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
8
U2730B-N
4719A–DAB–05/03
U2730B-N
Electrical Characteristics (Continued)
Operating conditions: VCC = 8.5 V, Tamb = 25°C, see application circuit (Figure 8), unless otherwise specified
No. Parameters
DSB noise figure
(50-W system)
Test Conditions
Pin
Maximum gain
Minimum gain
RF Input
Min.
Typ.
Max.
10
30
NF
Unit
Type*
dB
dB
D
MHz
C
26
Frequency range
Maximum input power
Symbol
fin,RF
dim3 ³ 20 dB
Input impedance
IF Output
1400
1550
pin,max,RF
-6
dBm
C
Zin,RF
200 || 1
W || pF
D
MHz
C
W
D
19
150
250
Frequency range
fout,IF
Output impedance
Zout,IF
50
VSWRIF
2.0
100
Voltage standing wave ratio
D
Gain Control
Threshold adjustment
Charge pump current
kW
D
125
µA
A
-100
-75
µA
A
0.1
0.6
V
A
V
A
External resistor
17
RTH
pRF = -10 dBm
VAGC = 3.5 V
18
ICP,P
75
100
ICP,N
-125
pRF = -60 dBm
VAGC = 3.5 V
Minimum gain control
voltage
pRF = -10 dBm
18
VAGCmin
Maximum gain control
voltage
pRF = -60 dBm
18
VAGCmax
5.5
5.75
fLO
1000
1261.568
VCO
5
Frequency
Phase noise
1 kHz distance
Minimum input power
VCO over-driven, see
“Application Circuit”
(Figure 8)
Maximum input power
1500
MHz
L1kHz
-75
dBc/Hz
C
pLO,MIN
-11
dBm
C
pLO,MAX
-5
dBm
C
SF
2464
A
SFref
48
33
36
49
32
35
64
63
65
A
Frequency Synthesizer
RF divide factor
Reference divide factor
SI1 = GND, SI2 = GND
SI1 = GND, SI2 = VCC
SI1 = GND, SI2 = open
SI1 = VCC, SI2 = GND
SI1 = VCC, SI2 = VCC
SI1 = VCC, SI2 = open
SI1 = open, SI2 = GND
SI1 = open, SI2 = VCC
SI1 = open, SI2 = open
Input frequency range
fref
Input sensitivity
15
Vrefs
Maximum input signal
15
Vrefmax
Zref
Input impedance
Single-ended
5
50
MHz
C
30
mVrms
C
300
mVrms
C
2.7k || 2.5
kW || pF
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
9
4719A–DAB–05/03
Electrical Characteristics (Continued)
Operating conditions: VCC = 8.5 V, Tamb = 25°C, see application circuit (Figure 8), unless otherwise specified
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Pin CI connected to GND
13
IPD2
160
200
240
µA
A
Pin CI connected to VCC
IPD1
240
300
360
µA
A
Pin CI connected to VCC/2
IPD1,tri
100
nA
A
Phase Detector
Charge-pump current
Output voltage PD
Pin CI open, Pin
13
Internal reference frequency
12
Lock Indication PLCK
14
Leakage current
VPLCK = 5.5 V
Saturation voltage
IPLCK = 0.25 mA
Control Inputs SI
A
B
5
V
C
IPLCK
10
µA
A
VPLCK,sat
0.5
V
A
0.1
VCC
A
Vtune
0.3
2 and 27
Pin connected to GND
VL
Pin open
VM
Pin connected to VCC
VH
0.9
1
VCC
A
VL
0
0.1
VCC
A
VCC
A
Control Input CI
0
open
A
10
Pin connected to GND
Input voltage
V
kHz
512
fPD
Typical tuning voltage range
Input voltage
0.3
VPD
Pin connected to VCC/2
Pin open
0.5
open
VH
Pin connected to VCC
Test Interface TI
VM
Vopen
0.9
A
1
VCC
A
11
Reference test frequency
Pin CI open
ftest,ref
512
kHz
B
LO test frequency
Pin CI = VCC/2
ftest,LO
512
kHz
B
Voltage swing
Rload ³ 1 MW, Cload £
15 pF, Pin CI open or
VCC/2
Vsw
400
mVpp
C
V
A
V
A
Power-save Mode PSM
1
PSM not active
VPSM
PSM active
VPSM
0.6
2.0
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Example: reference divider factor = 35, fREF = 17.92 MHz, charge-pump current = 200 µA
10
U2730B-N
4719A–DAB–05/03
U2730B-N
Gain Control
Charateristics
Operating conditions: VCC = 8.5 V, Tamb = 27°C, fRF = 1490 MHz, FLO = 1261.568 MHz
Figure 3. IF Output Power (Pin 19)
-10
-15
pIF (dBm)
-20
-25
Rth = 100 kW
-30
-35
-40
-60
-50
-40
-30
-20
-10
0
-10
0
pRF (dBm)
Figure 4. Gain Control Voltage (Pin 11)
6
5
Rth = 100 kW
VAGC (V)
4
3
2
1
0
-60
-50
-40
-30
-20
pRF (dBm)
11
4719A–DAB–05/03
Phase-noise
Performance
Measurement conditions:
Values acquired at Pin 19 with HP 70000 spectrum analyzer. RF input (Pin 26) is
blocked with 100 pF to GND.
A low phase-noise signal generator (Marconi 2042) was taken as PLL reference.
Figure 5. Phase-noise Performance operating Conditions: fREF = 17.92 MHz, -10 dB, IPD = 200 µA
RL -29.29 dBm
ATTEN 10 dB
10.00 dB/DIV
< -75 dBc/Hz
Center 1.261 568 GHz
RB 100 Hz VB 100 Hz
12
Span 50.00 kHz
ST 15.00 sec
U2730B-N
4719A–DAB–05/03
U2730B-N
Equivalent Circuits
Figure 6. AGC Control Circuit
Gaincontrolled
mixer
Gaincontrolled
amplifier
VRef1
550 MHz
IF
output
60 MHz
VRef2
AGC
TH
Rth
Figure 7. VCO Circuit
VTune
47k
BBY51
VCC
1.8 p
15 p
TANK
Resonator
1p
VREF
100 p
Resonator: Ceramic coaxial resonator
Murata 3 x 3 mm, 1.6 GHz
DRR030 KE1R600TC
13
4719A–DAB–05/03
Figure 8. Application Circuit
VAGC
3.3 mF
8.5 V
RF
8.5 V
100 pF
IF
100 pF
1 nF
100K
100 pF
18 pF
Quartz
100
10 nF
33 pF
10 nF
100 pF
crystal
1 nF
pF
68 pF
28
27
VCC4 SI1
26
RF
25
24
23
22
21
20
NRF GND GND GND GND VCC3
19
18
IF
AGC
17
16
15
TH OSCE OSCB
U2730B-N
PSM
SI2 VCC1 VREF TANK GND GND GND VCC2
1
2
3
4
5
6
8
7
9
CI
TI
CD
PD PLCK
10
11
12
13
14
Power save
5V
1 pF
100 pF
Lock
10 nF
56K
indication
10 nF
*100 pF
100 pF
100 pF
8.5 V
47K
1 nF
14
1 nF
8.5 V
1.8 pF
15 pF
D1
1K
1K
*3.3
*3.3
nF
nF
* optional
U2730B-N
4719A–DAB–05/03
U2730B-N
Application Circuit
for External LO
Signal
With an external LO signal it is possible to overdrive the VCO. In this case, the internal
VCO acts as a LO buffer.
Figure 9. Application Circuit for External LO Signal
ext. LO signal
(50 W signal gen.)
PLO = -10 dBm
TANK
100 p
470 nH
50
VREF
1n
Figure 10. Reference Oscillator Operation
68 pF
OSCB
Reference devider
33 pF
OSCE
Quartz crystal
18 pF
Figure 11. Rerference Oscillator Overdriven
OSCB
Reference devider
Reference signal
L1
C1
OSCE
15
4719A–DAB–05/03
Ordering Information
Extended Type Number
Package
Remarks
U2730B-NFS
SSO28
Tube
U2730B-NFSG1
SSO28
Taped and reeled according to IEC 286-3
Package Information
5.7
5.3
Package SSO28
Dimensions in mm
9.10
9.01
4.5
4.3
1.30
0.15
0.15
0.05
0.25
6.6
6.3
0.65
8.45
28
15
technical drawings
according to DIN
specifications
1
16
14
U2730B-N
4719A–DAB–05/03
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
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Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Atmel Operations
Memory
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
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Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
e-mail
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Web Site
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