ATMEL ATA6823

Features
• PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors
• A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge
• Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply
the Gate of the External Battery Reverse Protection NMOS
• 5V/3.3V Regulator and Current Limitation Function
• Reset Derived From 5V/3.3V Regulator Output Voltage
• Sleep Mode With Supply Current of Typically < 45 µA, Wake-up by Signal on Pins EN2
•
•
•
•
•
•
or on LIN Interface
A Programmable Window Watchdog
Battery Overvoltage Protection and Battery Undervoltage Management
Overtemperature Warning and Protection (Shutdown)
LIN 2.0 Compliant
3.3V/5V Regulator with Trimmed Band Gap
QFN32 Package
H-bridge Motor
Driver
ATA6823
1. Description
The ATA6823 is designed for several body and powertrain applications. The IC is
used to drive a continuous current motor in a full H-bridge configuration. An external
microcontroller controls the driving function of the IC by providing a PWM signal and a
direction signal and allows the use of the IC in a motor-control application. The PWM
control is performed by the low-side switch; the high-side switch is permanently on in
the driving phase. The VMODE configuration pin can be set to 5V or 3.3V mode (for
regulator and interface high level). The window watchdog has a programmable time,
programmable by choosing a certain value of the external watchdog resistor RWD,
internally trimmed to an accuracy of 10%. For communication a LIN transceiver 2.0 is
integrated.
4856F–AUTO–01/08
Figure 1-1.
Block Diagram
M
CP
VRES
RGATE
RGATE
H2
H1
S1
S2
RGATE
RGATE
L1
L2
PGND
CPLO
GND
Charge
Pump
HS Driver 2
HS Driver 1
LS Driver 1
LS Driver 2
VBAT
CPIH
DG3
OT
UV
12V
Regulator
VG
VBAT
PBAT
OV
OTP
12 bit
CC
CC timer
Oscillator
CP
DG2
DG1
Logic Control
Vint 5V
Regulator
VINT
Supervisor
WD timer
VBAT
EN2
VBG
VBATSW
VCC 5V
Regulator
LIN
LIN
Bandgap
VCC
WD EN1
VCC
/RESET
DIR
PWM
RX
TX
Microcontroller
Battery
2
VMODE
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2. Pin Configuration
Pinning QFN32
EN2
VBATSW
VBAT
VCC
PGND
L1
L2
PBAT
Figure 2-1.
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
Atmel YWW
21
ATA6823
20
ZZZZZ-AL
19
18
17
9 10 11 12 13 14 15 16
VG
CPLO
CPHI
VRES
H2
S2
H1
S1
TX
DIR
PWM
EN1
RX
DG3
DG2
DG1
VMODE
VINT
RWD
CC
/RESET
WD
GND
LIN
Note:
Table 2-1.
YWW
ATA6823
ZZZZZ
AL
Date code (Y = Year - above 2000, WW = week number)
Product name
Wafer lot number
Assembly sub-lot number
Pin Description
Pin
Symbol
I/O
Function
1
VMODE
I
2
VINT
I/O
3
RWD
I
4
CC
I/O
RC combination to adjust cross conduction time
5
/RESET
O
Reset signal for microcontroller
6
WD
I
Watchdog trigger signal
7
GND
I
8
LIN
I/O
9
TX
I
Transmit signal to LIN bus from microcontroller
10
DIR
I
Defines the rotation direction for the motor
11
PWM
I
PWM input controls motor speed
12
EN1
I
Microcontroller output to keep the chip in Active mode
13
RX
O
Receive signal from LIN bus for microcontroller
14
DG3
O
Diagnostic output 3
15
DG2
O
Diagnostic output 2
16
DG1
O
Diagnostic output 1
17
S1
I/O
Source voltage H-bridge, high-side 1
18
H1
O
Gate voltage H-bridge, high-side 1
19
S2
I/O
Source voltage H-bridge, high-side 2
20
H2
O
Gate voltage H-bridge, high-side 2
21
VRES
I/O
Gate voltage for reverse protection NMOS, blocking capacitor 470 nF/25V/X7R
Selector for VCC and interface logic voltage level
Blocking capacitor 220 nF/10V/X7R
Resistor defining the watchdog interval
Ground for chip core
LIN-bus terminal
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Table 2-1.
Pin Description (Continued)
Pin
Symbol
I/O
Function
22
CPHI
I
23
CPLO
O
24
VG
I/O
25
PBAT
I
Power supply (after reverse protection) for charge pump and H-bridge
26
L2
O
Gate voltage H-bridge, low-side 2
27
L1
O
Gate voltage H-bridge, low-side 1
28
PGND
I
Power ground for H-bridge and charge pump
29
VCC
O
5V/100 mA supply for microcontroller, blocking capacitor 2.2 µF/10V/X7R
30
VBAT
I
Supply voltage for IC core (after reverse protection)
31
VBATSW
O
100Ω PMOS switch from VBAT
32
EN2
I
Enable input
Charge pump capacitor 220 nF/25V/X7R
Blocking capacitor 470 nF/25V/X7R
3. General Statement and Conventions
• Parameter values given without tolerances are indicative only and not to be tested in
production
• Parameters given with tolerances but without a parameter number in the first column of
parameter table are “guaranteed by design” (mainly covered by measurement of other
specified parameters). These parameters are not to be tested in production. The tolerances
are given if the knowledge of the parameter tolerances is important for the application
• The lowest power supply voltage is named GND
• All voltage specifications are referred to GND if not otherwise stated
• Sinking current means that the current is flowing into the pin (value is positive)
• Sourcing current means that the current is flowing out of the pin (value is negative)
3.1
Related Documents
• Qualification of integrated circuits according to Atmel® HNO procedure based on AEC-Q100
• AEC-Q100-004 and JESD78 (Latch-up)
• ESD STM 5.1-1998
• CEI 801-2 (only for information regarding ESD requirements of the PCB)
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ATA6823
4. Application
4.1
General Remark
This chapter describes the principal application for which the ATA6823 was designed. Because
Atmel cannot be considered to understand fully all aspects of the system, application and environment, no warranties of fitness for a particular purpose are given.
Table 4-1.
Typical External Components
Component
Function
Value
Tolerance
CVINT
Blocking capacitor at VINT
220 nF, 10V, X7R
10%
CVCC
Blocking capacitor at VCC
2.2 µF, 10V, X7R
10%
CCC
Cross conduction time definition capacitor
Typical 330 pF, 100V, COG
RCC
Cross conduction time definition resistor
Typical 10 kΩ
CVG
Blocking capacitor at VG
470 nF, 25V, X7R
CCP
Charge pump capacitor
220 nF, 25V, X7R
10%
CVRES
Reservoir capacitor
470 nF, 25V, X7R
10%
RRWD
Watchdog time definition resistor
Typical 51 kΩ
1%
CLIN
Filter capacitor for LIN bus
Typical 220 pF, 100V
10%
10%
5. Functional Description
5.1
5.1.1
Power Supply Unit with Supervisor Functions
Power Supply
The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper
external protection circuitry has to be added. It is recommended to use at least a capacitor combination of storage and HF caps behind the reverse protection circuitry and closed to the VBAT
pin of the IC (see Figure 1-1 on page 2).
A fully-internal low-power and low-drop regulator, stabilized by an external blocking capacitor
provides the necessary low-voltage supply needed for the wake-up process. The low-power
band gap reference is trimmed and is used for the bigger VCC regulator, too. All internal blocks
are supplied by the internal regulator.
Note:
The internal supply voltage VINT must not be used for any other supply purpose!
Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V
VCC regulator.
A power-good comparator checks the output voltage of the VINT regulator and keeps the whole
chip in reset as long as the voltage is too low.
There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for measurement purposes. This switch is switched ON for VCC = HIGH and stays ON in case of a
watchdog reset going to sleep mode, VBATSW turns OFF. The signal can be used to switch on
external voltage regulators, etc.
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5.1.2
Voltage Supervisor
This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to manage undervoltage on it.
Function: in case of both overvoltage alarm (VTHOV) and of undervoltage alarm (VTHUV) the external NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2.
No other actions will be carried out. The voltage supervision block is connected to VBAT and filtered by a first-order low pass with a corner frequency of typical 15 kHz.
5.1.3
Temperature Supervisor
There is a temperature sensor integrated on-chip to prevent the IC from overheating due to a
failure in the external circuitry and to protect the external NMOSFET transistors.
In case of detected overtemperature (150°C), the diagnostic pin DG3 will be switched to “H” to
signalize this event to the microcontroller. It should undertake actions to reduce the power dissipation in the IC. In case of detected overtemperature (165°C), the VCC regulator and all drivers
including the LIN transceiver will be switched OFF immediately and /RESET will go LOW.
Both temperature thresholds are correlated. The absolute tolerance is ±10°C and there is a
built-in hysteresis of about 10°C to avoid fast oscillations. After cooling down below the 155°C
threshold; the IC will go into Active mode.
The LIN interface has a separate thermal shutdown with disabled the low-side driver at typically
165°C.
5.2
Sleep Mode
To be able to guarantee the low quiescent current of the inactive IC, a Sleep mode is established. In Sleep mode it is possible to wake-up the IC by using the pins EN2 or LIN. In Sleep
mode, the following blocks are active:
• Band gap
• Internal 5V regulator (VINT) with external blocking capacitor of 220 nF
• Input structure for detecting the EN2 pins threshold
• Wake-up block of the LIN receive part
5.3
Wake-up and Sleep Mode Strategy
The IC has two modes: Sleep and Active. The change between the modes is described below.
The default state after power-on is Active mode.
The wake-up procedure brings the IC from a standby mode (Sleep) to an active mode (Active).
The internal 5V supply VINT, the EN2 pin input structure and a certain part of the LIN receiver
are permanently active to ensure a proper startup of the system.
The Go to Active and Go to Sleep procedures are implemented as follows:
• Go to Active by activating pin EN2
The input EN2 is intended as a switch-on pin from an external signal. Its input structure consists
of a comparator with built-in hysteresis. It is ESD-protected by diodes against GND and VBAT; for
this reason the input voltage level must be positive and not higher than VBAT.
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ATA6823
Pulling the EN2 pin up to the VBAT level will drive the IC into Active mode. EN2 is debounced with
a time constant of 20 µs, based on a 100 kHz clock.
• Go to Active using the LIN interface
The second possibility for wake-up can be performed using the LIN transceiver. In Sleep mode,
the LIN receiver is partially active.
The wake-up by LIN requires 2 steps:
1. If the voltage on pin LIN is below a value of V/DATwake (about VVBAT – 2V) the receive part
of the LIN interface is active (not to be confused with Active mode of the whole IC). The
active receive part is able to detect a valid LOW on the LIN pin.
2. If LIN = LOW during a filter time twakeLIN (typically 70 µs) the IC will change to Active
mode. A short change back to HIGH during the filter time will reset the filter. This information is stored in a latch after entering Active mode
If the change to Active mode was caused by LIN, the EN1 or EN2 pins may remain LOW without
disturbing the Active mode.
• Stay in Active via EN1
The input EN1 is intended to keep the IC in Active Mode via a signal from the microcontroller.
The input is ESD-protected by diodes against GND and VCC. Therefore, the input voltage must
be positive and not higher than VCC. EN1 cannot be used to switch from Sleep to Active because
the VCC regulator is off in the Sleep mode and VCC will be zero.
• Go to Sleep
A HIGH to LOW transition at pin EN1 and a following permanent LOW for the time t gotosleep
(typically 20 µs) switches the IC to Sleep mode.
Figure 5-1 illustrates the wake-up by LIN. The status PREWAKE is characterized by the activated receive block of the LIN interface. After going to Active mode, the VCC regulator starts
working.
Go to Sleep is possible with a valid HIGH to LOW transition at pin EN1 (permanent LOW for
longer than tdb) if EN1 was in a valid HIGH state (HIGH for longer than tdb) before.
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Figure 5-1.
Wake-up by pin LIN
LIN
VBAT
55% VBAT
VBAT - 1.5V
activating
"PREWAKE"
45% VBAT
t
tdb
EN1
t
RX
t < twake LIN
twake LIN
t
STATUS
tdb
ACTIVE
SLEEP
5.4
t
5V/3.3V VCC Regulator
The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2 µF ceramic capacitor for
stability and has 100 mA current capability. Using the VMODE pin, the output voltage can be
selected to either 5V or 3.3V. Switching of the output voltage during operation is not intended to
be supported. The VMODE pin must be hard-wired to either VINT for 5V or to GND for 3.3V. The
logic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage.
The output voltage accuracy is in general < ±3%; in the 5V mode with VVBAT < 8V it is limited to
< 5%.
To prevent destruction of the IC, the current delivered by the regulator is limited to maximum
160 mA to 320 mA. The delivered voltage will break down and a reset may occur.
Please note that this regulator is the main heat source on the chip. The maximum output current
at maximum battery voltage and high ambient temperature can only guaranteed if the IC is
mounted on an efficient heat sink.
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ATA6823
A power-good comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as long as the voltage is too low.
Figure 5-2.
Correlation between VCC Output Voltage and Reset Threshold
5.15V
4.9V
VCC1
4.85V
VtHRESH
4.1V
VCC1-VtHRESH = VCC1 - VtHRESH
The voltage difference between the regulated output voltage and the upper reset threshold voltage is higher than 100 mV.
5.5
Reset and Watchdog Management
The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period TOSC is
adjustable via the external resistor RWD.
The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WD
input within a period time window of TWD. In order to save current consumption, the watchdog is
switched off during Sleep mode.
Figure 5-3.
Timing Diagram of the Watchdog Function
tresshort
tres
/RESET
td
td
t1
t2
t1
t2
WD
5.5.1
Timing Sequence
For example, with an external resistor RWD = 33 kΩ ±1% we get the following typical parameters
of the watchdog.
TOSC = 12.32 µs, t1 = 12.1 ms, t2 = 9.61 ms, TWD = 16.88 ms ±10%
The times tres = 68 ms and td = 68 ms are fixed values with a tolerance of 10%.
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After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. The
reset output, /RESET, stays low for the time tres (typically 68 ms), then switches to high. For an
initial lead time td (typically 68 ms for setups in the controller) the watchdog waits for a rising
edge on WD to start its normal window watchdog sequence. If no rising edge is detected, the
watchdog will reset the microcontroller for tres and wait td for the rising edge on WD.
Times t1 (close window) and t2 (open window) form the window watchdog sequence. To avoid
receiving a reset from the watchdog, the triggering signal from the microcontroller must hit the
timeframe of t2 = 9.61 ms. The trigger event will restart the watchdog sequence.
Figure 5-4.
TWD versus RWD
60
50
typ
TWD (ms)
max
40
30
min
20
10
0
10
20
30
40
50
60
70
80
90
100
RWD (kΩ)
If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms.
The watchdog start sequence is similar to the power-on reset.
The internal oscillator is trimmed to a tolerance of < ±10%. This means that t1 and t2 can also
vary by ±10%. The following calculation shows the worst case calculation of the watchdog
period Twd which the microcontroller has to provide.
t1min = 0.90 × t1 = 10.87 ms, t1max = 1.10 × t1 = 13.28 ms
t2min = 0.90 × t2 = 8.65ms, t2max = 1.10 × t2 = 10.57 ms
Twdmax = t1min + t2min = 10.87 ms + 8.65 ms = 19.52 ms
Twdmin = t1max = 13.28 ms
Twd = 16.42 ms ±3.15 ms (±19.1%)
Figure 5-4 above shows the typical watchdog period TWD depending on the value of the external
resistor ROSC.
A reset will be active for VCC < VtHRESx; the level VtHRESx is realized with a hysteresis (HYSRESth).
5.6
LIN Transceiver
A bi-directional bus interface is implemented for data transfer between the LIN bus and the local
LIN protocol controller.
The transceiver consists of a low side driver (1.2V at 40 mA) with slew rate control, wave shaping, current limitation, and a high-voltage comparator followed by a debouncing unit in the
receiver.
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ATA6823
5.6.1
Transmit Mode
During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus
signal on pin LIN.
To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew
rate control and wave-shaping unit. Transmission will be interrupted in the following cases:
• Thermal shutdown active or overtemperature LIN active
• Sleep mode
Figure 5-5.
Definition of Bus Timing Parameters
tBit
tBit
tBit
TXD
(input to transmitting Node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node 1
THRec(max)
VS
(Transceiver
supply
of transmitting
node)
THDom(max)
LIN Bus Signal
Thresholds of
receiving node 2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(output of receiving Node 1)
trx_pdf(1)
trx_pdr(1)
RXD
(output of receiving Node 2)
trx_pdr(2)
trx_pdf(2)
The recessive BUS level is generated from the integrated 30 kΩ pull-up resistor in series with an
active diode. This diode prevents the reverse current of VBUS during differential voltage
between VSUP and BUS (VBUS > VSUP).
No additional termination resistor is necessary to use the ATA6823 in LIN slave nodes. If this IC
is used for LIN master nodes, it is necessary that the BUS pin be terminated via an external 1 kΩ
resistor in series with a diode to VBAT.
5.6.2
TXD Dominant Time-out Function
The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from
being driven permanently in dominant state. If TXD is forced low longer than tdom > 18.4 ms, the
pin LIN will be switched off to recessive mode. To reset this mode switch TXD to high (> 10 µs)
before switching LIN to dominant again.
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5.7
5.7.1
Control Inputs EN1, EN2, DIR, PWM
Pins EN1, EN2
Any of the enable pins may be used to activate the IC with a HIGH. EN1 is a low level input, EN2
has to withstand a voltage up to 40V. Internal pull-down resistors are included.
5.7.2
Pin DIR
Logical input to control the direction of the external motor to be controlled by the IC. An internal
pull-down resistor is included.
5.7.3
Pin PWM
Logical input for PWM information delivered by external microcontroller. Duty cycle and frequency at this pin are passed through to the H-bridge. An internal pull-down resistor is included.
Table 5-1.
Status of the IC Depending on Control Inputs and Detected Failures
Control Inputs
ON
DIR
0
1
1
Driver Stage for External Power MOS
H2
Comments
PWM
H1
L1
L2
X
X
OFF
OFF
OFF
OFF
Standby mode
0
PWM
ON
OFF
/PWM
PWM
Motor PWM forward
1
PWM
/PWM
PWM
ON
OFF
Motor PWM reverse
The internal signal ON is high when
• At least one valid trigger has been accepted (SYNC = 1)
• VBAT is inside the specified range (UV = 0 and nOV = 1)
• The charge pump has reached its minimum voltage (CPOK = 1) and
• The device is not overheated (OT2 = 0)
In case of a short circuit, the appropriate transistor is switched off after a debounce time of about
10 µs. In order to avoid cross current through the bridge, a cross conduction timer is implemented. Its time constant is programmable by means of an RC combination.
Table 5-2.
Status of the Diagnostic Outputs
Device Status
Diagnostic Outputs
CPOK
OT1
OV
UV
SC
DG1
DG2
DG3
Comments
0
X
X
X
X
–
1
–
Charge pump failure
X
1
X
X
X
–
–
1
Overtemperature warning
X
X
1
X
X
–
1
–
Overvoltage
X
X
X
1
X
–
1
–
Undervoltage
X
X
X
1
1
X represents: don't care – no effect)
OT1: Overtemperature warning
OV: Overvoltage of VBAT
UV: Undervoltage of VBAT
SC: Short circuit
CPOK: Charge pump OK
–
–
Short circuit
X
Note:
In order to be able to distinguish between a wake-up from LIN or from EN2, the source of
wake-up is flagged in DG1 until the first valid trigger (LIN = 0, EN2 = 1).
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5.8
VG Regulator
The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage
will be used as one input for the charge pump, which generates the gate voltage for the
high-side driver. The purpose of the regulator is to limit the gate voltage for the external power
MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage
is reduced if the supply voltage at VBAT falls below 12V.
5.9
Charge Pump
The integrated charge pump is needed to supply the gates of the external power MOS transistors. It needs a shuffle capacitor of 220 nF and a reservoir capacitor of 470 nF. Without load, the
output voltage on the reservoir capacitor is VBAT plus VG. The charge pump is clocked with a
dedicated internal oscillator of 100 KHz. The charge pump is designed to reach a good EMC
level.
5.10
Thermal Shutdown
There is a thermal shutdown block implemented. With rising junction temperature, a first warning
level will be reached at 150°C. At this point the IC stays fully functional and a warning will be
sent to the microcontroller. At junction temperature 165°C the VCC regulator will be switched off
and a reset occurs.
5.11
H-bridge Driver
The IC includes two push-pull drivers for control of two external power NMOS used as high-side
drivers and two push-pull drivers for control of two external power NMOS used as low-side drivers. The drivers are able to be used with standard and logic-level power NMOS.
The drivers for the high-side control use the charge pump voltage to supply the gates with a voltage of VG above the battery voltage level. The low-side drivers are supplied by VG directly. It is
possible to control the external load (motor) in the forward and reverse direction (see Table 5-1
on page 12). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible in
both directions.
5.11.1
Cross Conduction Time
To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the external power NMOS is realized. An external RC combination defines the cross conduction time in
the following way:
tCC (µs) = 0.41 × RCC (kΩ) × CCC (nF) (tolerance: ±5% ±0.15 µs)
The RC combination is charged to 5V and the switching level of the internal comparator is 67%
of the start level.
The resistor RCC must be greater than 5 kΩ and should be as close as possible to 10 kΩ, the CCC
value has to be ≤5 nF. Use of COG capacitor material is recommended.
The time measurement is triggered by the PWM or DIR signal crossing the 50% level.
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Figure 5-6.
Timing of the Drivers
PWM or
DIR
50%
t
tLxHL
tLxf
tLxLH
tLxr
80%
tCC
Lx
20%
t
tHxLH
tCC
tHxr
tHxHL
tHxf
80%
Hx
20%
t
The delays tHxLH and tLxLH include the cross conduction time tCC.
5.12
Short Circuit Detection
To detect a short in H-bridge circuitry, internal comparators detect the voltage difference
between source and drain of the external power NMOS. If the transistors are switched ON and
the source-drain voltage difference is higher than the value VSC (4V with tolerances) for a time
> tSC (typically 10 µs) the signal SC (short circuit) will be set and the drivers will be switched off
immediately. The diagnostic pin DG1 will be set to “H”. With the next transition on pin PWM, the
bit will be cleared and the corresponding drivers, depending on the DIR pin, will be switched on
again.
There is a PBAT supervision block implemented to detect the possible voltage drop on PBAT
during a short circuit. If the voltage at PBAT falls under VSCPB (5.6V with tolerances) for a time
> tSC the drivers will be switched off immediately and DG1 will be set to “H”. It will be cleared as
above.
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6. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Pin Description
Ground
Pin Name
Min
Max
Unit
GND
0
0
V
Power ground
PGND
–0.3
+0.3
V
Reverse protected battery voltage
VBAT
–0.3
+40
V
Reverse protected battery voltage
PBAT
–0.3
+40
V
Digital output
/RESET
–0.3
VVCC + 0.3
V
Digital output
DG1, DG2, DG3
–0.3
VVCC + 0.3
V
4.9V output, external blocking capacitor
VINT
–0.3
+5.5
V
Cross conduction time capacitor/resistor
combination
CC
–0.3
VVINT + 0.3
V
Digital input coming from microcontroller
WD
–0.3
VVINT + 0.3
V
RWD
–0.3
VVCC + 0.3
V
DIR
–0.3
VVCC + 0.3
V
Watchdog timing resistor
Digital input direction control
Digital input PWM control + Test mode
PWM
–0.3
VVCC + 0.3
V
Digital input for enable control
EN1
–0.3
VVCC + 0.3
V
Digital input for enable control
EN2
–0.3
VVBAT + 0.3
V
5V regulator output
VCC
–0.3
+5.5
V
VMODE
–0.3
VVINT + 0.3
V
12V output, external blocking capacitor
VG
–0.3
+16
V
Digital output
RX
–0.3
VVCC + 0.3
V
Digital input
TX
–0.3
VVCC + 0.3
V
VVBAT + 2
V
Digital input
LIN data pin
LIN
–27
(1)
Source external high-side NMOS
S1, S2
–2
+30
V
Gates external low-side NMOS
L1, L2
VPGND – 0.3
VVG + 0.3
V
Gates of external high-side NMOS
H1, H2
VS – 1
VS + 16
V
Charge pump
CPLO
–0.3
VPBAT + 0.3
V
Charge pump
CPHI
–0.3
VVRES + 0.3
V
Charge pump output
VRES
–0.3
+30
V
VBATSW
–0.3
VVBAT + 0.3
V
Switched VBAT
Power dissipation
Storage temperature
Soldering temperature (10s)
Notes:
1.4
Ptot
ϑ STORE
ϑ SOLDERING
–40
(2)
W
+150
°C
240
°C
1. For VVBAT ≤ 13.5V
2. May be additionally limited by external thermal resistance
15
4856F–AUTO–01/08
7. Thermal Resistance
Parameters
Symbol
Value
Unit
Thermal resistance junction to heat slug
Rthjc
<5
K/W
Thermal resistance junction to ambient when heat
slug is soldered to PCB
Rthja
25
K/W
8. Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these
limits is not implied unless otherwise stated explicitly.
Parameters
Symbol
Min
Max
Unit
Operating supply voltage
(1)
VVBAT1
7
18
V
Operating supply voltage
(2)
VVBAT2
6
<7
V
Operating supply voltage
(3)
VVBAT3
3
<6
V
Operating supply voltage
(4)
VVBAT4
0
<3
V
Operating supply voltage
(5)
VVBAT5
> 20
40
V
Ta
–40
+125
°C
Normal functionality
Ta
–40
+125
°C
Normal functionality, overtemperature warning
Ta
150
165
°C
Drivers for H1, H2, L1, L2, and LIN are switched
OFF, VCC regulator is OFF
Ta
165
180
°C
Ambient temperature range under bias
Note:
1. Full functionality
2. H-bridge drivers may be switched off (undervoltage detection)
3. H-bridge drivers are switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly
4. H-bridge drivers are switched off, 5V regulator not working, RESET not correct
5. H-bridge drivers are switched off
16
ATA6823
4856F–AUTO–01/08
ATA6823
9. Electrical Characteristics
All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise.
No.
Parameters
Test Conditions
Pin
Symbol
Min
Typ
Max
Unit
Type*
1
Power Supply and Supervisor Functions
1.1
Current consumption VBAT VVBAT = 13.5V(1)
25, 30
IVBAT1
7
mA
A
1.2
Current consumption VBAT
VVBAT =13.5V
in Standby mode
25, 30
IVBAT2
50
µA
A
1.3
Internal power supply
2
VINT
4.8
4.94
5.1
V
A
1.4
Band gap voltage
VBG
1.225
1.235
1.245
V
A
1.5
Overvoltage threshold
VBAT
30
VTHOV
19.8
22.3
V
A
1.6
Overvoltage threshold
hysteresis VBAT
30
VTOVhys
1
1.5
V
A
1.7
Undervoltage threshold
VBAT
30
VTHUV
6.5
7
V
A
1.8
Undervoltage threshold
hysteresis VBAT
Measured during
qualification only
30
VTUVhys
0.2
0.4
V
A
1.9
On resistance of VBAT
switch
VVBAT = 13.5V
31
RON_VBATSW
100
Ω
A
2
Measured during
qualification only
5V/3.3V Regulator
2.1
Regulated output voltage
9V < VVBAT < 40V
Iload = 0 mA to 100 mA
29
VCC1
4.85
(3.2)
5.15
(3.4)
V
A
2.2
Regulated output voltage
6V < VVBAT ≤ 9V
Iload = 0 mA to 100 mA
29
VCC2
4.75
(3.2)
5.25
(3.4)
V
A
2.3
Line regulation
Iload = 0 mA to 100 mA
29
DC line
regulation
<1
50
mV
A
2.4
Load regulation
Iload = 0 mA to 100 mA
29
DC load
regulation
<10
50
mV
A
2.5
Output current limitation
VVBAT > 6V
29
IOS1
100
300
mA
C
2.6
Serial inductance to CVCC
including PCB
29
ESL
1
20
nH
D
2.7
Serial resistance to CVCC
including PCB
29
ESR
0
0.5
Ω
D
2.8
Blocking cap at VCC
29
CVCC
1.5
3.0
µF
D
(2), (3)
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high
2. The use of X7R material is recommended
3. For higher values, stability at zero load is not guaranteed
4. Tested during qualification only
5. Value depends on TOSC; function tested with digital test pattern
6. Tested during characterization only
7. Supplied by charge pump
8. See section “Cross Conduction Time”
9. Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
17
4856F–AUTO–01/08
9. Electrical Characteristics (Continued)
All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise.
No.
Parameters
2.9
2.10
Test Conditions
Pin
Symbol
HIGH threshold VMODE
1
VMODE H
LOW threshold VMODE
1
VMODE L
Min
Typ
Max
Unit
Type*
4.0
V
A
V
A
V
A
V
A
V
A
0.7
3
Reset and Watchdog
3.1
VCC threshold voltage
level for /RESET
VMODE = “H”
(VMODE = “L”)
29
VtHRESH
3.2
VCC threshold voltage
level for /RESET
VMODE = “H”
(VMODE = “L”)
29
VtHRESL
4.1 (2.7)
3.3
Hysteresis of /RESET
level
VMODE = “H”
(VMODE = “L”)(4)
29
HYSRESth
70
3.4
Length of pulse at
/RESET pin
(5)
5
tres
6800
T100
A
3.5
Length of short pulse at
/RESET pin
(5)
5
tresshort
200
T100
A
3.6
Wait for the first WD
trigger
(5)
5
td
6800
T100
A
3.7
Time for VCC < VtHRESL
before activating /RESET
(4)
29
tdelayRESL
0.5
2
µs
C
3.8
Resistor defining internal
bias currents for
watchdog oscillator
3
RRWD
10
91
kΩ
D
3.9
Watchdog oscillator
period
3
TOSC
11.09
13.55
µs
A
3.10
Watchdog oscillator
period with internal
resistor
TOSC_start
16
24
µs
A
3.11
Watchdog input
low-voltage threshold
6
VILWD
0.3 ×
VVCC
V
A
3.12
Watchdog input
high-voltage threshold
6
VIHWD
V
A
3.13
Hysteresis of watchdog
input voltage threshold
6
VhysWD
1
V
A
3.14
Close window
t1
980 ×
TOSC
RRWD = 33 kΩ
(5)
4.6
(3.05)
0.2
0.7 ×
VVCC
350
(220)
A
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high
2. The use of X7R material is recommended
3. For higher values, stability at zero load is not guaranteed
4. Tested during qualification only
5. Value depends on TOSC; function tested with digital test pattern
6. Tested during characterization only
7. Supplied by charge pump
8. See section “Cross Conduction Time”
9. Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
18
ATA6823
4856F–AUTO–01/08
ATA6823
9. Electrical Characteristics (Continued)
All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise.
No.
Parameters
Test Conditions
3.15
Open window
(5)
3.16
Output low-voltage of
/RESET
At IOLRES = 1 mA
3.17
Internal pull-up resistor at
pin /RESET
4
Pin
Symbol
Min
Typ
Max
Unit
780 ×
TOSC
t2
5
VOLRES
5
RPURES
5
10
Type*
A
0.4
V
A
15
kΩ
D
Lin Transceiver
4.1
Low-level output current
Normal mode;
VLIN = 0V, VRX = 0.4V
13
ILRX
4
mA
D
4.2
High-level output current
Normal mode;
VLIN = VBAT
VRX = VCC – 0.4V
13
IHRX
4
mA
D
4.3
Driver recessive output
voltage
VTXD = 0V; ILIN = 0 mA
8
VBUSrec
0.9 ×
VBAT
V
4.4
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVAT = 7.3V
Rload = 500Ω
8
V_LoSUP
1.2
V
4.5
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVAT = 18V
Rload = 500Ω
8
V_HiSUP
2
V
4.6
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVAT = 7.3V
Rload = 1000Ω
8
V_LoSUP_1k
0.6
V
4.7
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVAT = 18V
Rload = 1000Ω
8
V_HiSUP_1k_
0.8
V
4.8
Pull up resistor to VS
The serial diode is
mandatory
8
RLIN
20
4.9
Current limitation
VBUS = VBAT_max
8
IBUS_LIM
50
4.10
Input leakage current at
the receiver including
pull-up resistor as
specified
Input leakage current
driver off
VBUS = 0V
VBAT = 12V
8
IBUS_PAS_dom
–1
4.11
Leakage current LIN
recessive
Driver off
8V < VBAT < 18V
8V < VBUS < 18V
VBUS ≥ VBAT
8
IBUS_PAS_rec
30
60
kΩ
200
mA
D
mA
20
µA
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high
2. The use of X7R material is recommended
3. For higher values, stability at zero load is not guaranteed
4. Tested during qualification only
5. Value depends on TOSC; function tested with digital test pattern
6. Tested during characterization only
7. Supplied by charge pump
8. See section “Cross Conduction Time”
9. Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
19
4856F–AUTO–01/08
9. Electrical Characteristics (Continued)
All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise.
No.
Parameters
Pin
Symbol
Min
4.12
Leakage current at
ground loss
Control unit disconnected GNDDevice = VS
from ground
VBAT =12V
Loss of local ground must 0V < VBUS < 18V
not affect communication
in the residual network
8
IBUS_NO_gnd
–1
4.13
Node has to sustain the
current that can flow
VBAT disconnected
under this condition. Bus VSUP_Device = GND
must remain operational 0V < VBUS < 18V
under this condition
8
IBUS
4.14
Center of receiver
threshold
VBUS_CNT =
(Vth_dom + Vth_rec)/2
8
VBUS_CNT
4.15
Receiver dominant state
VEN = 5V
8
VBUSdom
4.16
Receiver recessive state
VEN = 5V
8
VBUSrec
4.17
Receiver input hysteresis VHYS = Vth_rec – Vth_dom
8
VBUShys
4.18
Dominant time for
wake-up via LIN-bus
8
TBUS
5
Test Conditions
VLIN = 0V
0.475 VS
Typ
0.5 VS
Max
Unit
1
mA
100
µA
0.525 VS
V
0.4 VS
V
0.6 VS
30
Type*
V
0.1 VS
0.175 VS
V
90
150
µs
D
0.3 ×
VVCC
V
A
V
A
Control Inputs EN1, DIR, PWM, WD, TX
5.1
Input low-voltage
threshold
VIL
5.2
Input high-voltage
threshold
VIH
5.3
Hysteresis
(6)
HYS
5.4
Pull-down resistor
EN1, DIR, PWN, WD
RPD
25
50
100
kΩ
5.5
Pull-up resistor
TX
RPU
25
50
100
kΩ
D
5.6
Rise/fall time
100
ns
D
5.7
Debounce time EN1
3 × T100
µs
D
VVBAT
+ VVG
V
A
V
A
6
0.7 ×
VVCC
0.7
A
trf
(6)
tdb
2 × T100
D
Charge Pump
6.1
Charge pump voltage
Load = 0A
21
VCP
6.2
Charge pump voltage
Load = 3 mA,
CCP = 100 nF
21
VCP
VVBAT
+ VVG – 1
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high
2. The use of X7R material is recommended
3. For higher values, stability at zero load is not guaranteed
4. Tested during qualification only
5. Value depends on TOSC; function tested with digital test pattern
6. Tested during characterization only
7. Supplied by charge pump
8. See section “Cross Conduction Time”
9. Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
20
ATA6823
4856F–AUTO–01/08
ATA6823
9. Electrical Characteristics (Continued)
All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise.
No.
Parameters
6.3
Period charge pump
oscillator
6.4
CP load current in VG
without CP load
Load = 0A
6.5
CP load current in VG
with CP load
Load = 3 mA,
CCP = 100 nF
7
Test Conditions
Pin
Symbol
Min
T100
9
Typ
Max
Unit
Type*
11
µs
A
IVGCPz
100
µA
D
IVGCP
3.3
mA
A
H-bridge Driver
7.1
Low-side driver HIGH
output voltage
VLxH
VVG
V
D
7.2
ON-resistance of sink
stage of pins L1, L2
RDSON_LxL,
x = 1, 2
20
Ω
A
7.3
ON-resistance of source
stage of pins L1, L2
RDSON_LxH,
x = 1, 2
20
Ω
A
7.4
Output peak current at
pins L1, L2, switched to
LOW
VLx = 3V
ILxL,
x = 1, 2
mA
D
7.5
Output peak current at
pins L1, L2, switched to
HIGH
VLx = 3V
ILxH,
x = 1, 2
–100
mA
D
7.6
Pull-down resistance at
pins L1, L2
100
kΩ
A
7.7
ON-resistance of sink
stage of pins H1, H2
VSx = 0
RDSON_HxL,
x = 1, 2
20
Ω
A
7.8
ON-resistance of source
stage of pins H1, H2
VSx = VVBAT
RDSON_HxH,
x = 1, 2
20
Ω
A
7.9
VVBAT = 13.5V
Output peak current at
V = VVBAT
pins Hx, switched to LOW Sx
VHx = VVBAT + 3V
IHxL,
x = 1, 2
mA
D
7.10
Output peak current at
pins Hx, switched to
HIGH
VVBAT = 13.5V
VSx = VVBAT
VHx = VVBAT + 3V
IHxH,
x = 1, 2
–100
mA
D
7.11
Static high-side switch
output low-voltage pins
Hx
VSx = 0V
IHx = 1 mA
VHxL,
x = 1, 2
0.3
V
RPDLx
x = 1, 2
100
30
100
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high
2. The use of X7R material is recommended
3. For higher values, stability at zero load is not guaranteed
4. Tested during qualification only
5. Value depends on TOSC; function tested with digital test pattern
6. Tested during characterization only
7. Supplied by charge pump
8. See section “Cross Conduction Time”
9. Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
21
4856F–AUTO–01/08
9. Electrical Characteristics (Continued)
All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise.
No.
Parameters
Test Conditions
7.12
Static high-side switch
output high-voltage pins
H1, H2
ILx = –10 µA
(PWM = static)
7.13
Sink resistance between
Hx and ground in Sleep
mode
Pin
Symbol
Min
VHxHstat1(7)
Typ
Max
Unit
VVBAT +
VVG – 1
VVBAT +
VVG
V
RHxsleep
3
10
kΩ
VHxHdyn1
VVBAT +
VVG – 1
VVBAT +
VVG
V
tLxHL
0.5
µs
tLxLH
0.5 + tCC
µs
tLxf
0.5
µs
tLxr
0.5
µs
Type*
Dynamic Parameters
7.14
Dynamic high-side switch CHx = 5 nF
output high-voltage pins CCB = 100 nF
fPWM = 20 kHz
H1, H2
7.15
Propagation delay time,
low-side driver from high
to low
7.16
Propagation delay time,
low-side driver from low to
high
7.17
Fall time low-side driver
7.18
Rise time low-side driver
7.19
Propagation delay time,
Figure 5-6 on page 14
high-side driver from high
VVBAT = 13.5V
to low
tHxHL
0.5
µs
7.20
Propagation delay time,
high-side driver from low
to high
tHxLH
0.5 + tCC
µs
7.21
Fall time high-side driver
tHxf
0.5
µs
7.22
Rise time high-side driver
tHxr
0.5
µs
tCC
10
µs
7.23
Cross conduction time
Figure 5-6 on page 14
VVBAT = 13.5V
VVBAT = 13.5V
CGx=5 nF
VVBAT = 13.5V,
CGx = 5 nF
(8)
5
kΩ
7.24
External resistor
RCC
7.25
External capacitor
CCC
5
nF
7.26
RON of tCC switching
transistor
RONCC
100
Ω
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high
2. The use of X7R material is recommended
3. For higher values, stability at zero load is not guaranteed
4. Tested during qualification only
5. Value depends on TOSC; function tested with digital test pattern
6. Tested during characterization only
7. Supplied by charge pump
8. See section “Cross Conduction Time”
9. Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
22
ATA6823
4856F–AUTO–01/08
ATA6823
9. Electrical Characteristics (Continued)
All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ ϑambient ≤ 125°C unless stated otherwise.
No.
Parameters
7.27
Switching level of tCC
comparator
7.28
Short circuit detection
voltage
7.29
Short circuit detection
time
8
Test Conditions
Pin
Symbol
Min
Typ
Max
Unit
Vswtcc
0.653 ×
VVCC
0.667 ×
VVCC
0.68 ×
VVCC
V
(9)
VSC
3.5
4
4.5
V
(10)
tSC
5
10
15
ms
Input EN2
8.1
Input low-voltage
threshold
VIL
2.3
3.6
V
8.2
Input high-voltage
threshold
VIH
2.8
4.0
V
8.3
Hysteresis
8.4
Pull-down resistor
8.5
Rise/fall time
8.6
Debounce time
9
9.1
9.2
Type*
(6)
HYS
0.47
50
RPD
V
100
200
kΩ
100
ns
3 × T100
µs
trf
(6)
tdb
2 × T100
IL
4
mA
IH
4
mA
Diagnostic Outputs DG1, DG2, DG3
Low level output current
High level output current
VDG = 0.4V(6)
VDG = VCC – 0.4V
(6)
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high
2. The use of X7R material is recommended
3. For higher values, stability at zero load is not guaranteed
4. Tested during qualification only
5. Value depends on TOSC; function tested with digital test pattern
6. Tested during characterization only
7. Supplied by charge pump
8. See section “Cross Conduction Time”
9. Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
23
4856F–AUTO–01/08
10. Schaffner and Electromagnetic Compatibility
10.1
Transients on Power-supply Rail (Battery)
The application (including IC and external protection circuitry, see Figure 1-1 on page 2) has to
withstand the test pulses in Table 10-1.
Table 10-1.
Test Pulses
Test
Pulse No.
Test
Level
Duration or Number
of Pulses
Specs
Acceptance
level
1
–100V
10 min
Ri = 10Ω
A
2
150V
10 min
Ri = 10Ω
A
3a
–200V
10 min
Ri = 50Ω
A
3b
200V
10 min
Ri = 50Ω
A
A
B
4
4V/5.5V
15 ms/2s
Ri = 0.01Ω
5
40V
5 pulses, 1 minute
recurrence period
Ri = 0.5Ω, td = 400 ms, tr = 5 ms
Figure 10-1. Pulse 1 (Ri = 10Ω)
200 ms
V
< 100 µs
12V
t
10%
90%
-100V
1 µs
1 ms
5s
Figure 10-2. Pulse 2 (Ri = 10Ω)
200 ms
50 µs
V
2 µs
150V
90%
10%
12V
50 µs
24
t
ATA6823
4856F–AUTO–01/08
ATA6823
Figure 10-3. Pulse 3a (Ri = 50Ω)
100 ns
V
10 ms
90 ms
5 ns
12V
10%
t
90%
-200V
100 µs
Figure 10-4. Pulse 3b (Ri = 50Ω)
V
100 µs
200V
90%
10%
12V
10 ms
t
90 ms
5 ns
100 ns
Figure 10-5. Pulse 4 (Ri = 0.01Ω)
12V
5.5V
4.0V
0V
< 5 ms
t
15 ms
50 ms
2000 ms
100 ms
25
4856F–AUTO–01/08
10.2
Transients on Pin LIN
Transients to these pins are coupled capacitively to the IC and are valid for the application with
external circuitry concerning figure 6.
Values: Pulse 3a, Pulse 3b (see Figure 10-3 and Figure 10-4 on page 25) coupled via 1 nF to
LIN, Ri = 50Ω
Acceptance level A
10.3
Conducted Emissions, Radiated Emissions and Susceptibility
The application using the IC described in this specification has to fulfill the demands of the following specifications:
• GM GMW3100 (2001-08)
• TL82166 (1998-02)
• TL82366 (2002-03)
• TL965 (1999-10)
It is the responsibility of both the deliverer and the user of the described IC to meet the mentioned specifications.
11. ESD and Latch-up Requirements
The device withstands pulses when tested according to ESD STM 5.1-1998:
• Constant voltage 2 kV
• R = 1.5 kΩ
• C = 100 pF
1 pulse per polarity and per pin
3 samples, 0 failures
Electrical post stress testing at room temperature
Static latch-up tested according to AEC-Q100-004 and JESD78.
• 3 to 6 samples, 0 failures
• Electrical post stress testing at room temperature
In test, the voltage at the pins VBAT, LIN, CP, VBATSW, Hx, and Sx must not exceed 45V when
not able to drive the specified current.
26
ATA6823
4856F–AUTO–01/08
ATA6823
12. Ordering Information
Extended Type Number
Package
Remarks
ATA6823-PHQW
QFN32
Pb-free
13. Package Information
Package: QFN 32 - 7 x 7
Exposed pad 4.7 x 4.7
Dimensions in mm
Not indicated tolerances ± 0.05
7
0.9±0.1
4.7
+0
0.05-0.05
32
25
1
32
24
1
technical drawings
according to DIN
specifications
17
0.6
0.3
8
Drawing-No.: 6.543-5097.01-4
8
16
9
0.65 nom.
4.55
Issue: 1; 24.02.03
14. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4856F-AUTO-01/08
• Section 5.4 “5V/3.3V VCC Regulator” on pages 8 to 9 changed
• Section 10 “Electrical Characteristics” number 3.3 on page 18 changed
• Section 12 “Ordering Information” on page 27 changed
4856E-AUTO-07/07
• Put datasheet in a new template
27
4856F–AUTO–01/08
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4856F–AUTO–01/08