Atmel AT24CS01 and AT24CS02 I2C-Compatible (2-wire) Serial EEPROM with a Unique, Factory Programmed 128-bit Serial Number 1-Kbit (128 x 8), 2-Kbit (256 x 8) PRELIMINARY DATASHEET Standard Features Low-voltage operation VCC = 1.7V to 5.5V Internally organized as 128 x 8 (1-Kbit) or 256 x 8 (2-Kbit) I2C-compatible (2-wire) serial interface Schmitt Trigger, filtered inputs for noise suppression Bidirectional data transfer protocol 400kHz (1.7V) and 1MHz (2.5V, 5.0V) compatibility Write Protect pin for hardware data protection 8-byte page write mode Partial page writes allowed Self-timed write cycle (5ms max) High-reliability Endurance: 1,000,000 write cycles Data retention: 100 years Green package options (Pb/Halide-free/RoHS-compliant) 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 5-lead SOT23 Die sale options: wafer form and tape and reel available Enhanced Features in the CS Serial EEPROM Series All standard features supported 128-bit unique factory-programmed serial number Permanently locked, read-only value Stored in a separate memory area Guaranteed unique across entire CS Series of Serial EEPROMs 8815A–SEEPR–6/12 1. Description The Atmel® AT24CS01 and AT24CS02 provides 1024/2048 bits of Serial Electrically Erasable and Programmable Read-only Memory (EEPROM) organized as 128/256 words of eight bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24CS01/02 is available in space-saving, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN and 5-lead SOT23 packages and is accessed via a 2-wire serial interface. In addition, both devices fully operate from 1.7V to 5.5V VCC. The AT24CS01/02 provides the additional feature of a factory programmed, guaranteed unique 128-bit serial number, while maintaining all of the traditional features available in the 1-Kbit or 2-Kbit Serial EEPROM. The time consuming step of performing and ensuring true serialization of product on a manufacturing line can be removed from the production flow by employing the CS Series Serial EEPROM. The 128-bit serial number is programmed and permanently locked from future writing during the Atmel production process. Further, this 128-bit location does not consume any of the user read/write area of the 1-Kbit or 2-Kbit Serial EEPROM. The uniqueness of the serial number is guaranteed across the entire CS Series of Serial EEPROMs, regardless of the size of the memory array or the type of interface protocol. This means that as an application's needs for memory size or interface protocol evolve in future generations, any previously deployed serial number from any Atmel CS Series Serial EEPROM part will remain valid. 2. Pin Descriptions and Pinout Figure 2-1. Pin Configuration 8-lead SOIC Pin Name Function A0 - A2 8-lead TSSOP A0 1 8 VCC A0 1 8 VCC Address Inputs A1 2 7 WP A1 2 7 WP SDA Serial Data A2 3 6 SCL A2 3 6 SCL SCL Serial Clock Input GND 4 5 SDA GND 4 5 SDA WP Write Protect GND Ground VCC Power Supply 5-lead SOT23 8-pad UDFN VCC 8 1 A0 WP 7 2 A1 SCL 6 3 A2 SDA 5 4 GND SCL 1 GND 2 SDA 3 5 WP 4 VCC Bottom View Note: For use of 5-lead SOT23, the software A2, A1, and A0 bits in the device address word must be set to zero to properly communicate with the device. Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 2 Absolute Maximum Ratings *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature ........................–55C to +125C Storage Temperature ...........................–65C to +150C Voltage on any pin with respect to ground .............................–1.0V to +7.0V Maximum Operating Voltage ................................. 6.25V DC Output Current................................................ 5.0mA 4. Block Diagram Figure 4-1. Block Diagram VCC GND WP Start Stop Logic SCL SDA Serial Control Logic Device Address Comparator Data Latches A1 A0 Read Load COMP Read/Write A2 High Voltage Pump & Timing Enable INC Data Word ADDR/Counter 128-bit Serial Number Row Decoder 3. EEPROM Array Column Decoder Serial MUX DOUT / ACK Logic DOUT DIN Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 3 5. Pin Description Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. Device/Page Addresses (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24CS01/02. As many as eight 1-Kbit or 2-Kbit devices may be addressed on a single bus system. For more detail, see section, “Device Addressing” on page 10. Write Protect (WP): AT24CS01/02 has a Write Protect (WP) pin that provides hardware data protection. When the Write Protect pin is connected to ground (GND), normal read/write operations to the full array are possible. When the Write Protect pin is connected to VCC, all write operations to the memory are inhibited but read operations are still possible. This operation is summarized in Table 5-1 below. Table 5-1. WP Pin Status Write Protect Part of the Array Protected Atmel AT24CS01/02 At VCC Full Array At GND Normal Read/Write Operations Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 4 6. Memory Organization Atmel AT24CS01, 1K Serial EEPROM: Internally organized with 16 pages of eight bytes each, the 1K requires a 7-bit data word address for random word addressing. Atmel AT24CS02, 2K Serial EEPROM: Internally organized with 32 pages of eight bytes each, the 2K requires an 8-bit data word address for random word addressing. Table 6-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0MHz, VCC = 1.7V to 5.5V Symbol Test Condition CI/O CIN Note: 1. Table 6-2. Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = 1.7V to 5.5V (unless otherwise noted) Symbol Parameter Test Condition VCC Supply Voltage ICC1 Supply Current VCC = 5.0V Read at 400kHz ICC2 Supply Current VCC = 5.0V Write at 400kHz ISB1 Standby Current VCC = 1.7V ISB2 Min Typ Max Units 5.5 V 0.4 1.0 mA 2.0 3.0 mA VIN = VCC or VSS 1.0 μA Standby Current VCC = 5.5V VIN = VCC or VSS 6.0 μA ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 μA ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 μA VIL Input Low Level(1) –0.6 VCC x 0.3 V VCC x 0.7 VCC + 0.5 V 1.7 (1) VIH Input High Level VOL1 Output Low Level VCC = 1.7V IOL = 0.15mA 0.2 V VOL2 Output Low Level VCC = 3.0V IOL = 2.1mA 0.4 V Note: 1. VIL min and VIH max are reference only and are not tested. Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 5 Table 6-3. AC Characteristics Applicable over recommended operating range from TAI = –40C to +85C, VCC = 1.7V to 5.5V, CL = 1TTL Gate and 100pF (unless otherwise noted) 1.7V Min 2.5V, 5.0V Symbol Parameter Max Min fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low 1.2 0.4 μs tHIGH Clock Pulse Width High 0.6 0.4 μs tI Noise Suppression Time tAA Clock Low to Data Out Valid 0.1 tBUF Time the bus must be free before a new transmission can start 1.3 0.5 μs tHD.STA Start Hold Time 0.6 0.25 μs tSU.STA Start Setup Time 0.6 0.25 μs tHD.DAT Data In Hold Time 0 0 μs tSU.DAT Data In Setup Time 100 100 ns 400 100 (1) 0.9 0.05 Max Units 1000 kHz 50 ns 0.55 μs tR Inputs Rise Time tF Inputs Fall Time(1) tSU.STO Stop Setup Time 0.6 0.25 μs tDH Data Out Hold Time 50 50 ns tWR Write Cycle Time 5 Endurance(1) 3.3V, +25C, Page Mode 1,000,000 Note: 1. 0.3 0.3 μs 300 100 ns 5 ms Write Cycles This parameter is ensured by characterization only. Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 6 7. Device Operation Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 7-4 on page 9). Data changes during SCL high periods will indicate a Start or Stop condition as defined below. Start Condition: A high-to-low transition of SDA with SCL high is a Start condition which must precede any other command (see Figure 7-5 on page 9). Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a read sequence, the Stop command will place the EEPROM in a standby power mode (see Figure 7-5 on page 9). Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. Standby Mode: The AT24CS01/02 features a low-power standby mode which is enabled upon power-up as well as after the receipt of the Stop bit and the completion of any internal operations. 2-wire Software Reset: After an interruption in protocol, power loss, or system reset, any 2-wire part can be reset by following these steps: 1. Create a start bit condition. 2. Clock nine cycles. 3. Create another start bit followed by stop bit condition as shown in Figure 7-1. The device is ready for next communication after above steps have been completed. Figure 7-1. Software reset Dummy Clock Cycles SCL 1 Start Bit 2 3 8 9 Start Bit Stop Bit SDA Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 7 Figure 7-2. Bus Timing SCL: Serial Clock, SDA: Serial Data I/O tHIGH tF tR tLOW SCL tSU.STA tLOW tHD.STA tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT Figure 7-3. Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O SCL th SDA 8 Bit ACK WORDN tWR Stop Condition Note: 1. (1) Start Condition The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of the internal clear/write cycle. Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 8 Figure 7-4. Data Validity SDA SCL Data Stable Data Stable Data Change Figure 7-5. Start and Stop Definition SDA SCL Start Stop Figure 7-6. Output Acknowledge 1 SCL 8 9 DATA IN DATA OUT Start Acknowledge Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 9 8. Device Addressing Standard EEPROM Access: The 1K and 2K EEPROM device requires an 8-bit device address word following a Start condition to enable the chip for a read or write operation. The device address word consists of a mandatory ‘1010’ (Ah) sequence for the first four most significant bits as shown in Figure 10-1 on page 12. This is common to all Serial EEPROM devices. The next three bits are the A2, A1, and A0 device address bits for the 1K and 2K EEPROM. These three bits must compare to their corresponding hard-wired input pins A2, A1, and A0 in order for the part to acknowledge. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a valid compare of the device address with hard-wired input pins A2, A1, and A0, the EEPROM will output a zero. If a compare is not successfully made, the chip will return to a standby state. Serial Number Access: The AT24CS01 and AT24CS02 utilizes a separate memory block containing a factory programmed 128-bit serial number. Access to this memory location is obtained by beginning the device address word with a ‘1011’ (Bh) sequence. The behavior of the next three bits (A2, A1, and A0) remain the same as during a standard EEPROM addressing sequence. These three bits must compare to their corresponding hard-wired input pins A2, A1, and A0 in order for the part to acknowledge. The eighth bit of the device address needs be set to a one to read the Serial Number. A zero in this bit position, other than during a dummy write sequence to set the address pointer, will result in a unknown data read from the part. Writing or altering the 128-bit serial number is not possible. Further specific protocol is needed to read the serial number from of the device. See Read Operations on page 11 for more details on accessing the special feature. 9. Write Operations Byte Write: A Byte Write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a Stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the Write is complete (see Figure 10-2 on page 12). Page Write: The 1K and 2K EEPROM are capable of an 8-byte Page Write. A Page Write is initiated in the same way as a Byte Write, but the microcontroller does not send a Stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the Page Write sequence with a Stop condition (see Figure 10-3 on page 12). The data word address lower three bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the internally generated word address reaches the page boundary, the subsequent byte loaded will be placed at the beginning of the same page. If more than eight data words are transmitted to the EEPROM, the data word address will roll-over and previously loaded data will be overwritten. Acknowledge Polling: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The Read/Write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the next read or write sequence to begin. Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 10 10. Read Operations Read operations are initiated in the same way as Write operations with the exception that the Read/Write select bit in the device address word is set to one. There are four read operations: Current Address Read Random Address Read Sequential Read Serial Number Read Current Address Read: The internal data word address counter maintains the last address accessed during the last Read or Write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll-over during read is from the last byte of the last memory page to the first byte of the first page. The address roll-over during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an zero but does generate a following Stop condition (see Figure 10-4 on page 12). Random Read: A Random Read requires a dummy byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another Start condition. The microcontroller now initiates a Current Address Read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following Stop condition (see Figure 10-5 on page 13). Sequential Read: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll-over and the Sequential Read will continue. The Sequential Read operation is terminated when the microcontroller does not respond with a zero but does generate a following Stop condition (see Figure 10-6 on page 13). Serial Number Read: Reading the serial number is similar to the sequential read sequence but requires use of the device address seen in Figure 10-1 on page 12, a dummy write, and the use of specific word address. Note: The entire 128-bit value must be read from the starting address of the serial number block to guarantee a unique number. Since the address pointer of the device is shared between the EEPROM array and the serial number block, a dummy Write Sequence should be performed to ensure the address pointer is set to zero. Random reads of the serial number block are supported but if the previous operation was to the EEPROM array, the address pointer will retain the last access location, incremented by one. Reading the serial number from a location other than the initial address of the block will not result in a unique serial number. Additionally, the word address must begin with a ‘10’ sequence regardless of the intended address. If a word address other than ‘10’ is used, then the device will output undefined data. Example: If the application desires to read the first byte of the serial number, the word address input would need to be 80h. When the end of the 128-bit serial number is reached (16 bytes of data), the data word address will roll-over back to the beginning of the 128-bit serial number. The Serial Number Read operation is terminated when the microcontroller does not respond with an zero (ACK) and instead issues a Stop condition (see Figure 10-7 on page 13). Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 11 Figure 10-1. Device Address Density Access Area 1K 2K Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EEPROM 1 0 1 0 A2 A1 A0 R/W Serial Number 1 0 1 1 A2 A1 A0 1 EEPROM 1 0 1 0 A2 A1 A0 R/W Serial Number 1 0 1 1 A2 A1 A0 1 MSB LSB Figure 10-2. Byte Write S T A R T Device Address W R I T E Word Address S T O P Data SDA LINE A C K R A / C WK M S B A C K Figure 10-3. Page Write S T A R T W R I T Device Address E Word Address (n) Data (n) Data (n + 1) S T O P Data (n + x) SDA LINE M S B R A / C WK A C K A C K A C K A C K Figure 10-4. Current Address Read S T A R T Device Address R E A D S T O P Data SDA LINE M S B R A / C WK N O A C K Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 12 Figure 10-5. Random Read S T A R T W R I T Device Address E S T A R T Device Address Word Address (n) R E A D S T O P Data (n) SDA LINE M S B R A / C WK A C K A C K N O A C K Dummy Write Figure 10-6. Sequential Read R E A D Device Address Data (n) Data (n + 1) Data (n + 2) S T O P Data (n + x) SDA LINE R A / C WK A C K A C K N O A C K A C K Figure 10-7. Serial Number Read S T A R T SDA LINE Device Address W R I T E 1 0 1 1 M S B S T A R T Word Address n 1 0 0 0 0 0 0 0 R A / C W K Device Address R E A D 1 0 1 1 A C K A C K Serial Number Data Byte 0x0 A C K Dummy Write S T O P Serial Number Data Byte 0x1 Serial Number Data Byte 0x2 Serial Number Data Byte 0x3 Serial Number Data Byte 0xF N O A C K Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 13 11. Part Markings AT24CS01 and AT24CS02: Package Marking Information 8-lead SOIC 8-lead TSSOP ATHYWW ## M @ AAAAAAA ATMLHYWW ## M @ AAAAAAAA 5-lead SOT-23 8-lead UDFN 2.0 x 3.0 mm Body ## MU ## HM@ YXX Note 1: YMXX Top Mark Bottom Mark designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT24CS01 Truncation Code ##: N1 AT24CS02 Truncation Code ##: N2 Date Codes Y = Year 2: 2012 3: 2013 4: 2014 5: 2015 Voltages 6: 2016 7: 2017 8: 2018 9: 2019 M = Month A: January B: February ... L: December WW = Work Week of Assembly 02: Week 2 04: Week 4 ... 52: Week 52 Country of Assembly Lot Number @ = Country of Assembly AAA...A = Atmel Wafer Lot Number M: 1.7V min Grade/Lead Finish Material Trace Code H: Industrial/NiPdAu U: Industrial/Matte Tin Atmel Truncation XX = Trace Code (Atmel Lot Numbers Correspond to Code) Example: AA, AB.... YZ, ZZ AT: Atmel ATM: Atmel ATML: Atmel 4/3/12 TITLE Package Mark Contact: [email protected] 24CS01-02SM, AT24CS01, and AT24CS02 Package Marking Information DRAWING NO. REV. 24CS01-02SM A Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 14 12. Ordering Code Detail AT2 4 C S 0 1 - S S H M - T Atmel Designator Shipping Carrier Option T Product Family 24CS = Serial EEPROM, plus 128-bit serial number feature = Tape and reel Operating Voltage M = 1.7V to 5.5V Package Device Grade or Wafer/Die Thickness Device Density 01 = 1K 02 = 2K H = Green, NiPdAu lead finish, Industrial temperature range (-40˚C to +85˚C) U = Green, matte Sn lead finish, Industrial temperature range (-40˚C to +85˚C) 11 = 11mil wafer thickness Package Option SS = JEDEC SOIC X = TSSOP MA = UDFN ST = SOT23 WWU = Wafer unsawn Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 15 13. Ordering Information 13.1 Atmel AT24CS01 Ordering Information Additional package types that are not listed may be available. Please contact Atmel for more details. Atmel Ordering Code Package AT24CS01-SSHM-T(1) (NiPdAu lead finish) 8S1 AT24CS01-XHM-T(1) 8X (NiPdAu lead finish) AT24CS01-MAHM-T(1) (NiPdAu lead finish) 8MA2 AT24CS01-STUM-T(1) 5TS1 AT24CS01-WWU11M(2) Notes: 1. 2. Wafer Sale Voltage Operation Range 1.7V to 5.5V Lead-free/Halogen-free/ Industrial Temperature (–40C to 85C) 1.7V to 5.5V Industrial Temperature (–40C to 85C) T = Tape and reel SOIC = 4K units per reel TSSOP, UDFN, and SOT23 = 5K units per reel For Wafer sales, please contact Atmel Sales. Package Type 8S1 8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8X 8-lead, 4.4mm body, Plastic Thin Shrink Small Outline (TSSOP) 8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Dual No Lead (UDFN) 5TS1 5-lead, 2.90mm x 1.60mm body, Plastic Thin Shrink Small Outline (SOT23) Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 16 13.2 Atmel AT24CS02 Ordering Information Additional package types that are not listed may be available. Please contact Atmel for more details. Atmel Ordering Code Package AT24CS02-SSHM-T(1) (NiPdAu lead finish) 8S1 AT24CS02-XHM-T(1) 8X (NiPdAu lead finish) AT24CS02-MAHM-T(1) (NiPdAu lead finish) 8MA2 AT24CS02-STUM-T(1) 5TS1 AT24CS02-WWU11M(2) Notes: 1. 2. Wafer Sale Voltage Operation Range 1.7V to 5.5V Lead-free/Halogen-free/ Industrial Temperature (–40C to 85C) 1.7V to 5.5V Industrial Temperature (–40C to 85C) T = Tape and reel SOIC = 4K units per reel TSSOP, UDFN, and SOT23 = 5K units per reel For Wafer sales, please contact Atmel Sales. Package Type 8S1 8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8X 8-lead, 4.4mm body, Plastic Thin Shrink Small Outline (TSSOP) 8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Dual No Lead (UDFN) 5TS1 5-lead, 2.90mm x 1.60mm body, Plastic Thin Shrink Small Outline (SOT23) Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 17 14. Packaging Information 14.1 8S1 — 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL MIN A 1.35 A1 D SIDE VIEW MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. NOM NOTE 1.27 BSC L 0.40 – 1.27 Ø 0° – 8° 6/22/11 Package Drawing Contact: [email protected] TITLE 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) GPC SWB DRAWING NO. REV. 8S1 G Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 18 14.2 8X — 8-lead TSSOP C 1 Pin 1 indicator this corner E1 E L1 H N L Top View End View A b A1 e COMMON DIMENSIONS (Unit of Measure = mm) A2 Side View Notes: MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.80 1.00 1.05 D 2.90 3.00 3.10 2, 5 SYMBOL D 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. E NOTE 6.40 BSC E1 4.30 4.40 4.50 3, 5 b 0.19 – 0.30 4 e L 0.65 BSC 0.45 L1 C 0.60 0.75 1.00 REF 0.09 - 0.20 12/8/11 TITLE Package Drawing Contact: [email protected] GPC 8X, 8-lead 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) TNR DRAWING NO. 8X Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 REV. E 19 14.3 8MA2 — 8-pad UDFN E 8 1 Pin 1 ID 2 7 3 6 4 5 D C A2 A A1 E2 COMMON DIMENSIONS (Unit of Measure = mm) b (8x) SYMBOL 8 1 7 2 Pin#1 ID D2 6 3 5 4 e (6x) 2.00 BSC E 3.00 BSC D2 1.40 1.50 1.60 E2 1.20 1.30 1.40 A 0.50 0.55 0.60 A1 0.0 0.02 0.05 A2 – – 0.55 L Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. The terminal #1 ID is a laser-marked feature. 3. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 0.35 0.40 0.50 BSC b 0.18 0.25 0.30 K 0.20 – – 3 7/15/11 GPC 8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) NOTE 0.152 REF 0.30 e TITLE Package Drawing Contact: [email protected] MAX NOM D C K L (8x) MIN YNZ DRAWING NO. 8MA2 Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 REV. B 20 14.4 5TS1 — 5-lead SOT23 e1 C 4 5 E1 C L E L1 1 3 2 END VIEW TOP VIEW b A2 SEATING PLANE e A A1 D SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.15 mm per side. 2. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15 mm from the lead tip. 4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm total in excess of the "b" dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. This drawing is for general information only. Refer to JEDEC Drawing MO-193, Variation AB for additional information. SYMBOL MIN A A1 A2 c D E E1 L1 e e1 b 0.00 0.70 0.08 MAX NOM 0.90 2.90 BSC 2.80 BSC 1.60 BSC 0.60 REF 0.95 BSC 1.90 BSC 0.30 - 1.00 0.10 1.00 0.20 0.50 NOTE 3 1,2 1,2 1,2 3,4 5/31/12 Package Drawing Contact: [email protected] TITLE GPC 5TS1, 5-lead 1.60mm Body, Plastic Thin Shrink Small Outline Package (Shrink SOT) TSZ DRAWING NO. 5TS1 Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 REV. D 21 15. Revision History Doc. Rev. Date 8815A 06/2012 Comments Initial document release. Atmel AT24CS01/02 [PRELIMINARY DATASHEET] 8815A–SEEPR–6/12 22 Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.com Tel: (+852) 2245-6100 Fax: (+49) 89-3194621 Fax: (+81) (3) 6417-0370 Fax: (+852) 2722-1369 © 2012 Atmel Corporation. All rights reserved. / Rev.: 8815A–SEEPR–6/12 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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