Features • • • • • • • • • • • Organized as 2M x 8 bits Single 3.3V Power Supply Stacks of 16 SRAM 128K x 865609E Die Access Time: 40 ns Very Low Power Consumption – Active: 100 mW (Typ) – Standby: 1 mW (Typ) TTL-Compatible Inputs and Outputs Die Designed on 0.35 Micron Process No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm 2 Tested up to a Total Dose of 200 krads (Si) according to MIL STD 883 Method 1019 Wide Temperature Range 55°C to +125°C Built and Tested by 3D+, using 3D+ Die Stacking Technology Description The AT61162E is a Rad Tolerant module, highly-integrated and very low-power CMOS static RAM organized as 2M x 8 bits. It is organized with 16 banks of 1 Mbit. Each bank has a 8-bit interface and is selected with 16 specific CS: 0 - 15. Banks are selectable by pairs with 8 specific BS: 0 - 7. This module takes full benefit of the 3D+ cube technology, and it is assembled and tested by 3D+, using Atmel 65609E 1-Mbit SRAM die: it is built with 8 layers, each one housing 2 dies. 10 nF decoupling capacitors are embedded for each memory die. Rad Hard 2-Mbit x 8 SRAM Cube AT61162E Preliminary This module brings the solution to applications where fast computing is as mandatory as low power consumption, for example: space electronics, portable instruments, or embarked systems. AT61162E is processed according to the methods of the latest revision of the MIL PRF 38535, QML N (QML Q counterpart for plastic). The package is a 64 gull wing pins dual in line, 11 mm wide, 28 mm long and 14.3 mm height and 0.8 mm pin pitch. Rev. 4157D–AERO–06/04 1 AT61162E Block Diagram CS0.0 CS0.1 I/O (0:7) A (0:16) WE OE Chip 1 CS1 CS2 BS7 CS7.0 CS7.1 Bank 1 Bank 0 I/O (0:7) A (0:16) WE OE BS1 BS0 CS1.0 CS1.1 Bank 7 I/O (0:7) A (0:16) WE OE Chip 1 CS1 CS2 Chip 1 CS1 CS2 I/O (0:7) A (0:16) WE OE I/O (0:7) A (0:16) WE OE CS1 CS2 I/O (0:7) A (0:16) WE OE Chip 0 I/O (0:7) A (0:16) WE OE CS1 CS2 Chip 0 CS1 CS2 Chip 0 Pin Configuration CS 7.0 CS 6.0 CS 5.0 CS 4.0 CS 3.0 CS 2.0 CS 1.0 CS 0.0 CS 0.1 CS 1.1 CS 2.1 CS 3.1 CS 4.1 CS 5.1 CS 6.1 CS 7.1 BS BS BS BS BS BS BS BS 7 6 5 4 3 2 1 0 2 4157D–AERO–06/04 Pin Description Pin Name Function AO - A16 Address Inputs WE Write Enable OE Output Enable CS 0.0 - CS 7.1 Chip Select 1 BS0 - BS7 Chip Select 2 I/O0 - I/O7 Data Inputs/Outputs VCC 3.3V Power GND Ground NC No Connection Truth Table CSx.x BSx WE OE Inputs/ Outputs All CS H – – – Z Deselect/ Power-down – All BS L – – Z Deselect/ Power-down H L Data out Read (Bank y.z selected) L – Data in Write (Bank y.z selected) H H Z Output Disable CS y.z: L BSy: H Other CS: H Other BS: – CS y.z: L CS y.z: H Other CS: – Other BS: L CS y.z: L BSy: H Other CS: H Other BS: – CS y.z: L CS y.z: H Other CS: – BSy: H Other BS: L CS y.z: L BSy: H Other CS: H Other BS: – CS y.z: L CS y.z: H Other CS: – 3 BSy: H Mode BSy: H Other BS: L AT61162E 4157D–AERO–06/04 AT61162E Electrical Characteristics Absolute Maximum Ratings* Supply Voltage to GND Potential ............................ 0.5 to +5V *Note: Stresses beyond those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Input Voltage GND ........................... GND -0.3 to VCC0.3V DC Output Voltage high-Z-State GND ... GND -0.3 to VCC+0.3V Storage Temperature ......................................... -65 to +150°C Output Current into Outputs (Low)................................. 20 mA Electro Statics Discharge Voltage (MIL STD 883D method 3015.3).................................. >1500V Operating Range Operating Temperature Operating Voltage -55°C to 125°C 3.3V ± 0.3V Military Recommended DC Operating Conditions Parameter Description Min Typ Max Units VCC Supply Voltage 3 3.3 3.6 V Gnd Ground 0 0 0 V V IH Input High Voltage 2.2 - VCC+0.3 V V IL Input Low Voltage GND-0.3 0.0 0.8 V Capacitance Parameter Description C IN(1) C OUT (1) Note: Min Typ Max Unit Input Low Voltage - - 8 pF Output High Voltage - - 8 pF 1. Guaranteed but not tested. 4 4157D–AERO–06/04 DC Parameters Parameter Min Typ Max Unit Input Leakage Current -16 - 16 µA IOZ (1) Output Leakage Current -16 - 16 µA V OL (2) Output Low Voltage - - 0.4 V V OH (3) Output High Voltage 2.4 - - V IIX (1) Description 1. Gnd < V IN < VCC, Gnd < VOUT < VCC Output Disabled. 2. VCC min. IOL = 1 mA. 3. VCC min. IOH = -0.5 mA. Consumption Symbol ICCSB ICCSB1 ICCOP Description (1) (2) (3) 61162E-35 Unit Value Standby Supply Current 40 mA max Standby Supply Current 32 mA max Dynamic Operating Current 90 mA max 1. CS0.0 - CS7.1 > VIH or BS0 - BS7 < V IL and CS0.0 - CS7.1 < VIL. 2. CS0.0 > VCC - 0.3V or, BS0 - BS7 < Gnd + 0.3V and CS0.0 - CS7.1 < 0.2V 3. One bank active (F = 1/TAVAV, IOUT = 0 mA, W = OE = VIH, VIN = Gnd/VCC, VCC max.), other banks stand by TTL (note 1) or CMOS (note 2). 5 AT61162E 4157D–AERO–06/04 AT61162E Write Cycle Symbol Parameter 61162E-40 Unit Value tAVAW Write cycle time 40 ns min tAVWL Address set-up time 0 ns min tAVWH Address valid to end of write 35 ns min tDVWH Data set-up time 35 ns min tE1LWH CS1 low to write end 35 ns min tE2HWH CS2 high to write end 35 ns min tWLQZ Write low to high-Z (1) 20 ns max tWLWH Write pulse width 35 ns min tWHAX Address hold from to end of write +3 ns min tWHDX Data hold time 0 ns min tWHQX Write high to low-Z (1) 0 ns min Note: 1. Parameters guaranteed, not tested, with output loading 5 pF (see 1b in Figure: AC Test Loads Waveforms). Read Cycle Symbol Parameter 61162E-40 Unit Value tAVAV Read cycle time 40 ns min tAVQV Address access time 40 ns max tAVQX Address valid to low-Z 3 ns min tE1LQV Chip-select1 access time 40 ns max tE1LQX CS1 low to low-Z (1) 3 ns min tE1HQZ CS1 high to high-Z (1) 20 ns max tE2HQV Chip-select2 access time 40 ns max tE2HQX CS2 high to low-Z (1) 3 ns min tE2LQZ CS2 low to high-Z (1) 20 ns max tGLQV Output Enable access time 15 ns max tGLQX OE low to low-Z (1) 0 ns min tGHQZ OE high to high-Z (1) 10 ns max Note: 1. Parameters guaranteed, not tested, with output loading 5 pF (see 1b in page Figure: AC Test Loads Waveforms). 6 4157D–AERO–06/04 AC Parameters AC Test Conditions Input Pulse Levels: ....................................................... GND to 3.0V Input Rise/Fall Times: .................................................. 5 ns Input Timing Reference Levels: ................................... 1.5V Output Loading IOL/IOH (see figures 1a and 1b)............ +30 pF AC Test Loads Waveforms R1 2552 R1 2552 3.3V 3.3V 2824 2824 Figure 1a Figure 1b Figure 2 1340 7 AT61162E 4157D–AERO–06/04 AT61162E Data Retention Mode Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. During data retention CS must be held high within VCC to VCC -0.2V or, chip select BS must be held down within GND to GND +0.2V. 2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 3. During power up and power down transitions CS and OE must be kept between VCC + 0.3V and 70% of VCC, or with BS between GND and GND -0.3V. 4. The RAM can begin operation > TR ns after VCC reaches the minimum operation voltages (3V). Timing 3V 3V BS Data Retention Characteristics Parameter Description Min Typical TA = 25°C Max Unit VCCDR VCC for data retention 2.0 – – V tCDR Chip deselect to data retention time 0.0 – – ns tR Operation recovery time tAVAV(1) – – ns ICCDR1 (2) Data retention current at 2.0V – 0.160 16 mA Notes: 1. TAVAV = Read Cycle Time 2. All CS = VCC or All BS = CS = GND, V IN = Gnd/V CC. 8 4157D–AERO–06/04 Figure 1. Write Cycle 1. W Controlled, OE High During Write Figure 2. Write Cycle 2. W Controlled, OE Low 9 AT61162E 4157D–AERO–06/04 AT61162E Figure 3. Write Cycle 3. CS1 or CS2 Controlled Note: The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and WE LOW. Both signals must be activated to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be referenced to the activated edge of the signal that terminates the write. Data out is high impedance if OE = VIH. Figure 4. Read Cycle nb 1 Figure 5. Read Cycle nb 2 10 4157D–AERO–06/04 Figure 6. Read Cycle nb 3 D 11 AT61162E 4157D–AERO–06/04 AT61162E Test Tools Supplier Reference Number ENPLAS OTS - 64 - 0.8 - 04 Ordering Information Reference Number Temperature Range Speed Package Quality Flow AT61162E-PM40MMN -55 to +125°C 40 ns Cube 64 pins QML N AT61162E-PM40M-E 25°C 40 ns Cube 64 pins Engineering Samples 12 4157D–AERO–06/04 Package Drawing 13 Dimensions (mm) Min Max A 14.0 14.60 D 13.60 13.80 D1 10.75 11.15 E 27.80 28.20 F 7.5 e 0.80 e1 0.35 AT61162E 4157D–AERO–06/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2003. All rights reserved. Atmel ® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4157D–AERO–06/04 /xM