ATMEL AT52BR1672

Features
• 16-Mbit Flash and 2-Mbit/4-Mbit SRAM
• Single 66-ball 8 mm x 10 mm x 1.2 mm CBGA Package
• 2.7V to 3.3V Operating Voltage
Flash
• 2.7V to 3.3V Read/Write
• Access Time – 85 ns
• Sector Erase Architecture
•
•
•
•
•
•
•
•
•
•
•
– Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
Fast Word Program Time – 20 µs
Fast Sector Erase Time – 300 ms
Dual-plane Organization, Permitting Concurrent Read While Program/Erase
– Memory Plane A: Eight 4K Word and Seven 32K Word Sectors
– Memory Plane B: Twenty-four 32K Word Sectors
Erase Suspend Capability
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 10 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
Top/Bottom Block Configuration
128-bit Protection Register
SRAM
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16-megabit
Flash and
2-megabit/
4-megabit
SRAM Stack
Memory
AT52BR1672(T)
AT52BR1674(T)
Preliminary
2-megabit (128K x 16)/4-megabit (256K x 16)
2.7V to 3.3V V CC Operating Voltage
70 ns Access Time
Fully Static Operation and Tri-state Output
1.2V (Min) Data Retention
Industrial Temperature Range
Device Number
Flash Plane
Architecture
Flash
Configuration
SRAM
Configuration
AT52BR1672(T)
12M + 4M
16M (1M x 16)
2M (128K x 16)
AT52BR1674(T)
12M + 4M
16M (1M x 16)
4M (256K x 16)
Rev. 2604B–STKD–09/02
1
CBGA Top View
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
NC
A11
A15
A14
A13
A12
GND
NC
NC
NC
A16
A8
A10
A9
I/O15
SWE
I/O14
I/O7
WE
RDY BUSY
I/O13
I/O6
I/O4
I/O5
SGND
RESET
I/O12
SCS2
SVcc
Vcc
NC
Vpp
A19
I/O10
I/O2
I/O3
SLB
SUB
SOE
I/O9
I/O8
I/O0
I/O1
A18
A17
A7
A6
A3
A2
A1
SCS1
NC
A5
A4
A0
CE
GND
OE
NC
NC
NC
A
B
C
D
E
I/O11
F
G
H
NC
Pin
Configurations
2
NC
Pin Name
Function
A0 - A16
Flash/SRAM Common Address Input for 2M SRAM
A0 - A17
Flash/SRAM Common Address Input for 4M SRAM
A18 - A19
Flash Address Input
CE
Flash Chip Enable
OE/SOE
Flash/SRAM, Output Enable
WE/SWE
Flash/SRAM, Write Enable
VCC
Flash Power Supply
VPP
Optional Flash Power Supply for Faster Program/Erase Operations
I/O0-I/O15
Data Inputs/Outputs
SCS1, SCS2
SRAM Chip Select
RDY/BUSY
Flash Ready/Busy Output
SVCC
SRAM Power Supply
GND/SGND
Flash/SRAM GND
SUB
SRAM Upper Byte
SLB
SRAM Lower Byte
NC
No Connect
RESET
Flash Reset
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
Description
The AT52BR1672(T) combines a 16-megabit Flash (1M x 16) and a 2-megabit SRAM (organized as 128K x 16) in a stacked CBGA package; while the AT52BR1674(T) combines a 16megabit Flash (1M x 16) and a 4-megabit SRAM (organized as 256K x 16) in a stacked CBGA
package. Both devices operate at 2.7V to 3.3V in the industrial temperature range. The modules use a 16-megabit Flash with dual plane architecture for concurrent read/write operations.
The Flash is organized as 12M + 4M for planes B and A, respectively.
Block Diagram
ADDRESS
OE WE
SOE SWE
RESET
CE
FLASH
SRAM
SCS1
RDY/BUSY
DATA
Absolute Maximum Ratings
Temperature under Bias .................................. -40°C to +85°C
Storage Temperature ..................................... -55°C to +150°C
All Input Voltages
except VPP and RESET
(including NC Pins)
with Respect to Ground .....................................-0.2V to +3.3V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Voltage on VPP
with Respect to Ground ..................................-0.2V to + 6.25V
Voltage on RESET
with Respect to Ground ...................................-0.2V to +13.5V
All Output Voltages
with Respect to Ground .....................................-0.2V to +0.2V
DC and AC Operating Range
AT52BR1672(T)/1674(T)
Operating Temperature (Case)
VCC Power Supply
Industrial
-40°C - 85°C
2.7V to 3.3V
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2604B–STKD–09/02
16-megabit
Flash
Description
The 16-megabit Flash memory organized as 1,048,576 words of 16 bits each. The x16 data
appears on I/O0 - I/O15. The memory is divided into 39 sectors for erase operations.The
device has CE and OE control signals to avoid any bus contention. This device can be read or
reprogrammed using a single 2.7V power supply, making it ideally suited for in-system
programming.
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector (see Sector Lockdown section).
The device is segmented into two memory planes. Reads from memory plane B may be performed even while program or erase functions are being executed in memory plane A and vice
versa. This operation allows improved system performance by not requiring the system to wait
for a program or erase operation to complete before a read is performed. To further increase
the flexibility of the device, it contains an Erase Suspend feature. This feature will put the
erase on hold for any amount of time and let the user read data from or program data to any of
the remaining sectors within the same memory plane. There is no reason to suspend the
erase operation if the data to be read is in the other memory plane. The end of a program or
an erase cycle is detected by the Ready/Busy pin, Data Polling or by the toggle bit.
The VPP pin provides faster program/erase times. With VPP at 5.0V or 12.0V, the program and
erase operations are accelerated.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement
of entering the three-byte program sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the write control lines are required for
writing into the device. This mode (Single Pulse Word Program) is exited by powering down
the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back
to V CC. Erase and Erase Suspend/Resume commands will not work while in this mode; if
entered they will result in data being programmed into the device. It is not recommended that
the six-byte code reside in the software of the final product but only exist in external programming code.
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AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
16-megabit Flash Memory Block Diagram
I/O0 - I/O15
INPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
REGISTER
A0 - A19
OUTPUT
MULTIPLEXER
OUTPUT
BUFFER
CE
COMMAND
REGISTER
WE
OE
ADDRESS
LATCH
RESET
DATA
COMPARATOR
Y-DECODER
Y-GATING
RDY/BUSY
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
GND
X-DECODER
PLANE B
SECTORS
PLANE A SECTORS
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2604B–STKD–09/02
Device
Operation
READ: The 16-megabit Flash is accessed like an EPROM. When CE and OE are low and WE
is high, the data stored at the memory location determined by the address pins are asserted
on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for
the command codes). The command sequences are written by applying a low pulse on the
WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Standard microprocessor write timings are used. The address locations used in the
command sequences are not affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read or
standby mode, depending upon the state of the control inputs.
ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command.
CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is tEC.
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while
the 30H data input command is latched on the rising edge of WE. The sector erase starts after
the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will
automatically time to completion. The maximum time to erase a section is tSEC. When the sector programming lockdown feature is not enabled, the sector will erase (from the same Sector
Erase command). An attempt to erase a sector that has been protected will result in the operation terminating in 2 µs.
WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical “0”)
on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required
internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle
time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a
program cycle.
VPP PIN: The circuitry of the 16-megabit Flash is designed so that the device can be programmed or erased from the VCC power supply or from the VPP input pin. When VPP is less
than or equal to the VCC pin, the device selects the V CC supply for programming and erase
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AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
operations. When the VPP pin is greater than the V CC supply, the device will select the V PP
input as the power supply for programming and erase operations. The device will allow for
some variations between the VPP input and the VCC power supply in its selection of VCC or VPP
for program or erase operations. If the VPP pin is within 0.3V of VCC for 2.7V < VCC < 3.3V,
then the program or erase operations will use VCC and disregard the VPP input signal. When
the VPP signal is used to accelerate program and erase operations, the VPP must be in the 5V
± 0.5V or 12V ± 0.5V range to ensure proper operation. The Vpp pin can be left unconnected.
SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled.
These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is
updated. This feature does not have to be activated; any sector’s usage as a write protected
region is optional to the user.
At power-up or reset all sectors are unlocked. To activate the lockdown for a specific sector,
the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked
down, the contents of the sector is read-only and cannot be erased or programmed.
SECTOR LOCKDOWN DETECTION: A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification
mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on
I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown
feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation.
SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is
through reset or power-up cycles. After power-up or reset, the content of a sector that is
locked down can be erased and reprogrammed.
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to
interrupt a sector erase operation and then program or read data from a different sector within
the same plane. Since this device has a dual-plane architecture, there is no need to use the
Erase Suspend feature while erasing a sector when you want to read data from a sector in the
other plane. After the Erase Suspend command is given, the device requires a maximum time
of 15 µs to suspend the erase operation. After the erase operation has been suspended, the
plane that contains the suspended sector enters the erase-suspend-read mode. The system
can then read data or program data to any other sector within the device. An address is not
required during the Erase Suspend command. During a sector erase suspend, another sector
cannot be erased. To resume the sector erase operation, the system must write the Erase
Resume command. The Erase Resume command is a one-bus cycle command, which does
require the plane address (determined by A18 and A19). The device also supports an erase
suspend during a complete chip erase. While the chip erase is suspended, the user can read
from any sector within the memory that is protected. The command sequence for a chip erase
suspend and a sector erase suspend are the same.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see “Operating Modes” on page 13 (for hardware operation) or “Software Product
Identification Entry/Exit” on page 21. The manufacturer and device codes are the same for
both modes.
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2604B–STKD–09/02
128-BIT PROTECTION REGISTER: The 16-megabit Flash contains a 128-bit register that
can be used for security purposes in system design. The protection register is divided into two
64-bit blocks. The two blocks are designated as block A and block B. The data in block A is
non-changeable and is programmed at the factory with a unique number. The data in block B
is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program
Protection Register command must be used as shown in the Command Definition table on
page 9. To lock out block B, the four-bus cycle Lock Protection Register command must be
used as shown in the Command Definition table. Data bit D1 must be zero during the fourth
bus cycle. All other data bits during the fourth bus cycle are don’t cares. Please see the “Protection Register Addressing Table” on page 10 for the address locations in the protection
register. To read the protection register, the Product ID Entry command is given followed by a
normal read operation from an address within the protection register. After reading the protection register, the Product ID Exit command must be given prior to performing any other
operation.
DATA POLLING: The Flash features Data Polling to indicate the end of a program cycle. During a program cycle an attempted read of the last word loaded will result in the complement of
the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all
outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to
read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true
data will be read from the device. Data Polling may begin at any time during the program
cycle. Please see “Status Bit Table” on page 22 for more details.
TOGGLE BIT: In addition to Data Polling, the 16-megabit Flash provides another method for
determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle
bit that is available on I/O6. While a sector is erase suspended, a read or a program operation
from the suspended sector will result in the I/O2 bit toggling. Please see “Status Bit Table” on
page 22 for more details.
RDY/BUSY: For the 16-megabit Flash, an open-drain Ready/Busy output pin provides
another method of detecting the end of a program or erase operation. RDY/BUSY is actively
pulled low during the internal program and erase cycles and is released at the completion of
the cycle. The open-drain connection allows for OR-tying of several devices to the same
RDY/BUSY line.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the Flash in the following ways: (a) VCC sense: if VCC is below 1.8V
(typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the
VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c)
Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d)
Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs and
control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
OUTPUT LEVELS: For the 16-megabit Flash, output high levels (VOH) are equal to V CCQ 0.2V (not VCC). For 2.7V - 3.3V output levels, VCCQ must be tied to VCC. For 1.8V - 2.2V output
levels, VCCQ must be regulated to 2.0V ± 10%, while VCC must be regulated to 2.7V - 3.0V (for
minimum power).
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AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
Command Definition in Hex(1)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
555
Sector Erase
6
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AA
AAA (2)
55
555
80
555
AA
AAA
555
AA
AAA
55
555
80
555
AA
AAA
55
555
10
55
SA(3)(4)
30
Word Program
4
555
AA
AAA
55
555
A0
Addr
DIN
Enter Single Pulse
Program Mode
6
555
AA
AAA
55
555
80
555
AA
AAA
55
555
A0
Single Pulse
Word Program
1
Addr
DIN
Sector Lockdown
6
555
AA
AAA
55
555
80
555
AA
AAA
55
SA(3)(4)
60
Erase Suspend
1
XXX
B0
Erase Resume
1
PA(5)
30
Product ID Entry
3
555
AA
AAA
55
555
90
Product ID Exit(6)
3
555
AA
AAA
55
555
F0
Product ID Exit(6)
1
XXX
F0
Program Protection
Register
4
555
AA
AAA
55
555
C0
Addr
DIN
Lock Protection
Register - Block B
4
555
AA
AAA
55
555
C0
080
X0
Status of Block B
Protection
4
555
AA
AAA
55
555
90
80
DOUT(7)
Notes:
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don’t Care.
The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are Don’t Care.
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see page 11 for
details).
4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power
cycled.
5. PA is the plane address (A19-A18).
6. Either one of the Product ID Exit commands can be used.
7. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Voltage on OE and VPP
with Respect to Ground ...................................-0.6V to +13.0V
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Protection Register Addressing Table
Word
Use
Block
A7
A6
A5
A4
A3
A2
A1
A0
0
Factory
A
1
0
0
0
0
0
0
1
1
Factory
A
1
0
0
0
0
0
1
0
2
Factory
A
1
0
0
0
0
0
1
1
3
Factory
A
1
0
0
0
0
1
0
0
4
User
B
1
0
0
0
0
1
0
1
5
User
B
1
0
0
0
0
1
1
0
6
User
B
1
0
0
0
0
1
1
1
7
User
B
1
0
0
0
1
0
0
0
Note:
10
1. All address lines not specified in the above table must be 0 when accessing the protection register, i.e., A19 - A8 = 0.
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
Top Boot 16-megabit Flash (12M + 4M) – Sector Address Table
x16
Plane
Sector
Size (Words)
Address Range (A19 - A0)
B
SA0
32K
00000 - 07FFF
B
SA1
32K
08000 - 0FFFF
B
SA2
32K
10000 - 17FFF
B
SA3
32K
18000 - 1FFFF
B
SA4
32K
20000 - 27FFF
B
SA5
32K
28000 - 2FFFF
B
SA6
32K
30000 - 37FFF
B
SA7
32K
38000 - 3FFFF
B
SA8
32K
40000 - 47FFF
B
SA9
32K
48000 - 4FFFF
B
SA10
32K
50000 - 57FFF
B
SA11
32K
58000 - 5FFFF
B
SA12
32K
60000 - 67FFF
B
SA13
32K
68000 - 6FFFF
B
SA14
32K
70000 - 77FFF
B
SA15
32K
78000 - 7FFFF
B
SA16
32K
80000 - 87FFF
B
SA17
32K
88000 - 8FFFF
B
SA18
32K
90000 - 97FFF
B
SA19
32K
98000 - 9FFFF
B
SA20
32K
A0000 - A7FFF
B
SA21
32K
A8000 - AFFFF
B
SA22
32K
B0000 - B7FFF
B
SA23
32K
B8000 - BFFFF
A
SA24
32K
C0000 - C7FFF
A
SA25
32K
C8000 - CFFFF
A
SA26
32K
D0000 - D7FFF
A
SA27
32K
D8000 - DFFFF
A
SA28
32K
E0000 - E7FFF
A
SA29
32K
E8000 - EFFFF
A
SA30
32K
F0000 - F7FFF
A
SA31
4K
F8000 - F8FFF
A
SA32
4K
F9000 - F9FFF
A
SA33
4K
FA000 - FAFFF
A
SA34
4K
FB000 - FBFFF
A
SA35
4K
FC000 - FCFFF
A
SA36
4K
FD000 - FDFFF
A
SA37
4K
FE000 - FEFFF
A
SA38
4K
FF000 - FFFFF
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2604B–STKD–09/02
Bottom Boot 16-megabit Flash (12M + 4M) – Sector Address Table
x16
Plane
12
Sector
Size (Words)
Address Range (A19 - A0)
A
SA0
4K
00000 - 00FFF
A
SA1
4K
01000 - 01FFF
A
SA2
4K
02000 - 02FFF
A
SA3
4K
03000 - 03FFF
A
SA4
4K
04000 - 04FFF
A
SA5
4K
05000 - 05FFF
A
SA6
4K
06000 - 06FFF
A
SA7
4K
07000 - 07FFF
A
SA8
32K
08000 - 0FFFF
A
SA9
32K
10000 - 17FFF
A
SA10
32K
18000 - 1FFFF
A
SA11
32K
20000 - 27FFF
A
SA12
32K
28000 - 2FFFF
A
SA13
32K
30000 - 37FFF
A
SA14
32K
38000 - 3FFFF
B
SA15
32K
40000 - 47FFF
B
SA16
32K
48000 - 4FFFF
B
SA17
32K
50000 - 57FFF
B
SA18
32K
58000 - 5FFFF
B
SA19
32K
60000 - 67FFF
B
SA20
32K
68000 - 6FFFF
B
SA21
32K
70000 - 77FFF
B
SA22
32K
78000 - 7FFFF
B
SA23
32K
80000 - 87FFF
B
SA24
32K
88000 - 8FFFF
B
SA25
32K
90000 - 97FFF
B
SA26
32K
98000 - 9FFFF
B
SA27
32K
A0000 - A7FFF
B
SA28
32K
A8000 - AFFFF
B
SA29
32K
B0000 - B7FFF
B
SA30
32K
B8000 - F7FFF
B
SA31
32K
C0000 - C7FFF
B
SA32
32K
C8000 - CFFFF
B
SA33
32K
D0000 - D7FFF
B
SA34
32K
D8000 - DFFFF
B
SA35
32K
E0000 - E7FFF
B
SA36
32K
E8000 - EFFFF
B
SA37
32K
F0000 - F7FFF
B
SA38
32K
F8000 - FFFFF
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
DC and AC Operating Range
Operating Temperature (Case)
Industrial
VCC Power Supply
AT52BR1672(T)-85
AT52BR1674(T)-85
-40°C - 85°C
-40°C - 85°C
2.7V to 3.3V
2.7V to 3.3V
Operating Modes
Mode
CE
OE
WE
RESET
VPP
Ai
I/O
Read
VIL
VIL
VIH
VIH
X
Ai
DOUT
Program/Erase(2)
VIL
VIH
VIL
VIH
VPP(6)
Ai
DIN
Standby/Program Inhibit
VIH
X(1)
X
VIH
X
X
High-Z
X
X
VIH
VIH
X
X
VIL
X
VIH
X
Output Disable
X
VIH
X
VIH
X
Reset
X
X
X
VIL
X
VIL
VIL
VIH
VIH
Program Inhibit
High-Z
X
High-Z
Product Identification
Hardware
Software(5)
Notes:
1.
2.
3.
4.
5.
6.
VIH
A1 - A19 = V IL, A9 = V H(3), A0 = V IL
Manufacturer Code(4)
A1 - A19 = VIL, A9 = V H(3), A0 = V IH
Device Code(4)
A0 = VIL, A1 - A19 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A19 = VIL
Device Code(4)
X can be VIL or VIH.
Refer to AC programming waveforms on page 18.
VH = 12.0V ± 0.5V.
Manufacturer Code: 001FH. Device Code: 00C2H (Top Boot); 00C0H (Bottom Boot).
See details under “Software Product Identification Entry/Exit” on page 21.
VPP can be left unconnected or 0V ≤ VPP ≤ 3.3V. For faster erase/program operations, VPP can be set to 5.0V ± 0.5V or
12V ± 0.5V.
13
2604B–STKD–09/02
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to V CC
10
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
1
mA
ISB3
VCC Standby Current TTL
CE = 2.0V to VCC, VCC = 2.85V
10
µA
ICC (1)(2)
VCC Active Read Current
f = 5 MHz; IOUT = 0 mA, 3.3V ≤ V CC
30
mA
ICC1
VCC Programming Current (VPP = VCC )
45
mA
µA
VPP Input Load Current
VPP = 0V, VCC = 3.0V
10
IPP1
VPP = VCC = 3.0V
10
µA
ICC2
VCC Programming Current (VPP = 5.0V ± 0.5V)
40
mA
IPP2
VPP Programming Current (VPP = 5.0V ± 0.5V)
5
mA
ICC3
VCC Programming Current (VPP = 12.0V ± 0.5V)
40
mA
IPP3
VPP Programming Current (VPP = 12.0V ± 0.5V)
6
mA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL1
Output Low Voltage
IOL = 2.1 mA
0.45
V
VOL2
Output Low Voltage
IOL = 1.0 mA
0.20
V
VOH1
Output High Voltage
VOH2
Output High Voltage
Notes:
14
Min
2.0
IOH = -400 µA
VCCQ < 2.6V
IOH = -400 µA
VCCQ ≥ 2.6V
IOH = -100 µA
VCCQ < 2.6V
IOH = -100 µA
VCCQ ≥ 2.6V
V
V CCQ - 0.2
2.4
V
V CCQ - 0.1
2.5
V
V
V
1. In the erase mode, ICC is 50 mA.
2. For 3.3V < VCC < 3.6V, ICC (max) = 35 mA.
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
AC Read Characteristics
AT52BR1672(T)-85
Symbol
Parameter
Min
Max
tACC
Address to Output Delay
tCE(1)
CE to Output Delay
tOE(2)
OE to Output Delay
0
40
tDF(3)(4)
CE or OE to Output Float
0
25
tOH
Output Hold from OE, CE or Address, whichever occurred first
0
tRO
RESET to Output Delay
AT52BR1674(T)-85
Min
Max
Units
85
85
ns
85
85
ns
0
40
ns
0
25
ns
0
100
ns
100
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
OUTPUT
Notes:
HIGH Z
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
15
2604B–STKD–09/02
Input Test Waveforms and Measurement Level
tR, tF < 5 ns
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
16
1. This parameter is characterized and is not 100% tested.
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
AC Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Setup Time
0
ns
tAH
Address Hold Time
40
ns
tCS
Chip Select Setup Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
40
ns
tDS
Data Setup Time
30
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
30
ns
AC Word Load Waveforms
WE Controlled
CE Controlled
17
2604B–STKD–09/02
Program Cycle Characteristics
Symbol
Parameter
tBP
Min
Typ
Max
Units
Word Programming Time (0V < VPP < 4.5V)
20
50
µs
tBPVPP
Word Programming Time (VPP > 4.5V)
10
25
µs
tAS
Address Setup Time
0
ns
tAH
Address Hold Time
40
ns
tDS
Data Setup Time
30
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
40
ns
tWPH
Write Pulse Width High
30
ns
tWC
Write Cycle Time
70
ns
tSR/W
Latency between Read and Write Operations
50
ns
tRP
Reset Pulse Width
tRH
Reset High Time before Read
tEC
Chip Erase Cycle Time (VPP < 4.5V)
12
seconds
tECVPP
Chip Erase Cycle Time (VPP > 4.5V)
6
seconds
tSEC
Sector Erase Cycle Time (VPP < 4.5V)
400
ms
tEPS
Erase or Program Suspend Time
15
µs
500
ns
50
ns
300
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP
tBP
tWPH
WE
t
tAS
A0 - A19
tAH
tDH
555
555
AAA
tWC
ADDRESS
SR/W
VALID
READ ADDRESS
tDS
tACC
DATA
18
AA
55
A0
INPUT DATA
OUTPUT
DATA
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
Sector or Chip Erase Cycle Waveforms
OE (1)
CE
tWP
t EC
tWPH
WE
tSR/W
tAS
A0 - A19
tAH
555
Notes:
555
AAA
tWC
DATA
tDH
555
Note 2
AAA
ADDRESS
VALID
tDS
AA
55
80
AA
55
Note 3
WORD 0
WORD 1
WORD 2
WORD 3
WORD 4
WORD 5
OUTPUT
VALID
t ACC
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
19
2604B–STKD–09/02
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
tOE
tWR
Notes:
OE to Output Delay
Min
Typ
Max
10
ns
10
ns
(2)
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 15.
Units
ns
0
ns
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
tOE
OE to Output Delay
tOEHP
OE High Pulse
tWR
Notes:
Min
Max
Units
10
ns
10
ns
(2)
Write Recovery Time
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 15.
Typ
ns
50
ns
0
ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
20
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
Software Product Identification Entry(1)
Sector Lockdown Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 80
TO
ADDRESS 555
LOAD DATA 90
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
Software Product Identification Exit(1)(6)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
OR
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA 60
TO
SECTOR ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA F0
TO
ADDRESS 555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
LOAD DATA 55
TO
ADDRESS AAA
PAUSE 200 µs(2)
Notes:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex) and A11 - A19 (Don’t
Care).
2. Sector Lockdown feature enabled.
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex) and A11 - A19 (Don’t Care).
2. A1 - A19 = VIL. Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
Additional Device Code is read for address 0003H
3. The device does not remain in identification mode if powered
down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 001FH.
Device Code: 00C2H (Top Boot); 00C0H (Bottom Boot).
Additional Device Code: 00C8H.
6. Either one of the Product ID Exit commands can be used.
21
2604B–STKD–09/02
Status Bit Table
Status Bit
I/O7
Read Address In
I/O6
I/O2
Plane A
Plane B
Plane A
Plane B
Plane A
Plane B
Programming in Plane A
I/O7
DATA
TOGGLE
DATA
1
DATA
Programming in Plane B
DATA
I/O7
DATA
TOGGLE
DATA
1
Erasing in Plane A
0
DATA
TOGGLE
DATA
TOGGLE
DATA
Erasing in Plane B
DATA
0
DATA
TOGGLE
DATA
TOGGLE
Erase Suspended & Read
Erasing Sector
1
1
1
1
TOGGLE
TOGGLE
Erase Suspended & Read
Non-erasing Sector
DATA
DATA
DATA
DATA
DATA
DATA
Erase Suspended &
Program Non-erasing Sector
in Plane A
I/O7
DATA
TOGGLE
DATA
TOGGLE
DATA
Erase Suspended &
Program Non-erasing Sector
in Plane B
DATA
I/O7
DATA
TOGGLE
DATA
TOGGLE
While
22
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
2-megabit
SRAM
Description
The 2-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 128K
words by 16 bits. The SRAM uses high-performance full CMOS process technology and is
designed for high-speed and low-power circuit technology. It is particularly well-suited for the
high-density low-power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
Features
• Fully Static Operation and Tri-state Output
• TTL Compatible Inputs and Outputs
• Battery Backup
– 1.2V (Min) Data Retention
Voltage (V)
Speed (ns)
Operation
Current/ICC (mA)
(Max)
2.7 - 3.3
70
10
Standby
Current (µA)
(Max)
Temperature
(°C)
10
-40 - 85
Block Diagram
ROW DECODER
A0
MEMORY ARRAY
512K X 16
WRITE DRIVER
COLUMN
DECODER
DATA I/O BUFFER
SENSE AMP
BLOCK
DECODER
PRE DECODER
ADD INPUT BUFFER
A16
I/O0
I/O7
I/O8
I/O15
SCS1
SCS2
SOE
SLB
SUB
SWE
23
2604B–STKD–09/02
Absolute Maximum Ratings(1)
Symbol
Parameter
Rating
Unit
VIN, VOUT
Input/Output Voltage
-0.3 to 3.6
V
VCC
Power Supply
-0.3 to 4.6
V
TA
Operating Temperature
-40 to 85
°C
TSTG
Storage Temperature
-55 to 150
°C
PD
Power Dissipation
1.0
W
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the
operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect reliability.
Truth Table
I/O Pin
SCS1
SCS2
H(1)
X
(1)
L
X
X
L
SWE
SOE
X
X
X
(1)
H
L
H
L
H
Notes:
H
L
H
H
X
L
SLB(2)
SUB(2)
X
X
Mode
I/O0 - I/O7
I/O8 - I/O15
Power
Deselected
High-Z
High-Z
Standby
Output Disabled
High-Z
High-Z
Active
DIN
High-Z
High-Z
DIN
H
H
L
H
H
L
L
L
L
H
H
L
L
L
DIN
DIN
L
H
DOUT
High-Z
H
L
High-Z
DOUT
L
L
DOUT
DOUT
Write
Read
Active
Active
1. H = VIH, L = VIL, X = Don't Care (VIL or VIH)
2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is
LOW, data is written or read to the lower byte, I/O0 - I/O8. When SUB is LOW, data is written or read to the upper byte, I/O9
- I/O16.
Recommended DC Operating Condition
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
2.3
3.0
3.3
V
VSS
Ground
0
0
0
V
VIH
Input High Voltage
VCC + 0.3
V
0.4
V
VIL
(1)
Note:
24
Input Low Voltage
2.2
-0.2
(1)
1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
DC Electrical Characteristics
TA = -40°C to 85°C
Symbol
Parameter
Test Condition
Min
ILI
Input Leakage Current
VSS < VIN < VCC
ILO
Output Leakage Current
VSS < VOUT < VCC,
SCS1 = VIH or SCS2=VIL or
SOE = V IH or SWE = VIL or
SUB = VIH, SLB = VIH
ICC
Operating Power Supply Current
SCS1 = VIL, SCS2=V IH,
VIN = V IH or VIL, II/O = 0 mA
ICC1
Average Operating Current
Max
Unit
-1
1
µA
-1
1
µA
5
10
mA
Cycle Time = 1 µs
II/O = 0 mA,
SCS1 = 0.2V, SCS2 = VCC -0.2V,
VIN ≤ 0.2V or V IN ≥ VCC - 0.2V
4
6
mA
Cycle Time = Min,
100% Duty, II/O = 0 mA
SCS1 = VIL, SCS2 = VIH,
VIN = V IH or VIL
30
45
mA
0.5
mA
10
µA
2
µA
0.4
V
ISB
Standby Current (TTL Input)
SCS1 = VIH or SCS2 = VIL
ISB1
Standby Current (CMOS Input)
SCS1 ≥ VCC - 0.2V
or
SCS2 ≤ VSS + 0.2V
VOL
Output Low
IOL = 0.5 mA
VOH
Output High
IOH = -0.5 mA
Note:
Typ(1)
LL
0.4
SL
2.0
V
1. Typical values are at VCC = 3.0V, TA = 25°C. Typical values are not 100% tested.
Capacitance(1)
(Temp = 25°C, f = 1.0 MHz)
Symbol
Parameter
CIN
COUT
Note:
Condition
Max
Unit
Input Capacitance (Add, SCS1,
SCS2, SLB, SUB, SWE, SOE)
VIN = 0 V
8
pF
Output Capacitance (I/O)
VI/O = 0 V
10
pF
1. These parameters are sampled and not 100% tested.
25
2604B–STKD–09/02
AC Characteristics
TA = -40°C to 85°C, Unless Otherwise Specified
70 ns
#
Symbol
Parameter
Min
1
Max
Unit
tRC
Read Cycle Time
70
2
tAA
Address Access Time
70
ns
3
tACS
Chip Select Access Time
70
ns
4
tOE
Output Enable to Output Valid
35
ns
5
tBA
SLB, SUB Access Time
35
ns
6
tCLZ
Chip Select to Output in Low Z
5
ns
7
tOLZ
Output Enable to Output in Low Z
0
ns
8
tBLZ
SLB, SUB Enable to Output in Low Z
0
ns
9
tCHZ
Chip Deselection to Output in High Z
0
30
ns
10
tOHZ
Out Disable to Output in High Z
0
30
ns
11
tBHZ
SLB, SUB Disable to Output in High Z
0
30
ns
12
tOH
Output Hold from Address Change
10
ns
13
tWC
Write Cycle Time
70
ns
14
tCW
Chip Selection to End of Write
60
ns
15
tAW
Address Valid to End of Write
60
ns
16
tBW
SLB, SUB Valid to End of Write
60
ns
17
tAS
Address Setup Time
0
ns
18
tWP
Write Pulse Width
50
ns
19
tWR
Write Recovery Time
0
ns
20
tWHZ
Write to Output in High Z
0
21
tDW
Data to Write Time Overlap
30
ns
22
tDH
Data Hold from Write Time
0
ns
23
tOW
Output Active from End of Write
5
ns
ns
25
ns
AC Test Conditions
TA = -40°C to 85°C, Unless Otherwise Specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Level
1.5V
Output Load
CL = 5 pF + 1 TTL Load
CL = 5 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load
26
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
Output Test Load
Timing Diagrams
Read Cycle 1(1),(4)
tRC
ADDRESS
tAA
tOH
tACS
SCS1
SCS2
tCHZ(3)
tBA
SUB, SLB
tBHZ(3)
tOE
SOE
tOLZ(3)
tOHZ (3)
tBLZ(3)
DATA OUT
HIGH-Z
tCLZ(3)
DATA VALID
Read Cycle 2(1),(2),(4)
tRC
ADDRESS
tAA
tOH
tOH
DATA OUT
PREVIOUS DATA
DATA VALID
Read Cycle 3(1),(2),(4)
SCS1
SUB, SLB
SCS2
DATA OUT
Notes:
tACS
tCLZ (3)
tCHZ (3)
DATA VALID
1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE = VIL.
3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
27
2604B–STKD–09/02
Write Cycle 1 (SWE Controlled)(1),(4),(8)
tWC
ADDRESS
tWR(2)
tCW
SCS1
SCS2
tAW
tBW
SUB, SLB
tWP
SWE
tAS
DATA IN
tDW
tDH
tAS
HIGH-Z
DATA VALID
(3)(7)
tOW
tWHZ
(5)
(5)
DATA OUT
Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
tWC
ADDRESS
tWR(2)
tCW
tAS
SCS1
tAW
SCS2
tBW
SUB, SLB
tWP
SWE
tDW
DATA IN
HIGH-Z
DATA OUT
Notes:
28
tDH
DATA VALID
HIGH-Z
1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.
2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
the SWE transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
Data Retention Electric Characteristic
TA = -40°C to 85°C
Symbol
Parameter
Test Condition
Min
VDR
VCC for Data Retention
SCS1 > V CC -0.2V,
SCS2 ≤ 0.2V or
VCC - 0.2V,
VSS ≤ VIN ≤ VCC
1.2
ICCDR
Data Retention Current
VCC = 3.0V,
SCS1 > V CC - 0.2V or
SCS2 ≤ VSS + 0.2V or
VSS ≤ VIN ≤ VCC
tCDR
Chip Deselect to Data
Retention Time
tR
Operating Recovery Time
Notes:
Typ
Max
Unit
3.3
V
9.5
µA
0.7
µA
0.4(1)
0
ns
tRC(2)
ns
See Data Retention Timing Diagram
1. Typical values are under the condition of TA = 25°C. Typical values are sampled and not 100% tested.
2. tRC is read cycle time.
Data Retention Timing Diagram 1
DATA RETENTION MODE
VCC
2.3V
tCDR
tR
IH
VDR
SCS1 > VCC - 0.2V
SCS1
VSS
Data Retention Timing Diagram 2
DATA RETENTION MODE
VCC
2.3V
tCDR
tR
SCS2
VDR
0.4V
VSS
SCS2 < 0.2V
29
2604B–STKD–09/02
4-megabit
SRAM
Description
The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 256K
words by 16 bits. The SRAM uses high-performance full CMOS process technology and is
designed for high-speed and low-power circuit technology. It is particularly well-suited for the
high-density low-power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
Features
• Fully Static Operation and Tri-state Output
• TTL Compatible Inputs and Outputs
• Battery Backup
– 1.2V (Min) Data Retention
Voltage (V)
Speed (ns)
Operation
Current/ICC (mA)
(Max)
2.7 - 3.3
70
5
Standby
Current (µA)
(Max)
Temperature
(°C)
15
-40 - 85
Block Diagram
ROW DECODER
A0
MEMORY ARRAY
256K X 16
WRITE DRIVER
COLUMN
DECODER
DATA I/O BUFFER
SENSE AMP
BLOCK
DECODER
PRE DECODER
ADD INPUT BUFFER
A17
I/O0
I/O7
I/O8
I/O15
SCS1
SCS2
SOE
SLB
SUB
SWE
30
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
Absolute Maximum Ratings(1)
Symbol
Parameter
Rating
Unit
VIN, VOUT
Input/Output Voltage
-0.3 to 3.6
V
VCC
Power Supply
-0.3 to 4.6
V
TA
Operating Temperature
-40 to 85
°C
TSTG
Storage Temperature
-55 to 150
°C
PD
Power Dissipation
1.0
W
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the
operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect reliability.
Truth Table
I/O Pin
SCS1
(1)
X
(1)
L
H
X
SCS2
X
L
SWE
SOE
X
X
X
(1)
H
L
H
H
L
H
SLB(2)
SUB(2)
X
X
H
H
L
H
H
L
L
L
L
H
H
L
H
H
I/O8 - I/O15
Power
Deselected
High-Z
High-Z
Standby
Output Disabled
High-Z
High-Z
Active
DIN
High-Z
High-Z
DIN
DIN
DIN
DIN
High-Z
DOUT
High-Z
High-Z
DOUT
DOUT
DOUT
DOUT
High-Z
Write
L
L
H
H
L
L
Read
L
Notes:
I/O0 - I/O7
X
L
L
Mode
L
Active
Active
1. H = VIH, L = VIL, X = Don't Care (VIL or VIH)
2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is
LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8
- I/O15.
Recommended DC Operating Condition
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
2.7
3.0
3.3
V
VSS
Ground
0
0
0
V
VIH
Input High Voltage
VCC + 0.3
V
0.6
V
VIL
(1)
Note:
Input Low Voltage
2.2
-0.31
(1)
1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
31
2604B–STKD–09/02
DC Electrical Characteristics
TA = -40°C to 85°C
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
VSS < VIN < VCC
-1
1
µA
ILO
Output Leakage Current
VSS < VOUT < VCC,
SCS1 = VIH or SCS2=VIL or
SOE = V IH or SWE = VIL or
SUB = VIH, SLB = VIH
-1
1
µA
ICC
Operating Power Supply Current
SCS1 = VIL, SCS2=V IH,
VIN = V IH or VIL, II/O = 0 mA
5
mA
ICC1
Average Operating Current
SCS1 = VIL, SCS2 = VIH,
VIN = V IH or VIL, Cycle Time = Min
100% Duty, II/O = 0 mA
35
mA
SCS1 < 0.2V, SCS2 > VCC - 0.2V
VIN < 0.2V or VIN > V CC - 0.2V,
Cycle Time = 1 µs
100% Duty, II/O = 0 mA
5
mA
0.5
mA
SL
4
µA
LL
15
µA
0.4
V
ISB
Standby Current (TTL Input)
SCS1 = VIH or SCS2 = VIL or
SUB, SLB = VIH
VIN = V IH or VIL
ISB1
Standby Current (CMOS Input)
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > V CC - 0.2V or
VIN < V SS + 0.2V
VOL
Output Low
IOL = 0.1 mA
VOH
Output High
IOH = -0.1 mA
2.4
V
Capacitance(1)
(Temp = 25°C, f = 1.0 MHz)
Symbol
Parameter
CIN
COUT
Note:
32
Condition
Max
Unit
Input Capacitance (Add, SCS1,
SCS2, SLB, SUB, SWE, SOE)
VIN = 0 V
8
pF
Output Capacitance (I/O)
VI/O = 0 V
10
pF
1. These parameters are sampled and not 100% tested.
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
AC Characteristics
TA = -40°C to 85°C, Unless Otherwise Specified
70 ns
#
Symbol
Parameter
Min
1
Max
Unit
tRC
Read Cycle Time
70
2
tAA
Address Access Time
70
ns
3
tACS
Chip Select Access Time
70
ns
4
tOE
Output Enable to Output Valid
35
ns
5
tBA
SLB, SUB Access Time
70
ns
6
tCLZ
Chip Select to Output in Low Z
10
ns
7
tOLZ
Output Enable to Output in Low Z
5
ns
8
tBLZ
SLB, SUB Enable to Output in Low Z
10
ns
9
tCHZ
Chip Deselection to Output in High Z
0
30
ns
10
tOHZ
Out Disable to Output in High Z
0
30
ns
11
tBHZ
SLB, SUB Disable to Output in High Z
0
30
ns
12
tOH
Output Hold from Address Change
10
ns
13
tWC
Write Cycle Time
70
ns
14
tCW
Chip Selection to End of Write
60
ns
15
tAW
Address Valid to End of Write
60
ns
16
tBW
SLB, SUB Valid to End of Write
60
ns
17
tAS
Address Setup Time
0
ns
18
tWP
Write Pulse Width
50
ns
19
tWR
Write Recovery Time
0
ns
20
tWHZ
Write to Output in High Z
0
21
tDW
Data to Write Time Overlap
30
ns
22
tDH
Data Hold from Write Time
0
ns
23
tOW
Output Active from End of Write
5
ns
ns
20
ns
AC Test Conditions
TA = -40°C to 85°C, Unless Otherwise Specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Level
1.5V
Output Load
CL = 5 pF + 1 TTL Load
CL = 5 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load
33
2604B–STKD–09/02
Output Test Load
Timing Diagrams
Read Cycle 1(1),(4)
tRC
ADDRESS
tAA
tOH
tACS
SCS1
SCS2
tCHZ(3)
tBA
SUB, SLB
tBHZ(3)
tOE
SOE
tOLZ(3)
tOHZ (3)
tBLZ(3)
DATA OUT
HIGH-Z
tCLZ(3)
DATA VALID
Read Cycle 2(1),(2),(4)
tRC
ADDRESS
tAA
tOH
tOH
DATA OUT
PREVIOUS DATA
DATA VALID
Read Cycle 3(1),(2),(4)
SCS1
SUB, SLB
SCS2
tACS
tCLZ (3)
DATA OUT
Notes:
34
tCHZ (3)
DATA VALID
1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE = VIL.
3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
Write Cycle 1 (SWE Controlled)(1),(4),(8)
tWC
ADDRESS
tWR(2)
tCW
SCS1
SCS2
tAW
tBW
SUB, SLB
tWP
SWE
tAS
DATA IN
tDW
tDH
tAS
HIGH-Z
DATA VALID
tWHZ(3)(7)
tOW
(5)
(5)
DATA OUT
Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
tWC
ADDRESS
tWR(2)
tCW
tAS
SCS1
tAW
SCS2
tBW
SUB, SLB
tWP
SWE
tDW
DATA IN
DATA OUT
Notes:
HIGH-Z
tDH
DATA VALID
HIGH-Z
1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.
2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
the SWE transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
35
2604B–STKD–09/02
Data Retention Electric Characteristic
TA = -40°C to 85°C
Symbol
Parameter
Test Condition
Min
VDR
VCC for Data Retention
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
1.2
ICCDR
Data Retention Current
Vcc=1.5V,
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
tCDR
tR
Note:
Chip Deselect to Data
Retention Time
Typ(1)
Max
Unit
3.3
V
SL
0.1
2
µA
LL
0.1
10
µA
0
ns
tRC(2)
ns
See Data Retention Timing Diagram
Operating Recovery Time
1. Typical values are under the condition of TA = 25°C. Typical values are sampled and not 100% tested.
2. tRC is read cycle time.
Data Retention Timing Diagram 1
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
IH
VDR
SCS1 > VCC - 0.2V
SCS1
VSS
Data Retention Timing Diagram 2
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
SCS2
VDR
0.4V
VSS
36
SCS2 < 0.2V
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
AT52BR1672(T)/1674(T)
Ordering Information
tACC (ns)
Voltage Range
85
2.7V - 3.3V
85
Ordering Code
Package
Operation Range
AT52BR1672(T)-85CI
66C5
Industrial
(-40° to 85°C)
2.7V - 3.3V
AT52BR1674(T)-85CI
66C5
Industrial
(-40° to 85°C)
85
2.7V - 3.3V
AT52BR1672-85CI
66C5
Industrial
(-40° to 85°C)
85
2.7V - 3.3V
AT52BR1674-85CI
66C5
Industrial
(-40° to 85°C)
Package Type
66C5
66-ball, Plastic Chip-scale Ball Grid Array Package (CBGA)
37
2604B–STKD–09/02
Package Drawing
66C5 – CBGA
0.12 C
E
C Seating Plane
Marked A1 Identifier
D
Side View
A1
Top View
A
0.60 REF
E1
A1 Ball Corner
e
1.20 REF
A
B
C
D
D1
E
COMMON DIMENSIONS
(Unit of Measure = mm)
F
G
H
e
12 11
10
9
8
7
6
5
4
3
2
1
Øb
Bottom View
SYMBOL
MIN
NOM
MAX
E
9.90
10.00
10.10
E1
–
8.80
–
D
7.90
8.00
8.10
D1
–
5.60
–
A
–
–
1.20
A1
0.25
–
–
e
Øb
NOTE
0.80 BSC
–
0.40
–
09/19/01
R
38
2325 Orchard Parkway
San Jose, CA 95131
TITLE
66C5, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball
Pitch Chip-scale Ball Grid Array Package (CBGA)
DRAWING NO.
66C5
REV.
A
AT52BR1672(T)/1674(T)
2604B–STKD–09/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
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Web Site
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© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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Printed on recycled paper.
2604B–STKD–09/02
/0M