TI TPS54610-Q1

Typical Size
6,4 mm X 9,7 mm
TPS54610-Q1
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SLVS726 – JANUARY 2007
3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM
SWITCHER WITH INTEGRATED FETs (SWIFT™)
FEATURES
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
30-mΩ, 12-A Peak MOSFET Switches for High
Efficiency at 6-A Continuous Output Source
or Sink Current
Adjustable Output Voltage Down to 0.9 V With
1.0% Accuracy
Wide PWM Frequency: Fixed 350 kHz, 550 kHz
or Adjustable 280 kHz to 700 kHz
Synchronizable to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Component Count
SWIFT Documentation, Application Notes, and
Design Software: www.ti.com/swift
APPLICATIONS
•
•
•
•
Low-Voltage, High-Density Distributed Power
Systems
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs, and
Microprocessors
Broadband, Networking, and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
DESCRIPTION
As a member of the SWIFT™ family of dc/dc
regulators, the TPS54610 low-input voltage
high-output current synchronous buck PWM
converter integrates all required active components.
Included on the substrate with the listed features are
a true, high-performance, voltage error amplifier that
enables maximum performance and flexibility in
choosing the output filter L and C components; an
under-voltage-lockout circuit to prevent start-up until
the input voltage reaches 3 V; an internally or
externally set slow-start circuit to limit inrush
currents; and a power good output, useful for
processor/logic reset, fault signaling, and supply
sequencing.
The TPS54610 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT™ designer software tool to
aid in quickly achieving high-performance power
supply designs to meet aggressive equipment
development cycles.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPS54610-Q1
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SLVS726 – JANUARY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED SCHEMATIC
EFFICIENCY AT 350 kHz
100
Input
Output
VIN
95
PH
90
TPS54610
BOOT
Efficiency − %
85
PGND
VSENSE
VBIAS
AGND COMP
80
75
70
65
VI = 5 V,
VO = 3.3 V
60
55
50
0
1
2
3
4
5
6
Load Current − A
ORDERING INFORMATION (1)
(1)
(2)
2
TJ
OUTPUT VOLTAGE
PACKAGE (2)
PART NUMBER
40°C to 125°C
Adjustable down to 0.9 V
Plastic HTSSOP (PWP)
TPS54610QPWPRQ1
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
See the application section of the data sheet for PowerPAD drawing and layout information.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TPS54610
VI
VO
Input voltage range
Output voltage range
IO
Source current
IS
Sink current
VIN, SS/ENA, SYNC
–0.3 V to 7 V
RT
–0.3 V to 6 V
VSENSE
–0.3 V to 4 V
BOOT
–0.3 V to 17 V
VBIAS, COMP, PWRGD
–0.3 V to 7 V
PH
–0.6 V to 10 V
PH
Internally Limited
COMP, VBIAS
Voltage differential
6 mA
PH
12 A
COMP
6 mA
SS/ENA, PWRGD
10 mA
AGND to PGND
±0.3 V
TJ
Operating virtual junction temperature range
–40°C to 150°C
Tstg
Storage temperature
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for
10 seconds
(1)
300°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
VI
Input voltage
TJ
Operating junction temperature
MIN
MAX
3
6
UNIT
V
–40
125
°C
Dissipation Ratings (1) (2)
(1)
(2)
(3)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
28 Pin PWP with solder
18.2 °C/W
5.49 W (3)
3.02 W
2.20 W
28 Pin PWP without solder
40.5 °C/W
2.48 W
1.36 W
0.99 W
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
Test board conditions:
a. 3” x 3”, 4 layers, thickness: 0.062”
b. 1.5-oz. copper traces located on the top of the PCB
c. 1.5-oz. copper ground plane on the bottom of the PCB
d. 0.5-oz. copper ground planes on the 2 internal layers
e. 12 thermal vias (see Recommended Land Pattern in applications section of this data sheet
Maximum power dissipation may be limited by over current protection.
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Electrical Characteristics
TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
IQ
Quiescent current
3
6
fs = 350 kHz, SYNC ≤ 0.8 V, RT open,
PH pin open
11
15.8
fs = 550 kHz, SYNC ≥ 2.5 V, RT open,
PH pin open
16
23.5
Shutdown, SS/ENA = 0 V
1
1.4
2.95
3.0
V
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
V
Stop threshold voltage, UVLO
2.70
2.80
Hysteresis voltage, UVLO
0.14
0.16
V
2.5
µs
Rising and falling edge deglitch, UVLO (1)
V
BIAS VOLTAGE
Output voltage, VBIAS
I(VBIAS) = 0
2.70
2.80
Output current, VBIAS (2)
2.95
V
100
µA
0.900
V
CUMULATIVE REFERENCE
Vref
Accuracy
0.882
0.891
REGULATION
Line regulation (1) (2) (3)
Load regulation (1) (3)
IL = 3 A, fs = 350 kHz, TJ = 125°C
0.07
IL = 3 A, fs = 550 kHz, TJ = 125°C
0.07
IL = 0 A to 6 A, fs = 350 kHz, TJ = 125°C
0.03
IL = 0 A to 6 A, fs = 550 kHz, TJ = 125°C
0.03
%/V
%/A
OSCILLATOR
Internally set—free running frequency
SYNC ≤ 0.8 V, RT open
265
350
440
SYNC ≥ 2.5 V, RT open
415
550
680
RT = 180 kΩ (1% resistor to AGND) (1)
252
280
308
290
312
350
663
700
762
Externally set—free running frequency range RT = 160 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND) (1)
High level threshold, SYNC (1)
Low level threshold,
2.5
0.8
50
Frequency range, SYNC (1)
4
V
200
Maximum duty cycle (1)
90%
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 10
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kHz
V
1
Minimum controllable on time (1)
(1)
(2)
(3)
700
0.75
Ramp amplitude (peak-to-peak) (1)
V
ns
330
Ramp valley (1)
kHz
V
SYNC (1)
Pulse duration, external synchronization,
SYNC (1)
kHz
ns
TPS54610-Q1
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SLVS726 – JANUARY 2007
Electrical Characteristics (continued)
TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain
1 kΩ COMP to AGND (4)
90
110
Error amplifier unity gain bandwidth
Parallel 10 kΩ, 160 pF COMP to AGND (4)
3
5
Error amplifier common mode input voltage
range
Powered by internal LDO (4)
0
Input bias current, VSENSE (4)
VSENSE = Vref
60
Output voltage slew rate (symmetric),
COMP (4)
1
dB
MHz
VBIAS
V
250
nA
1.4
V/µs
PWM COMPARATOR
PWM comparator propagation delay time,
PWM comparator input to PH pin (excluding
deadtime)
10-mV overdrive (4)
70
85
ns
1.20
1.40
V
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
Enable hysteresis voltage,
0.82
SS/ENA (4)
Falling edge deglitch, SS/ENA (4)
Internal slow-start time (4)
2.6
0.03
V
2.5
µs
3.35
4.1
ms
Charge current, SS/ENA
SS/ENA = 0 V
2.5
5
8
µA
Discharge current, SS/ENA
SS/ENA = 1.2 V, VI = 2.7 V
1.2
2.3
4
mA
POWER GOOD
Power good threshold voltage
VSENSE falling
Power good hysteresis voltage (4)
Power good falling edge deglitch (4)
90
%Vref
3
%Vref
35
Output saturation voltage, PWRGD
I(sink) = 2.5 mA
Leakage current, PWRGD
VI = 5.5 V
0.18
µs
0.3
V
1
µA
CURRENT LIMIT
Current limit trip point
VI = 3 V Output shorted (4)
VI= 6 V Output
shorted (4)
7.2
10
10
12
A
Current limit leading edge blanking time (4)
100
ns
Current limit total response time (4)
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point (4)
135
Thermal shutdown hysteresis (4)
150
165
10
°C
°C
OUTPUT POWER MOSFETS
rDS(on)
(4)
(5)
Power MOSFET switches
VI = 6 V (5)
26
47
VI = 3 V (5)
36
65
mΩ
Specified by design
Matched MOSFETs low-side rDS(on) production tested, high-side rDS(on) specified by design
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PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
THERMAL 22
PAD
21
20
19
18
17
16
15
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
Terminal Functions
TERMINAL
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT
resistor and SYNC pin. Connect PowerPAD to AGND.
BOOT
5
Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for
the high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
PGND
15-19
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single
point connection to AGND is recommended.
PH
6-14
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or the internal shutdown signal is active.
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using
the SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
SS/ENA
26
Slow-start/enable input/output. Dual function pin that provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SYNC
27
Synchronization input. Dual function pin that provides logic input to synchronize to an external oscillator or pin
select between two internally set switching frequencies. When used to synchronize to an external signal, a
resistor must be connected to the RT pin.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with
a high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
20-24
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low-ESR 10-µF ceramic capacitor.
VIN
VSENSE
6
DESCRIPTION
NAME
2
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
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VBIAS
AGND
VIN
Enable
Comparator
SS/ENA
Falling
Edge
Deglitch
1.2 V
Hysteresis: 0.03 V
2.5 µs
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16 V
REG
VBIAS
SHUTDOWN
VIN
ILIM
Comparator
Thermal
Shutdown
150°C
3−6V
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
30 mΩ
2.5 µs
SS_DIS
SHUTDOWN
Internal/External
Slow-start
(Internal Slow-start Time = 3.35 ms
PH
+
−
R Q
Error
Amplifier
Reference
VREF = 0.891 V
S
PWM
Comparator
LOUT
VO
CO
Adaptive Dead-Time
and
Control Logic
VIN
30 mΩ
OSC
PGND
Power-good
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.90 Vref
TPS54610
Hysteresis: 0.03 Vref
VSENSE
COMP
RT
SHUTDOWN
35 µs
SYNC
ADDITIONAL 6-A SWIFT™ DEVICES (SEE SLVS397 and SLVS400)
DEVICE
OUTPUT VOLTAGE
DEVICE
OUTPUT VOLTAGE
DEVICE
OUTPUT VOLTAGE
TPS54611
0.9 V
TPS54614
1.8 V
TPS54672
DDR Memory/Adj.
TPS54612
1.2 V
TPS54615
2.5 V
TPS54673
Pre-bias/Adj.
TPS54613
1.5 V
TPS54616
3.3 V
TPS54680
Sequencing/Adj.
RELATED DC/DC PRODUCTS
•
•
•
TPS40000 dc/dc controller
TPS759xx 7.5-A low dropout regulator
PT6440 series 6-A plugin modules
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SLVS726 – JANUARY 2007
TYPICAL CHARACTERISTICS
VIN = 3.3 V
IO = 6 A
50
40
30
20
10
0
25
85
TJ − Junction Temperature − °C
60
VIN = 5 V
50
IO = 6 A
40
30
20
10
0
−40
125
0
25
85
TJ − Junction Temperature − °C
650
SYNC ≥ 2.5 V
550
450
SYNC ≤ 0.8 V
350
250
−40
25
85
125
Figure 3.
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
DEVICE POWER LOSSES
AT TJ = 125°C
vs
LOAD CURRENT
0.895
800
5
TJ = 125°C
fs = 700 kHz
4.5
RT = 68 k
600
500
RT = 100 k
400
300
0.893
Device Power Losses − W
700
0.891
0.889
0.887
4
3
2.5
2
1.5
25
VI = 5 V
1
0.885
0
VI = 3.3 V
3.5
0.5
RT = 180 k
200
−40
0
TJ − Junction Temperature − °C
Figure 2.
85
125
0
−40
0
25
85
TJ − Junction Temperature − °C
0
125
1
2
3
4
5
6
7
8
IL − Load Current − A
Figure 4.
Figure 5.
Figure 6.
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
ERROR AMPLIFIER
OPEN LOOP RESPONSE
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
RL = 10 kΩ,
CL = 160 pF,
TA = 25°C
120
0.893
3.80
0
140
TA = 85°C,
IO = 3 A
−20
−40
0.891
Gain − dB
−60
fs = 550 kHz
0.889
80
Phase
−80
−100
60
−120
40
Gain
20
−140
−160
0.887
0.885
0
−180
−20
−200
1 k 10 k 100 k 1 M 10 M
1
3
3.5
4
4.5
5
VI − Input Voltage − V
Figure 7.
5.5
6
10
100
f − Frequency − Hz
Figure 8.
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Phase − Degrees
100
Internal Slow-Start Time − ms
0.895
VO − Output Voltage Regulation − V
125
750
Figure 1.
TJ − Junction Temperature − °C
8
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
f − Internally Set Oscillator Frequency − kHz
Drain-Source On-State Resistance − m Ω
60
0
−40
f − Externally Set Oscillator Frequency − kHz
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
V ref − Voltage Reference − V
Drain-Source On-State Resistance − m Ω
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
3.65
3.50
3.35
3.20
3.05
2.90
2.75
−40
0
25
85
TJ − Junction Temperature − °C
Figure 9.
125
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APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical TPS54610 application. The TPS54610 (U1) can provide
greater than 6 A of output current at a nominal output voltage of 3.3 V. For proper thermal performance, the
exposed thermal PowerPAD under the integrated circuit package must be soldered to the printed-circuit board.
VI
+
C2
220 µF
10 V
U1
TPS54610PWP
28
R2
10 kΩ
VIN
VIN
27
26
25
C1
0.047 µF
RT
VIN
SYNC
VIN
VIN
SS/ENA
PH
PH
VBIAS
PH
PWRGD
4
C4
0.1 µF
3
PH
PWRGD
PH
PH
COMP
PH
PH
C8
10 µF
24
23
22
21
L1
4.7 µH
20
14
13
+
12
11
C9
+
470 µF
4V
C10
470 µF
4V
C11
100 pF
VO
10
9
8
7
6
PH
5
VSENSE
BOOT
19
PGND
18
PGND
17
PGND
16
1
AGND
PGND
15
PGND
POWERPAD
C7
2
C3
120 pF
C5
5600 pF
0.047 µF
R1
9.09 kΩ
C6
R3
3.74 kΩ
R5
8200 pF
1.74 kΩ
R4
10 kΩ
Figure 10. Application Circuit
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COMPONENT SELECTION
The values for the components used in this design
example were selected using the SWIFT designer
software tool. SWIFT designer provides a complete
design environment for developing dc-dc converters
using the TPS54610.
INPUT FILTER
The input to the circuit is a nominal 5 VDC. The input
filter C2 is a 220-µF POSCAP capacitor, with a
maximum allowable ripple current of 3 A. C8
provides high frequency decoupling of the TPS54610
from the input supply and must be located as close
as possible to the device. Ripple current is carried in
both C2 and C8, and the return path to PGND must
avoid the current circulating in the output capacitors
C9 and C10.
FEEDBACK CIRCUIT
The resistor divider network of R3 and R4 sets the
output voltage for the circuit at 3.3 V. R4, along with
R1, R5, C3, C5, and C6 form the loop compensation
network for the circuit. For this design, a Type 3
topology is used.
OPERATING FREQUENCY
In the application circuit, the 350 kHz operation is
selected by leaving RT and SYNC open. Connecting
a 180 kΩ to 68 kΩ resistor between RT (pin 28) and
analog ground can be used to set the switching
frequency to 280 kHz to 700 kHz. To calculate the
RT resistor, use the equation below:
500 kHz
R+
100 [kW]
Switching Frequency
(1)
OUTPUT FILTER
The output filter is composed of a 4.7-µH inductor
and two 470-µF capacitors. The inductor is a low dc
resistance (12 mΩ) type, Coiltronics UP3B-4R7. The
capacitors used are 4-V POSCAP types with a
maximum ESR of 0.040 Ω. The feedback loop is
compensated so that the unity gain frequency is
approximately 25 kHz.
PCB LAYOUT
Figure 11 shows a generalized PCB layout guide for
the TPS54610.
The VIN pins are connected together on the
printed-circuit board (PCB) and bypassed with a
low-ESR ceramic-bypass capacitor. Care should be
taken to minimize the loop area formed by the
10
bypass capacitor connections, the VIN pins, and the
TPS54610 ground pins. The minimum recommended
bypass capacitance is 10-mF ceramic capacitor with
a X5R or X7R dielectric and the optimum placement
is closest to the VIN pins and the PGND pins.
The TPS54610 has two internal grounds (analog and
power). Inside the TPS54610, the analog ground ties
to all of the noise sensitive signals, while the power
ground ties to the noisier power signals. Noise
injected between the two grounds can degrade the
performance of the TPS54610, particularly at higher
output currents. However, ground noise on an analog
ground plane can also cause problems with some of
the control and bias signals. For these reasons,
separate analog and power ground traces are
recommended. There is an area of ground on the top
layer directly under the IC, with an exposed area for
connection to the PowerPAD. Use vias to connect
this ground area to any internal ground planes.
Additional vias are also used at the ground side of
the input and output filter capacitors. The AGND and
PGND pins are tied to the PCB ground by
connecting them to the ground area under the device
as shown. The only components that tie directly to
the power ground plane are the input capacitors, the
output capacitors, the input voltage decoupling
capacitor, and the PGND pins of the TPS54610. Use
a separate wide trace for the analog ground signal
path. The analog ground is used for the voltage set
point divider, timing resistor RT, slow-start capacitor
and bias capacitor grounds. Connect this trace
directly to AGND (Pin 1).
The PH pins are tied together and routed to the
output inductor. Since the PH connection is the
switching node, the inductor is located close to the
PH pins. The area of the PCB conductor is
minimized to prevent excessive capacitive coupling.
Connect the boot capacitor between the phase node
and the BOOT pin as shown. Keep the boot
capacitor close to the IC and minimize the conductor
trace lengths.
Connect the output filter capacitor(s) as shown
between the VOUT trace and PGND. It is important
to keep the loop formed by the PH pins, LOUT,
COUT and PGND as small as practical.
Place the compensation components from the VOUT
trace to the VSENSE and COMP pins. Do not place
these components too close to the PH trace. Due to
the size of the IC package and the device pin-out,
they must be routed close, but maintain as much
separation as possible while still keeping the layout
compact.
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Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency,
connect them to this trace.
ANALOG GROUND TRACE
FREQUENCY SET RESISTOR
AGND
RT
SYNC
VSENSE
COMPENSATION
NETWORK
COMP
SLOW START
CAPACITOR
SS/ENA
BIAS CAPACITOR
PWRGD
BOOT
CAPACITOR
BOOT
PH
VOUT
PH
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
VBIAS
VIN
EXPOSED
POWERPAD
AREA
VIN
PH
VIN
PH
VIN
PH
VIN
PH
PGND
PH
PGND
PH
PGND
PH
PGND
PH
PGND
VIN
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
TOPSIDE GROUND AREA
VIA to Ground Plane
Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD
Submit Documentation Feedback
11
TPS54610-Q1
www.ti.com
SLVS726 – JANUARY 2007
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog
ground plane must provide an adequate heat
dissipating area. A 3-inch by 3-inch plane of 1 ounce
copper is recommended, though not mandatory,
depending on ambient temperature and airflow. Most
applications have larger areas of internal ground
plane available, and the PowerPAD must be
connected to the largest area available. Additional
areas on the top or bottom layers also help dissipate
heat, and any area available must be used when 6 A
or greater operation is desired. Connection from the
exposed area of the PowerPAD to the analog ground
8 PL q 0.0130
4 PL
q 0.0180
plane layer must be made using 0.013 inch diameter
vias to avoid solder wicking through the vias. Eight
vias must be in the PowerPAD area with four
additional vias located under the device package.
The size of the vias under the package, but not in
the exposed thermal pad area, can be increased to
0.018. Additional vias beyond the twelve
recommended that enhance thermal performance
must be included in areas not under the device
package.
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.06
0.0150
0.0339
0.0650
0.0500
0.3820 0.3478 0.0500
0.0500
0.2090
0.0256
0.0650
0.0339
0.1700
0.1340
Minimum Recommended Top
Side Analog Ground Area
Minimum Recommended Exposed
Copper Area for Powerpad. 5mm
Stencils May Require 10 Percent
Larger Area
0.0630
0.0400
Figure 12. Recommended Land Pattern for 28-Pin PWP PowerPAD
12
Submit Documentation Feedback
TPS54610-Q1
www.ti.com
SLVS726 – JANUARY 2007
PERFORMANCE GRAPHS
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
100
100
95
95
90
90
LOAD REGULATION
vs
OUTPUT CURRENT
1.004
VI = 5 V,
VO = 3.3 V,
TA = 25°C,
fs = 550 kHz
1.003
VO = 1.8 V
75
70
VO = 1.2 V
65
55
VO = 3.3 V
80
VO = 1.8 V
75
VO = 1.2 V
70
65
VI = 3.3 V,
f = 550 kHz,
L = 4.7 µH,
TA = 25°C
60
VI = 5 V,
f = 550 kHz,
L = 4.7 µH,
TA = 25°C
60
55
2
3
4
5
IO − Output Current − A
6
7
0.996
0
1
2
3
4
5
IO − Output Current − A
Figure 13.
LINE REGULATION
vs
INPUT VOLTAGE
1.002
1.0015
IO = 6 A
1.001
1.0005
Gain − dB
1
0.9995
7
4
5
6
125
180
VI = 5 V,
VO = 3.3 V,
IO = 6 A,
TA = 25°C,
fs = 550 kHz
TJ = 125°C
fs = 700 kHz
115
135
20
90
Phase
45
105
VI = 5 V
95
85
Safe Operating Area
75
65
VI = 3.3 V
55
45
35
−20
0.998
4.5
5
5.5
100
6
1k
10 k
100 k
0
1M
25
0
f − Frequency − Hz
VI − Input Voltage − V
1
2
3
4
5
6
Figure 18.
OUTPUT RIPPLE VOLTAGE
LOAD TRANSIENT RESPONSE
SLOW-START TIMING
t - Time = 1 ms/div
Figure 19.
8
t - Time = 100 ms/div
Figure 20.
VI = 5 V ,
No Slow-Start Cap
Output Voltage - 2 V/div
VI = 5 V,
1A to 5A,
Input Voltage - 2 V/div
Figure 17.
Output Voltage - 50 mV/div
Figure 16.
VI = 5 V,
VO = 3.3 V,
6 A, 350 kHz
7
IO − Output Current − A
Output Current - 2 A/div
4
Output Ripple Voltage - 10 mV/div
3
LOOP RESPONSE
0.9985
(1)
2
AMBIENT TEMPERATURE
vs
LOAD CURRENT (1)
0
0.999
1
IO − Output Current − A
Gain
No Load
0
Figure 15.
40
IO = 3 A
6
Figure 14.
60
VI = 5 V,
VO = 3.3 V,
TA = 25°C,
fs = 550 kHz
0.999
Ambient Temperature − ° C
1
1
0.997
50
0
1.001
0.998
Phase −Degrees
50
Line Regulation
Load Regulation
VO = 2.5 V
80
85
Efficiency − %
Efficiency − %
1.002
85
t - Time = 2 ms/div
Figure 21.
Safe operating area is applicable to the test board conditions in the Dissipation Ratings.
Submit Documentation Feedback
13
TPS54610-Q1
www.ti.com
SLVS726 – JANUARY 2007
Figure 22 shows the schematic diagram for a
reduced size, high frequency application using the
TPS54610. The TPS54610 (U1) can provide up to
6 A of output current at a nominal outputvoltage of
1.8 V. A small size 0.56-µH inductor is used and the
switching frequency is set to 680 kHz by R1. The
compensation network is optimized for fast transient
response as shown in Figure 22. For good thermal
performance, the PowerPAD under the integrated
circuit TPS54610 needs to be soldered well to the
printed-circuit board. Application information is
available in TI literature number SLVA107, Designing
for Small-Size, High-Frequency Applications With
Swift™Family of Synchronous Buck Regulators.
VI
C1
10 µF
U1
TPS54610PWP
C2
10 µF
R1
28
RT
VIN
71.5 kΩ
VIN
27
C3
0.047 µF
26
C4
1 µF
25
SYNC
VIN
SS/ENA
PH
VBIAS
PWRGD
C5
3
10 kΩ
C6
VIN
PH
PH
4
R2
VIN
PH
PH
COMP
470 pF
PH
PH
PH
23
22
21
20
14
13
12
11
10
9
8
7
L1
0.56 µH
6
PH
5
C7
VSENSE
BOOT
19
0.047 µF
PGND
18
PGND
R4
17
PGND
2.4 Ω
16
1
AGND
PGND
15
PGND
C11
POWERPAD
3300 pF
470 pF
VO
2
R5
1.47 kΩ
R3
39 Ω
R6
1.5 kΩ
24
+
C8
+
150 µF
C12
0.012 µF
2 A/div
50 mV/div
Figure 22. Small-Size, High-Frequency Design
10 µs/div
Figure 23. Transient Response, 1.5-A to 4.5-A Step
14
Submit Documentation Feedback
C9
150 µF
C10
1 pF
TPS54610-Q1
www.ti.com
SLVS726 – JANUARY 2007
DETAILED DESCRIPTION
UNDERVOLTAGE LOCK OUT (UVLO)
VBIAS REGULATOR (VBIAS)
The TPS54610 incorporates an under voltage
lockout circuit to keep the device disabled when the
input voltage (VIN) is insufficient. During power up,
internal circuits are held inactive until VIN exceeds
the nominal UVLO threshold voltage of 2.95 V. Once
the UVLO start threshold is reached, device start-up
begins. The device operates until VIN falls below the
nominal UVLO stop threshold of 2.8 V. Hysteresis in
the UVLO comparator, and a 2.5-µs rising and falling
edge deglitch circuit reduce the likelihood of shutting
the device down due to noise on VIN.
The VBIAS regulator provides internal analog and
digital blocks with a stable supply voltage over
variations in junction temperature and input voltage.
A high quality, low-ESR, ceramic bypass capacitor is
required on the VBIAS pin. X7R or X5R grade
dielectrics are recommended because their values
are more stable over temperature. The bypass
capacitor must be placed close to the VBIAS pin and
returned to AGND.
SLOW-START/ENABLE (SS/ENA)
The slow-start/enable pin provides two functions.
First, the pin acts as an enable (shutdown) control by
keeping the device turned off until the voltage
exceeds the start threshold voltage of approximately
1.2 V. When SS/ENA exceeds the enable threshold,
device start-up begins. The reference voltage fed to
the error amplifier is linearly ramped up from 0 V to
0.891 V in 3.35 ms. Similarly, the converter output
voltage reaches regulation in approximately 3.35 ms.
Voltage hysteresis and a 2.5-µs falling edge deglitch
circuit reduce the likelihood of triggering the enable
due to noise.
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with
a low-value capacitor connected between SS/ENA
and AGND.
External loading on VBIAS is allowed, with the
caution that internal circuits require a minimum
VBIAS of 2.70 V, and external loads on VBIAS with
ac or digital switching noise may degrade
performance. The VBIAS pin may be useful as a
reference voltage for external circuits.
VOLTAGE REFERENCE
The voltage reference system produces a precise
Vref signal by scaling the output of a temperature
stable bandgap circuit. During manufacture, the
bandgap and scaling circuits are trimmed to produce
0.891 V at the output of the error amplifier, with the
amplifier connected as a voltage follower. The trim
procedure adds to the high precision regulation of
the TPS54610, because it cancels offset errors in the
scale and error amplifier circuits.
OSCILLATOR AND PWM RAMP
Adding a capacitor to the SS/ENA pin has two
effects on start-up. First, a delay occurs between
release of the SS/ENA pin and start-up of the output.
The delay is proportional to the slow-start capacitor
value and lasts until the SS/ENA pin reaches the
enable
threshold.
The
start-up
delay
is
approximately:
1.2 V
t +C
d
(SS)
5 mA
(2)
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the SYNC pin as
a static digital input. If a different frequency of
operation is required for the application, the oscillator
frequency can be externally adjusted from 280 to
700 kHz by connecting a resistor between the RT pin
and AGND and floating the SYNC pin. The switching
frequency is approximated by the following equation,
where R is the resistance from RT to AGND:
Switching Frequency + 100 kW 500 [kHz]
R
(4)
Second, as the output becomes active, a brief
ramp-up at the internal slow-start rate may be
observed before the externally set slow-start rate
takes control and the output rises at a rate
proportional to the slow-start capacitor. The
slow-start time set by the capacitor is approximately:
0.7 V
t
+C
(SS)
(SS)
5 mA
(3)
External synchronization of the PWM ramp is
possible over the frequency range of 330 kHz to 700
kHz by driving a synchronization signal into SYNC
and connecting a resistor from RT to AGND. Choose
a resistor between the RT and AGND, which sets the
free running frequency to 80% of the synchronization
signal. The following table summarizes the frequency
selection configurations:
The actual slow-start time is likely to be less than the
above approximation due to the brief ramp-up at the
internal rate.
Submit Documentation Feedback
15
TPS54610-Q1
www.ti.com
SLVS726 – JANUARY 2007
SWITCHING
FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz to 700 kHz
Float
R = 180 kΩ to 68 kΩ
Externally synchronized frequency
Synchronization signal
R = RT value for 80% of external
synchronization frequency
ERROR AMPLIFIER
The high-performance, wide-bandwidth, voltage-error
amplifier sets the TPS54610 apart from most dc/dc
converters. The user is given the flexibility to use a
wide range of output L and C filter components to
suit the particular application needs. Type 2 or type 3
compensation can be employed using external
compensation components.
PWM CONTROL
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM
control logic. Referring to the internal block diagram,
the control logic includes the PWM comparator, OR
gate, PWM latch, and portions of the adaptive
dead-time and control logic block. During
steady-state operation below the current limit
threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch.
Once the PWM latch is reset, the low-side FET
remains on for a minimum duration set by the
oscillator pulse width. During this period, the PWM
ramp discharges rapidly to its valley voltage. When
the ramp begins to charge back up, the low-side FET
turns off and high-side FET turns on. As the PWM
ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the
low-side FET. The low-side FET remains on until the
next oscillator pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or
above the PWM peak voltage. If the error amplifier is
high, the PWM latch is never reset, and the high-side
FET remains on until the oscillator pulse signals the
control logic to turn the high-side FET off and the
low-side FET on. The device operates at its
maximum duty cycle until the output voltage rises to
the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the
error amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn
16
on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM
comparator to change states. The TPS54610 is
capable of sinking current continuously until the
output reaches the regulation set-point.
If the current limit comparator trips for longer than
100 ns, the PWM latch resets before the PWM ramp
exceeds the error amplifier output. The high-side
FET turns off and low-side FET turns on to decrease
the energy in the output inductor and consequently
the output current. This process is repeated each
cycle in which the current limit comparator is tripped.
DEAD-TIME CONTROL AND MOSFET
DRIVERS
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power
MOSFETs during the switching transitions by actively
controlling the turnon times of the MOSFET drivers.
The high-side driver does not turn on until the
voltage at the gate of the low-side FET is below 2 V.
While the low-side driver does not turn on until the
voltage at the gate of the high-side MOSFET is
below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive
the power MOSFETs gates. The low-side driver is
supplied from VIN, while the high-side drive is
supplied from the BOOT pin. A bootstrap circuit uses
an external BOOT capacitor and an internal 2.5-Ω
bootstrap switch connected between the VIN and
BOOT pins. The integrated bootstrap switch
improves drive efficiency and reduces external
component count.
OVERCURRENT PROTECTION
The cycle-by-cycle current limiting is achieved by
sensing the current flowing through the high-side
MOSFET and comparing this signal to a preset
overcurrent threshold. The high side MOSFET is
turned off within 200 ns of reaching the current limit
threshold. A 100-ns leading edge blanking circuit
prevents current limit false tripping. Current limit
detection occurs only when current flows from VIN to
PH when sourcing current to the output filter. Load
protection during current sink operation is provided
by thermal shutdown.
Submit Documentation Feedback
TPS54610-Q1
www.ti.com
SLVS726 – JANUARY 2007
THERMAL SHUTDOWN
POWER GOOD (PWRGD)
The device uses the thermal shutdown to turn off the
power MOSFETs and disable the controller if the
junction temperature exceeds 150°C. The device is
released from shutdown automatically when the
junction temperature decreases to 10°C below the
thermal shutdown trip point, and starts up under
control of the slow-start circuit.
The power-good circuit monitors for under-voltage
conditions on VSENSE. If the voltage on VSENSE is
10% below the reference voltage, the open-drain
PWRGD output is pulled low. PWRGD is also pulled
low if VIN is less than the UVLO threshold or
SS/ENA is low, or a thermal shutdown occurs. When
VIN≥ UVLO threshold, SS/ENA ≥ enable threshold,
and VSENSE > 90% of Vref, the open-drain output of
the PWRGD pin is high. A hysteresis voltage equal
to 3% of Vref and a 35 µs falling edge deglitch circuit
prevent-tripping of the power-good comparator due
to high-frequency noise.
Thermal shutdown provides protection when an
overload condition is sustained for several
milliseconds. With a persistent fault condition, the
device cycles continuously; starting up by control of
the soft-start circuit, heating up due to the fault
condition, and then shutting down upon reaching the
thermal shutdown trip point. This sequence repeats
until the fault condition is removed.
Submit Documentation Feedback
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jan-2012
PACKAGING INFORMATION
Orderable Device
TPS54610QPWPRG4Q1
Status
(1)
ACTIVE
Package Type Package
Drawing
HTSSOP
PWP
Pins
Package Qty
28
2000
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CU NIPDAU Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54610-Q1 :
• Catalog: TPS54610
• Enhanced Product: TPS54610-EP
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jan-2012
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
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