TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com WIDE-INPUT-RANGE NONSYNCHRONOUS VOLTAGE-MODE CONTROLLER Check for Samples: TPS40200-Q1 FEATURES 1 • • • • • • • • • • • • • DESCRIPTION Qualified for Automotive Applications Input Voltage Range 4.5 V to 52 V Output Voltage (700 mV to 90% VIN) 200-mA Internal P-FET Driver Voltage Feed-Forward Compensation Undervoltage Lockout (UVLO) Programmable Fixed-Frequency (35-kHz to 500-kHz) Operation Programmable Short-Circuit Protection Hiccup Overcurrent Fault Recovery Programmable Closed Loop Soft Start 700-mV 1% Reference Voltage External Synchronization Small 8-Pin SOIC (D) Package The TPS40200 is a flexible nonsynchronous controller with a built-in 200-mA driver for P-channel FETs. The circuit operates with inputs up to 52 V, with a power-saving feature that turns off driver current once the external FET has been fully turned on. This feature extends the flexibility of the device, allowing it to operate with an input voltage up to 52 V without dissipating excessive power. The circuit operates with voltage-mode feedback and has feed-forward input-voltage compensation that responds instantly to input voltage change. The integral 700-mV reference is trimmed to 2%, providing the means to accurately control low voltages. The TPS40200 is available in an 8-pin SOIC and supports many of the features of more complex controllers. Clock frequency, soft start, and overcurrent limit are each easily programmed by a single, external component. The part has undervoltage lockout (UVLO) and can be easily synchronized to other controllers or a system clock to satisfy sequencing and/or noise-reduction requirements. APPLICATIONS • • • • • Automotive Controls Distributed Power Systems DSL/Cable Modems Scanners Telecom Major sections in this data sheet include: • Specifications • General Information • Example Applications • Design References TYPICAL APPLICATION 100 VIN R5 C3 RSENSE 2 SS ISNS 7 C5 3 COMP GDRV 6 4 FB Q1 L1 GND 5 VOUT C2 D1 R4 R1 Efficiency - % TPS40200 1 RC VDD 8 C4 R3 VIN = 8 V VIN = 12 V VIN = 16 V 90 C1 80 70 60 R2 C6 VOUT = 5 V 50 0 Figure 1. 12-V to 5-V Buck Converter With 94% Efficiency 0.5 1 1.5 2 Load Current - A 2.5 3 Figure 2. Typical Efficiency of Application Circuit 1 (Described in Application 1) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. ORDERING INFORMATION (1) TA OUTPUT VOLTAGE PACKAGE (2) PART NUMBER MEDIUM QUANTITY –40°C to 125°C Adjustable Plastic small outline (D) TPS40200QDRQ1 Tape and reel 2500/Reel (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Electrostatic Discharge (ESD) Protection MAX UNIT Human-Body Model (HBM) MIN 1000 V Charged-Device Model (CDM) 1500 V 100 V Machine Model (MM) Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) TPS40200 VDD, ISNS Input voltage range Output voltage range Tstg UNIT 52 RC, FB –0.3 to 5.5 SS –0.3 to 9.0 COMP –0.3 to 9.0 GDRV (VIN – 10) to VIN Storage temperature range Lead temperature 1,6 mm (1/16 in) from case for 10 s V V –55 to 150 °C 260 °C Recommended Operating Conditions MIN MAX UNIT VDD Input voltage 4.5 52 V TA Operating temperature –40 125 °C TYP UNIT 49 °C/W Thermal Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER θJC (1) 2 Thermal resistance, junction to case (1) TI uses test boards designed to JESD 51-3 and JESD 51-7 for thermal-impedance measurements. The parameters outlined in these standards are also used to set up thermal models. TI uses the thermal-model program ThermCAL, a finite-difference thermal-modeling tool. Using this test procedure, the junction-to-case thermal resistance of this part is 49°C/W. Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Electrical Characteristics –40°C < TA < 125°C, VDD = 12 V, fOSC = 100 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage Reference COMP = FB, TA = 25°C VFB Feedback voltage 4.5 V < VDD < 52 V 689 696 702 TA = 25°C 686 696 703 –40°C < TA < 125°C 676 696 712 mV Gate Driver Isrc Gate driver pullup current 125 300 mA Isnk Gate driver pulldown current 200 300 mA VGATE Gate driver output voltage 5.6 8 10 V 1.5 3.0 mA 4.25 4.55 V VGATE = (VDD – VGDRV), 12 V < VDD < 52 V Quiescent Current Iqq Device quiescent current fOSC = 300 kHz, Driver not switching, 4.5 V < VDD < 52 V Undervoltage Lockout (UVLO) VUVLO(on) Turn-on threshold VUVLO(off) Turn-off threshold –40°C < TA < 125°C 3.8 4.05 VUVLO(HYST) Hysteresis V 110 200 275 mV 65 105 170 kΩ Soft Start RSS(chg) Internal soft-start pullup resistance RSS(dchg) Internal soft-start pulldown resistance 190 305 485 kΩ VSSRST Soft-start reset threshold 100 150 200 mV 50 100 140 mV 2 % 200 mV Overcurrent Protection VILIM Overcurrent threshold OCDF Overcurrent duty cycle VILIM(rst) Overcurrent reset threshold 4.5 V < VDD < 52 V –40°C < TA < 125°C Note 1 100 150 Oscillator Oscillator frequency range fOSC Oscillator frequency Frequency line regulation VRMP Ramp amplitude Note 35 RRC = 200 kΩ, CRC = 470 pF 85 100 500 118 RRC = 68.1 kΩ, CRC = 470 pF 210 300 345 12 V < VDD < 52 V -9 0 4.5 V < VDD < 12 V –21 0 4.5 V < VDD < 52 V VDD/10 kHz % V Pulse-Width Modulator tMIN Minimum controllable pulse width DMAX Maximum duty cycle KPWM Modulator and power-stage dc gain VDD = 12 V 200 540 VDD = 30 V 100 200 ns Fosc = 100 kHz, CL = 470 pF 93 95 Fosc = 300 kHz, CL = 470 pF 90 93 8 10 12 V/V 100 250 nA % Error Amplifier IIB Input bias current AOL Open loop gain Note 60 80 dB GBWP Unity gain bandwidth Note 1.5 3 MHz ICOMP(src) Output source current VFB = 0.6 V, COMP = 1 V 100 250 μA ICOMP(snk) Output sink current VFB = 1.2 V, COMP = 1 V 1.0 2.5 mA Copyright © 2006–2011, Texas Instruments Incorporated 3 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com DEVICE INFORMATION TPS40200 COMP 3 FB 4 – E/A and SS Reference 8 VDD SS 2 + GDRV voltage swing limited to (VIN – 8 V) + 700 mV Soft-Start and Overcurrent PWM Logic ISNS 7 Driver 6 GDRV Enable E/A 5 GND OSC RC 1 UVLO Figure 3. Functional Block Diagram D PACKAGE (TOP VIEW) RC SS COMP FB 1 8 2 7 3 6 4 5 VDD ISNS GDRV GND Figure 4. Device Pinout TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION RC 1 I Switching frequency setting RC network. Connect capacitor from RC pin to GND pin and resistor from VIN pin to RC pin. The device may be synchronized to an external clock by connecting an open-drain output to this pin and pulling it to GND. The pulse width for synchronization should not be excessive (see General Information). SS 2 I Soft-start programming. Connect capacitor from SS to GND to program soft start time. Pulling this pin below 150 mV causes the output switching to stop, placing the device in a shutdown state. The pin also functions as a restart timer for overcurrent events. COMP 3 O Error amplifier output. Connect control loop compensation network from COMP to FB. FB 4 I Error amplifier inverting input. Connect feedback resistor network center tap to this pin. GND 5 GDRV 6 O Driver output for external P-channel MOSFET ISNS 7 I Current-sense comparator input. Connect a current sense resistor between ISNS and VDD in order to set desired overcurrent threshold. VDD 8 I System input voltage. Connect local bypass capacitor from VDD to GND. 4 Device ground Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS QUIESCENT CURRENT vs TEMPERATURE QUIESCENT CURRENT vs VDD 3 1.66 1.65 2.5 1.64 2 1.62 IDD - mA IDD - mA 1.63 1.61 1.6 1.5 1 1.59 1.58 VDD = 12 V 0.5 1.57 1.56 -50 0 -25 0 25 50 75 100 5 125 10 15 20 25 30 35 VDD - V 40 45 50 Figure 5. Figure 6. SOFT-START THRESHOLD vs TEMPERATURE UVLO TURN ON AND TURN OFF vs TEMPERATURE 156.5 4.3 156 4.25 UVLO Turn On - V Reset Threshold - mV Temp - °C 155.5 155 154.5 154 VDD = 12 V 153.5 -50 -25 55 Turn On 4.2 4.15 4.1 Turn Off 4.05 4 0 25 50 75 Temp - °C Figure 7. Copyright © 2006–2011, Texas Instruments Incorporated 100 125 -50 -25 0 25 50 Temp - °C 75 100 125 Figure 8. 5 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) OSCILLATOR FREQUENCY vs TEMPERATURE CURRENT-LIMIT THRESHOLD vs TEMPERATURE 103 98 96 102.5 VDD = 4.5 V 102 R = 202 kW C = 470 pF 92 ILIM threshold - mV Frequency (kHz) 94 90 88 VDD = 12 V 86 84 80 -50 -25 0 25 50 75 100 101 VDD = 12 V 100.5 100 VDD = 52 V 82 101.5 99.5 -50 125 -25 0 Temp (°C) 50 75 100 125 Temp - °C Figure 9. Figure 10. OSCILLATOR FREQUENCY vs VDD POWER-STAGE GAIN vs VDD 275 21.00 R = 68.1 kW C = 470 pF TJ = 25°C 270 265 TJ = 25°C 20.50 260 255 Gain - dB Oscillator Frequency (kHz) 25 250 245 20.00 240 235 19.50 230 225 220 19.00 5 10 15 20 25 30 35 VDD (V) Figure 11. 6 40 45 50 55 5 10 15 20 25 30 35 VDD - V 40 45 50 55 Figure 12. Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) POWER-STAGE GAIN vs TEMPERATURE POWER-STAGE GAIN vs TEMPERATURE 20.50 20.50 20.30 20.45 VDD = 24 V VDD = 4.5 V 20.40 VDD = 12 V 19.90 Gain - dB Gain - dB 20.10 19.70 20.35 VDD = 52 V 20.30 19.50 20.25 -50 -25 0 25 50 75 100 125 -50 -25 0 Temp - °C MODULATOR RAMP AMPLITUDE vs TEMPERATURE MODULATOR RAMP AMPLITUDE vs TEMPERATURE VDD = 24 V Vramp - V 2.2 Vramp - V 100 Figure 14. 2.6 2 1.8 1.6 VDD = 12 V 1.2 1 -50 75 Figure 13. 3 1.4 50 -25 0 25 50 125 Temp °C 2.8 2.4 25 75 Temp - °C Figure 15. Copyright © 2006–2011, Texas Instruments Incorporated 100 125 6 5.8 5.6 5.4 5.2 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 VDD = 52 V VDD = 36 V -50 -25 0 25 50 75 100 125 Temp - °C Figure 16. 7 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) MODULATOR RAMP AMPLITUDE vs VDD FEEDBACK AMPLIFIER INPUT BIAS CURRENT vs TEMPERATURE 160 6 TJ = 25°C 140 5 120 4 IIB - nA VRAMP - V 100 3 80 60 2 40 1 20 0 0 5 10 15 20 25 30 35 VDD - V 40 45 50 55 -50 25 50 75 Figure 17. Figure 18. COMP SOURCE CURRENT vs TEMPERATURE COMP SINK CURRENT vs TEMPERATURE 100 125 100 125 3.5 3 Output Current - mA 250 Output Current - mA 0 Temp - °C 300 200 150 100 50 2.5 2 1.5 1 0.5 0 0 -50 -25 0 25 50 Temp - °C Figure 19. 8 -25 75 100 125 -50 -25 0 25 50 75 Temp - °C Figure 20. Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) GATE DRIVE VOLTAGE vs TEMPERATURE GATE DRIVE VOLTAGE vs VIN 8.4 8 VDD = 12 V 7.8 7.6 VGATE - V VJ = 25°C 8.2 8 7.4 7.8 7.2 7.6 7 7.4 6.8 7.2 6.6 7 6.4 Temp - °C 30 35 VDD - V Figure 21. Figure 22. REFERENCE VOLTAGE vs TEMPERATURE REFERENCE VOLTAGE vs TEMPERATURE -25 0 25 50 75 100 5 125 720 720 718 718 716 716 714 714 712 VFB - mV VFB - mV -50 VDD = 24 V 710 708 706 10 15 20 25 40 45 50 55 712 710 VDD = 4.5 V 708 706 VDD = 50 V 704 704 702 702 700 VDD = 12 V 700 -50 -25 0 25 50 75 Temp - °C Figure 23. Copyright © 2006–2011, Texas Instruments Incorporated 100 125 -50 -25 0 25 50 75 100 125 Temp - °C Figure 24. 9 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) MINIMUM CONTROLLABLE PULSE WIDTH vs FREQUENCY MAXIMUM DUTY CYCLE vs INPUT VOLTAGE 700 100 600 95 Maximum Duty Cycle (%) VDD = 4.5 V Pulse Width - ns 500 400 300 VDD = 24 V VDD = 12 V 200 100 VDD = 36 V 200 300 Frequency - kHz Figure 25. 10 80 75 fOSC (kHz) 500 200 100 50 70 60 0 100 85 65 VDD = 52 V 0 90 400 500 0 10 20 30 40 50 Input Voltage (V) Figure 26. Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com GENERAL INFORMATION Overview The TPS40200 is a nonsynchronous controller with a built-in 200-mA driver designed to drive high-speed P-channel FETs up to 500 kHz. Its small size combined with complete functionality makes the part both versatile and easy to use. The controller uses a low-value current-sensing resistor in series with the input voltage and the power FET’s source connection to detect switching current. When the voltage drop across this resistor exceeds 100 mV, the part enters a hiccup fault mode at approximately 2% of the operating frequency. The part uses voltage feedback to an error amplifier that is biased by a precision 700-mV reference. Feed-forward compensation from the input keeps the PWM gain constant over the full input voltage range, eliminating the need to change frequency compensation for different input voltages. The part also incorporates a soft-start feature, during which the output follows a slowly rising soft-start voltage, preventing output-voltage overshoot. Programming the Operating Frequency The operating frequency of the controller is determined by an external resistor RRC that is connected from the RC pin to VDD and a capacitor attached from the RC pin to ground. This connection and the two oscillator comparators inside the IC are shown in Figure 27. The oscillator frequency can be calculated from the following equation: f SW = 1 R RC ´ C RC ´ 0.105 Where: fSW = clock frequency RRC = timing resistor value in Ω CRC = timing capacitor value in F RRC must be kept large enough that the current through it does not exceed 750 μA when the internal switch (shown in Figure 27) is discharging the timing capacitor. This condition may be expressed by Equation 1: VIN £ 750 mA R RC (1) Synchronizing the Oscillator Figure 27 shows the functional diagram of the TPS40200 oscillator. When synchronizing the oscillator to an external clock, the RC pin must be pulled below 150 mV for 20 ns or more. The external clock frequency must be higher than the free-running frequency of the converter as well. When synchronizing the controller, if the RC pin is held low for an excessive amount of time, erratic operation may occur. The maximum amount of time that the RC pin should be held low is 50% of a nominal output pulse, or 10% of the period of the synchronization frequency. Under circumstances where the input voltage is high and the duty cycle is less than 50%, a Schottky diode connected from the RC pin to an external clock may be used to synchronize the oscillator. The cathode of the diode is connected to the RC pin. The trip point of the oscillator is set by an internal voltage divider to be 1/10 of the input voltage. The clock signal must have an amplitude higher than this trip point. When the clock goes low, it allows the reset current to restart the RC ramp, synchronizing the oscillator to the external clock. This provides a simple, single-component method for clock synchronization. Copyright © 2006–2011, Texas Instruments Incorporated 11 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com VDD VIN 8 TPS40200 + CLK RRC S Q RC RC R Q 1 Ext. Frequency Synchronization (optional) + CRC + GND 150mV 5 Figure 27. Oscillator Functional Diagram VDD VIN Amplitde > VIN ¸ 10 Duty cycle < 50% 8 TPS40200 + CLK RRC S Q RC RC R Q 1 Frequency > Controller Frequency + CRC + GND 150mV 5 Figure 28. Diode Connected Synchronization 12 Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Current-Limit Resistor Selection As shown in Figure 31, a resistor in series with the power MOSFET sets the overcurrent protection level. Use a low-inductance resistor to avoid problems with ringing signals and nuisance tripping. When the FET is on and the controller senses 100 mV or more drop from the VDD pin to the ISNS pin, an overcurrent condition is declared. When this happens, the FET is turned off and, as shown in Figure 30, the soft-start capacitor is discharged. When the soft-start capacitor reaches a level below 150 mV, the converter clears the overcurrent condition flag and attempts to restart. If the condition that caused the overcurrent event to occur is still present on the output of the converter (see Figure 29), another overcurrent condition is declared and the process repeats indefinitely. Figure 29 shows the soft-start capacitor voltage during an extended output fault condition. The overall duty cycle of current conduction during a persistent fault is approximately 2%. Figure 29. Typical Soft-Start Capacitor and VOUT During Overcurrent VS-S TPS40200 VIN 8 + 100 mV 100 kW + ISNS Fault 7 S Q R Q SS 2 + Reset Fault Latched Fault 300 kW + 300 mV EAMP SS Ref Enable EAMP + 150 mV GND 5 Figure 30. Current-Limit Reset Copyright © 2006–2011, Texas Instruments Incorporated 13 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com If necessary, a small R-C filter can be added to the current sensing network to reduce nuisance tripping due to noise pickup. This filter can also be used to trim the overcurrent trip point to a higher level with the addition of a single resistor (see Figure 31). The nominal overcurrent trip point using the circuit of Figure 31 is described as: IOC = VILIM R F1 + R F2 ´ R ILIM R F2 Where: IOC = overcurrent trip point, peak current in the inductor VILIM = overcurrent threshold voltage for the TPS40200, typically 100 mV RILIM = value of the current sense resistor in Ω RF1 and RF2 = values of the scaling resistors in Ω The value of the capacitor is determined by the nominal pulse width of the converter and the values of the scaling resistors RF1 and RF2. It is best not to have the time constant of the filter longer than the nominal pulse width of the converter, otherwise a substantial increase in the overcurrent trip point occurs. Using this constraint, the capacitor value may be bounded by the following: Cf £ VO R ´ R f2 ÷ f1 R VIN ´ f SW f1 + R f2 Where: Cf = value of the current limit filter capacitor in F VO = output voltage of the converter VIN = input voltage to the converter fSW = converter switching frequency Rf1 and Rf2 = values of the scaling resistors in Ω VIN RILIM RF1 TPS40200 VDD 8 CF RF2 ISNS 7 GDRV 6 NOTE: The current-limit resistor and its associated circuitry can be eliminated, and pins 7 and 8 shorted. However, the result of this may result in damage to the part or PCB in the event of an overcurrent event. Figure 31. Current-Limit Adjustment 14 Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com MOSFET Gate Drive The output driver sinking current is approximately 200 mA and is designed to drive P-channel power FETs. When the driver pulls the gate charge of the FET it is controlling to –8 V, the drive current folds back to a low level so that high power dissipation only occurs during the turn-on period of the FET. This feature is particularly valuable when turning on a FET at high input voltages, where leaving the gate drive current on would otherwise cause unacceptable power dissipation. Undervoltage Lockout (UVLO) Protection UVLO protection ensures proper start-up of the device only when the input voltage has exceeded minimum operating voltage. Undervoltage protection incorporates hysteresis that eliminates hiccup starting in cases where input supply impedance is high. VDD 8 TPS40200 545k + RUN 200K + 1.3V 36K GND 5 Figure 32. Undervoltage Lockout Undervoltage protection ensures proper start-up of the device only when the input voltage has exceeded minimum operating voltage. The UVLO level is measured at the VDD pin with respect to GND. Start-up voltage is typically 4.3 V with approximately 200 mV of hysteresis. The part shuts off at a nominal 4.1 V. As shown in Figure 32, when the input VDD voltage rises to 4.3 V, the 1.3-V comparator threshold voltage is exceeded and a RUN signal occurs. Feedback from the output closes the switch and shunts the 200-kΩ resistor, so that an approximately 200-mV lower voltage, or 4.1 V, is required before the part shuts down. Copyright © 2006–2011, Texas Instruments Incorporated 15 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Programming the Soft-Start Time An external capacitor (CSS) connected from the SS pin to ground controls the TPS40200 soft-start interval. An internal charging resistor connected to VDD produces a rising reference voltage that is connected through a 700-mV offset to the reference input of the TPS40200 error amplifier. When the soft-start capacitor voltage (VCSS) is below 150 mV, there is no switching activity. When VCSS rises above the 700-mV offset, the error amplifier starts to follow VSST – 700 mV and uses this rising voltage as a reference. When VCSS reaches 1.4 V, the internal reference takes over, and further increases have no effect. An advantage of initiating a slow start in this fashion is that the controller cannot overshoot, because its output follows a scaled version of the controller's reference voltage. A conceptual drawing of the circuit that produces these results is shown in Figure 33. A consequence of the 700-mV offset is that the controller does not start switching until the VCSS has charged up to 700 mV. The output remains at 0 V during the resulting delay. When VCCS exceeds the 700-mV offset, the TPS40200 output follows the soft-start time constant. Once above 1.4 V, the 700-mV internal reference takes over, and normal operation begins. TPS40200 VSST 105 kW 2 + Css Ideal Diodes Error Amplifier + 700 mV VSST (offset) SS + FB 4 700 mV COMP 3 Figure 33. Soft-Start Circuit The slow-start time should be longer (slower) than the time constant of the output LC filter. This time constraint may be expressed as: t S ³ 2p ´ L O ´ C O (2) The calculation of the soft-start interval is simply the time it takes the RC network to exponentially charge from 0 V to 1.4 V. An internal 105-kΩ charging resistor is connected from the SS pin to VSST. For applications where the voltage is above 8 V, an internal regulator clamps the maximum charging voltage to 8 V. The result of this is a formula for the start up time, as given by: ö æ VSST ÷ t SS = R c ´ CSS ´ ln çç ÷ è VSST - 1.4 ø 16 Where: tSS = required soft-start time in seconds CSS = soft-start capacitor value in F Rc = internal soft-start charging resistor (105 kΩ nominal) VSST = input voltage up to a maximum of 8 V Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Voltage Setting and Modulator Gain Because the input current to the error amplifier is negligible, the feedback impedance can be selected over a wide range. Knowing that the reference voltage is 708 mV, pick a convenient value for R1 and then calculate the value of R2 from the following formula: æ R ö VOUT = 0.708çç1 + 2 ÷÷ R 1ø è (3) Vg L KPWM VOUT d Cout Vc Rload R2 + Vref R1 Figure 34. System Gain Elements The error amplifier has a dc open-loop gain of at least 60 dB with a minimum of a 1.5-MHz gain bandwidth product, which gives the user flexibility with respect to the type of feedback compensation used for the particular application. The gain selected by the user at the crossover frequency is set to provide an overall unity gain for the system. The crossover frequency should be selected so that the error amplifier's open-loop gain is high with respect to the required closed-loop gain. This ensures that the amplifier's response is determined by the passive feedback elements. Copyright © 2006–2011, Texas Instruments Incorporated 17 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com EXAMPLE APPLICATIONS Application 1: Buck Regulator, 8-V to 12-V Input, 3.3-V or 5-V Output at 2.5 A Overview The buck regulator design shown in Figure 35 shows the use of the TPS40200. It delivers 2.5 A at either 3.3 V or 5 V as selected by a single feedback resistor. It achieves approximately 90% efficiency at 3.3 V and 94% at 5 V. A discussion of design tradeoffs and methodology is included to serve as a guide to the successful design of forward converters using the TPS40200. The bill of materials for this application is given in Table 3. The efficiency from boards built from this design is shown in Figure 36 and Figure 37. Gerber files and additional application information are available. + + Notes D3 : Do not populate. SOT 23 Common Cathode Dual Schottky R6 =26.7k for 3.3 Vout, R6 = 16.2k for 5.0 Vout Figure 35. 8-V to 16-V VIN Step-Down Buck Converter 100 100 VIN = 8 V VIN = 12 V VIN = 16 V 90 80 Efficiency - % Efficiency - % 90 70 60 VIN = 8 V VIN = 12 V VIN = 16 V 80 70 60 VOUT = 5 V VOUT = 3.3 V 50 0 0.5 1 1.5 2 Load Current - A 2.5 3 Figure 36. Full-Load Efficiency at 5-V VOUT 18 50 0 0.5 1 1.5 2 Load Current - A 2.5 3 Figure 37. Full-Load Efficiency at 3.3-V VOUT Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Component Selection Table 2. Design Parameters SYMBOL PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VIN Input voltage 8.0 12 16.0 V VOUT Output voltage IOUT at 2.5 A 3.200 3.3 3.400 (1) V Line regulation ~0.2 % VOUT 3.293 3.3 3.307 V Load regulation ~0.2% VOUT 3.293 3.3 3.307 V Output voltage IOUT at 2.5 A 4.85 5.0 5.150 (1) V Line regulation ~0.2% VOUT 4.990 5.0 5.010 V 4.990 5.0 5.010 VOUT Load regulation ~0.2% VOUT VRIPPLE Output ripple voltage At maximum output current VOVER Output overshoot VUNDER Output undershoot IOUT Output current ISCP Short-circuit current trip point FS (1) mV For 2.5-A load transient from 2.5 A to 0.25 A 100 mV For 2.5-A load transient from 0.25 A to 2.5 A 60 mV At nominal input voltage and maximum output current Efficiency V 60 Switching frequency 0.125 2.5 A 3.75 5.00 A 90 % 300 kHz Set-point accuracy is dependent on external resistor tolerance and the IC reference voltage. Line and load regulation values are referenced to the nominal design output voltage. FET Selection Criteria 1. The maximum input voltage for this application is 16 V. Switching the inductor causes overshoot voltages that can equal the input voltage. Because the RDSON of the FET rises with breakdown voltage, select a FET with the lowest breakdown voltage possible. In this case, a 30-V FET was selected. 2. The selection of a power FET’s size requires knowing both the switching losses and dc losses in the application. AC losses are all frequency dependent and directly related to device capacitances and device size. On the other hand, dc losses are inversely related to device size. The result is an optimum where the two types of losses are equal. Because device size is proportional to RDSON, a starting point is to select a device with an RDSON that results in a small loss of power relative to package thermal capability and overall efficiency objectives. 3. In this application, the efficiency target is 90% and the output power 8.25 W. This gives a total power-loss budget of 0.916 W. Total FET losses must be small relative to this number. The dc conduction loss in the FET is given by: PDC = Irms 2 × RDSON The RMS current is given by: 1 2 é æ DIpp ö÷ù 2 2 ú Irms = êD ´ ç IOUT + ê ç 12 ÷ú è ø ë û Copyright © 2006–2011, Texas Instruments Incorporated Where: ΔIpp = ΔV × D × (ts/LI) ΔV = VIN – VOUT – (DCR + RDSON) × IOUT RDSON = FET on-state resistance DCR = inductor dc resistance D = duty cycle tS = reciprocal of the switching frequency 19 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Using the values in this example, the dc power loss is 129 mW. The remaining FET losses are: • PSW – The power dissipated while switching the FET on and off • Pgate – The power dissipated driving the FET's gate capacitance • PCOSS – The power switching the FET's output capacitance The total power dissipated by the FET is the sum of these contributions: PFET = PSW + Pgate + PCOSS + PRDSON The P-channel FET used in this application is a FDC654P with the following characteristics: trise = 13 × 10–9 COSS = 83 × 10–12 tfall = 6 × 10–9 Qg = 9 nC RDSON = 0.1 Ω Vgate = 1.9 V –9 Qgs = 1.0 × 10–9 Qgd = 1.2 × 10 Using these device characteristics and the following formulas, PSW is calculated as: æ ö f f PSW = S ´ çç VIN ´ Ipk ´ t CHON ÷÷ + S VIN ´ Ipk ´ t CHOFF = 10 mW 2 è ø 2 ( t CHON = ) (4) Q ´ RG Q GD ´ R G t CHOFF = GD VIN - VTH and VIN are the switching times for the power FET. Where PGATE = Q G × VGATE × f S = 22 mW (5) 2 PCOSS = C OSS × VIN _ MAX × f S 2 = 2 mW (6) IG = QG × fS = 2.7 mA is the gate current. The sum of the switching losses is 34 mW and is comparable to the 129-mW dc losses. At added expense, a slightly larger FET would be better, because the dc loss would drop and the ac losses would increase, with both moving toward the optimum point of equal losses. 20 Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Rectifier Selection Criteria • Rectifier breakdown voltage The rectifier must withstand the maximum input voltage, which, in this case, is 16 V. To allow for switching transients that can approach the switching voltage, a 30-V rectifier was selected. • Diode size The importance of power losses from the Schottky rectifier (D2) is determined by the duty cycle. For a low duty-cycle application, the rectifier is conducting most of the time, and the current that flows through it times its forward drop can be the largest component of loss in the entire controller. In this application, the duty cycle ranges from 20% to 40%, which, in the worst case, means that the diode is conducting 80% of the time. Where efficiency is of paramount importance, choose a diode with as low a forward drop as possible. In more cost-sensitive applications, size may be reduced to the point of the thermal limitations of the diode package. The device in this application is large relative to the current required by the application. In a more cost-sensitive application, a smaller diode in a less-expensive package could provide a less-efficient but appropriate solution. The device used has the following characteristics: • Vf = 0.3 V at 3 A • Ct = 300 pF (Ct = effective reverse voltage capacitance of the synchronous rectifier, D2) The two components of the losses from the diode D2 are: ( PCOND = Vf × IOUT + ( IRIPPLE × (1 – D) = 653 mW 4 Where: D = the duty cycle IRIPPLE = ripple current IOUT = output current VF = forward voltage PCOND = conduction power loss The switching capacitance of this diode adds an ac loss, given by Equation 7: 1 2 PSW = C × (VIN + Vf ) × f = 6.8 mW 2 (7) This additional loss raises the total loss to 660 mW. At an output voltage of 3.3 V, the application runs at a nominal duty cycle of 27%, and the diode is conducting 72.5% of the time. As the output voltage is moved up to 5 V, the on time increases to 46%, and the diode is conducting only 54% of the time during each clock cycle. This change in duty cycle proportionately reduces the conduction power losses in the diode. This reduction may be expressed as 660(0.54/0.725) = 491 mW, for a savings in power of 660 – 491 = 169 mW. To illustrate the relevance of this power savings, measure the full-load module efficiency for this application at 3.3 V and 5 V. The 5-V output efficiency is 92%, compared to 89% for the 3.3-V design. This difference in efficiency represents a 456-mW reduction in losses between the two conditions. This 169-mW power-loss reduction in the rectifier represents 37% of the difference. [ ] Copyright © 2006–2011, Texas Instruments Incorporated 21 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Inductor Selection Criteria The TPS40200 P-FET driver facilitates switching the power FET at a high frequency. This, in turn, enables the use of smaller less-expensive inductors as illustrated in this 300-kHz application. Ferrite, with its good high-frequency properties, is the material of choice. Several manufacturers provide catalogs with inductor saturation currents, inductance values, and LSRs (internal resistance) for their various-sized ferrites. In this application, the part must deliver a maximum current of 2.5 A. This requires that the output inductor’s saturation current be above 2.5 A plus one-half the ripple current caused during inductor switching. The value of the inductor determines this ripple current. A low value of inductance has a higher ripple current that contributes to ripple voltage across the resistance of the output capacitors. The advantages of a low inductance are a higher transient response, lower DCR, a higher saturation current, and a smaller less-expensive part. Too low an inductor, however, leads to higher peak currents, which ultimately are bounded by the overcurrent limit set to protect the output FET or by output ripple voltage. Fortunately, with low-ESR ceramic capacitors on the output, the resulting ripple voltage for relatively high ripple currents can be small. For example, a single 1-μF 1206-sized 6.3-V ceramic capacitor has an internal resistance of 2 Ω at 1 MHz. For this 2.5-A application, a 10% ripple current of 0.25 A produces a 50-mV ripple voltage. This ripple voltage may be further reduced by additional parallel capacitors. The other bound on inductance is the minimum current at which the controller enters discontinuous conduction. At this point, inductor current is zero. The minimum output current for this application is specified at 0.125 A. This average current is one-half the peak current that must develop during a minimum on time. The conditions for minimum on time are high line and low load. LMAX is calculated using: LMAX = VIN − VOUT × t ON = 32 µH IPEAK Where: VIN = 16 V VOUT = 3.3 V IPEAK = 0.25 A tON = 0.686 μs tON 3. 3 V 1 ´ is given by 300 kHz 16 V The inductor used in the circuit is the closest standard value of 33 μH. This is the maximum inductance that can be used in the converter to deliver the minimum current while maintaining continuous conduction. 22 Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Output Capacitance In order to satisfy the output voltage overshoot and undershoot specifications, there must be enough output capacitance to keep the output voltage within the specified voltage limits during load current steps. In a situation where a full load of 2.5 A within the specified voltage limits is suddenly removed, the output capacitor must absorb energy stored in the output inductor. This condition may be described by realizing that the energy in the stored in the inductor must be suddenly absorbed by the output capacitance. This energy relationship is written as: 1 1 2 2 2 ´ L OIO £ ´ C O VOS - VO 2 2 [ ( )] Where: VOS = allowed over-shoot voltage above the output voltage LO = inductance IO = output current CO = output capacitance VO = output voltage In this application, the worst-case load step is 2.25 A, and the allowed overshoot is 100 mV. With a 33-μH output inductor, this implies an output capacitance of 249 μF for a 3.3-V output and 165 μF for a 5-V output. When the load increases from minimum to full load, the output capacitor must deliver current to the load. The worst case is for a minimum on time that occurs at 16 V in, 3.3 V out, and minimum load. This corresponds to an off time of (1 – 0.2) times the period 3.3 μs and is the worst-case time before the inductor can start supplying current. This situation may be represented by: DVO < DIO ´ t OFFMAX CO Where: ΔVO = undershoot specification of 60 mV ΔIO = load current step tOFFMAX = maximum off time This condition produces a requirement of 100 μF for the output capacitance. The larger of these two requirements becomes the minimum value of output capacitance. The ripple current develops a voltage across the ESR of the output capacitance, so another requirement on this component is that its ESR be small relative to the ripple voltage specification. Switching Frequency The TPS40200 has a built-in 8-V 200-mA P-channel FET-driver output that facilitates using P-channel switching FETs. A clock frequency of 300 kHz was chosen as a switching frequency that represents a compromise between a high frequency that allows the use of smaller capacitors and inductors, but one that is not so high as to cause excessive transistor switching losses. As previously discussed, an optimum frequency can be selected by picking a value where the dc and switching losses are equal. The frequency is set by using the design formula given in the FET Selection Criteria section. RRC ´ CRC = 1 0.105 ´ fSW Where: RRC = timing resistor value in ohms or RRC = 68.1 kΩ CRC = timing capacitor value in F or C5 = 470 pF fSW = desired switching frequency in Hz, which in this case calculates to 297 kHz At a worst case of 16 V, the timing resistor draws about 250 μA, which is well below the 750-μA maximum that the circuit can pull down. Copyright © 2006–2011, Texas Instruments Incorporated 23 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Programming the Overcurrent Threshold Level The current limit in the TSP40200 is triggered by a comparator with a 100-mV offset whose inputs are connected across a current-sense resistor between VCC and the source of the high-side switching FET. When current in this resistor develops more than 100 mV, the comparator trips and terminates the output gate drive. In this application, the current-limit resistor is set by the peak output stage current, which consists of the maximum load current plus one-half the ripple current. In this case, 2.5 + 0.125 = 2.625 A. To accommodate tolerances, a 25% margin is added, giving a 3.25-A peak current. Using the equation in Figure 38 yields a value for RILIM of 0.30 Ω. Current sensing in a switching environment requires attention to both circuit board traces and noise pickup. In the design shown, a small RC filter has been added to the circuit to prevent switching noise from tripping the current-sense comparator. The requirements of this filter are board dependent but, with the layout used in this application, no spurious overcurrent was observed. VIN RILIM RF1 TPS40200 VDD 8 CF RF2 ISNS 7 GDRV 6 ILIM = 0. 1 R ILIM Figure 38. Overcurrent Trip Circuit for RF2 Open 24 Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Soft-Start Capacitor The soft-start interval is given (in pF) by: C SS = t SS æ VSST ö ÷ R ´ ln çç ÷ è VSST - 1.4 ø ´ 10 3 Where: R = internal 105-kΩ charging resistor VCC = input voltage up to 8 V, where the charging voltage is internally clamped to 8 V maximum VOS = 700 mV, and (because the input voltage is 12 V) VSST = 8 V The oscilloscope picture (see Figure 39) shows the expected delay at the output (middle trace) until the soft-start node (bottom trace) reaches 700 mV. At this point, the output rises following the exponential rise of the soft-start capacitor voltage until the soft-start capacitor reaches 1.4 V and the internal 700-mV reference takes over. This total time is approximately 1 ms, which agrees with the calculated value of 0.95 ms when the soft-start capacitance is 0.047 μF. A. Channel 1 is the output voltage rising to 3.3 V. B. Channel 2 is the soft-start pin. Figure 39. Soft Start Showing Output Delay and Controlled Rise to Programmed Output Voltage Copyright © 2006–2011, Texas Instruments Incorporated 25 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Frequency Compensation The four elements that determine the system overall response are discussed in this section. The gain of the error amplifier (KEA) is the first of these elements. Its output develops a control voltage that is the input to the PWM. The TPS40200 has a unique modulator that scales the peak-to-peak amplitude of the PWM ramp to be 0.1 times the value of the input voltage. Because modulator gain is given by VIN divided by VRAMP, the modulator gain is 10 and is constant at 10 (20 dB) over the entire specified input-voltage range. The last two elements that affect system gain are the transfer characteristic of the output LC filter and the feedback network from the output to the input to the error amplifier. These four elements may be expressed by the following equation that represents the system transfer function as shown in Figure 40. TV(S) = KFB × KEA(S) × KPWM × XLC(S) Where: KFB = output voltage setting divider KEA = error amplifier feedback KPWM = modulator gain XLC = filter transfer function vg Vref + KEA - vc KPWM d XLC vo Tv(s) KFB Figure 40. Control Loop 26 Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Figure 41 shows the feedback network used in this application. This is a type-2 compensation network, which gives a combination of good transient response and phase boost for good stability. This type of compensation has a pole at the origin, causing a –20-dB/decade (–1) slope, followed by a zero that causes a region of flat gain, followed by a final pole that returns the gain slope to –1. The Bode plot in Figure 42 shows the effect of these poles and zeros. The procedure for setting up the compensation network is: 1. Determine the break frequency of the output capacitor. 2. Select a zero frequency well below this break frequency. 3. From the gain bandwidth of the error amplifier, select a crossover frequency at which the amplifier gain is large relative to expected closed-loop gain. 4. Select a second zero well above the crossover frequency that returns the gain slope to a –1 slope. 5. Calculate the required gain for the amplifier at crossover. Be prepared to iterate this procedure to optimize the pole and zero locations as needed. C7 C8 R8 R10 + R6 VREF Figure 41. Error Amplifier Feedback Elements The frequency response of this converter is largely determined by two poles that arise from the LC output filter and a higher-frequency zero caused by the ESR of the output capacitance. The poles from the output filter cause a 40-dB/decade rolloff with a phase shift approaching 180°, followed by the output capacitor zero that reduces the roll off to –20 dB and gives a phase boost back toward 90°. In other nomenclature, this is a –2 slope followed by a –1 slope. The two zeros in the compensation network act to cancel the double pole from the output filter. The compensation network’s two poles produce a region in which the error amplifier is flat and can be set to a gain such that the overall gain of the system is 0 dB. This region is set so that it brackets the system crossover frequency. Gain - dB P1 Error Amplifier Type 2 Compensation Slope = -1 z1 p2 A V2 f1 A V1 f2 Freq. Figure 42. Error Amplifier Bode Plot Copyright © 2006–2011, Texas Instruments Incorporated 27 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com In order to properly compensate this system, it is necessary to know the frequencies of its poles and zeros. Step 1 The break frequency of the output capacitor is given by: Fesr = 1 2pR esr C Where: C = the output capacitor RESR = the ESR of the capacitors Because of the ESR of the output capacitor, this output filter has a single-pole response above the 1.8-kHz break frequency of the output capacitor and its ESR. This simplifies compensation since the system becomes essentially a single-pole system. Step 2 The first zero is place well below the 1.8-kHz break frequency of the output capacitor and its ESR. Phase boost from this zero is shown in Figure 44. fZ1 = 1 2pR 8C8 Where: R8 = 300 kΩ C8 = 1500 pF FZ1 = 354 Hz Step 3 From a minimum gain bandwidth product of 1.5 MHz, and knowing it has a 20-dB/decade rolloff, the open-loop gain of the error amplifier is 33 dB at 35 kHz. This approximate frequency is chosen for a crossover frequency to keep the amplifier gain contribution to the overall system gain small, as well as following the convention of placng the crossover frequency between 1/6 to 1/10 the 300 kHz switching frequency. Step 4 The second pole is placed well above the 35-kHz crossover frequency. fP2 = 28 1 × (C7 + C8) 2π × C 7 × C 8 × R 8 Where: R8 = 300 kΩ C7 = 10 pF C8 = 1500 pF fP3 = 53 kHz Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Step 5 Calculate the gain elements in the system to determine the gain required by the error amplifier to make the overall gain 0 dB at 35 kHz: TV (S ) = K FB ´ K EA (S)´ K PWM ´ X LC (S) Where: KFB is the output voltage setting divider KEA is the error amplifier feedback KPWM is the modulator gain XLC is the filter transfer function With reference to Figure 43, the output filter's transfer characteristic XLC(S) can be estimated by the following: L RSW VIN D VSW VOUT 1-D RSR COUT RLOAD Figure 43. Output Filter Analysis X LC (S) = Z OUT (S) Z OUT (S) + Z L (S) + R SW ´ D + R SR ´ (1 - D) Where: ZOUT is the parallel combination of output capacitor(s) and the load RSW is the RDS(on) of the switching FET plus the current-sense resistor RSR is the resistance of the synchronous rectifier D is the duty cycle estimated as 3.3 / 12 = 0.27 To evaluate XLC(S) at 35 kHz use the following: • ZOUT(S) at 35 kHz, which is dominated by the output capacitorr's ESR; estimated to be 400 mΩ • ZL(S) at 35 KHz is 7.25 Ω • RSW = 0.95 mΩ, including the RLIM resistance • RSR = 100 mΩ Using these numbers, XLC(S) = 0.04 or -27.9 dB. The feedback network has a gain to the error amplifier given by: K fb = R 10 R6 Where for 3.3 VOUT, R6 = 26.7 kΩ Using the values in this application, Kfb = 11.4 dB. The modulator has a gain of 10 that is flat to well beyond 35 kHz, so KPWM = 20 dB. To acheive 0 dB overall gain, the amplifier and feedback gain must be set to 7.9 dB (20 dB - 27.9 dB) The amplifier gain, including the feedback gain, Kfb, can be approximated by this expression: Copyright © 2006–2011, Texas Instruments Incorporated 29 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 VOUT (S ) = VIN www.ti.com A VOL R10 R10 1+ + ´ (1 + A VOL ) R 8 ZFS Where: ZFS is the parallel combination of C7 in parallel with the sum of R8 and the impedance of C8 AVOL is the open-loop gain of the error amplifier at 35 kHz, which is 44.6 or 33 dB Figure 44 shows the result of the compensation. The crossover frequency is 35 kHz, and the phase margin is 45°. The response of the system is dominated by the ESR of the output capacitor and is exploited to produce an essentially single-pole system with simple compensation. 50 180 40 160 30 140 20 Gain 100 0 -10 80 Phase 60 -20 40 -30 20 -40 -50 0.1 Phase - Degrees 120 Gain 10 1 10 100 0 1000 Crossover Frequency - kHz Figure 44. Overall System Gain and Phase Response Figure 44 also shows the phase boost that gives the system a crossover phase margin of 47°. The bill of materials for this application is shown in Table 3. Gerber PCB layout files and additional application information are available from the factory. 30 Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Table 3. Bill of Materials, Buck Regulator, 12 V to 3.3 V and 5 V REF VALUE DESCRIPTION SIZE MFR PART NUMBER C1 100 μF Capacitor, Aluminum, SM, 25 V, 0.3 Ω 8 mm × 10 mm C12 220 μF Capacitor, Aluminum, SM, 6.3 V, 0.4 Ω 8 mm × 6.2 mm Panasonic EEVFC0J221P C13 100 pF Capacitor, Ceramic, 50 V, [COG], [20%] 603 muRata Std. C3 0.1 pF Capacitor, Ceramic, 50 V, [X7R], [20%] 603 muRata Std. 1 μF Capacitor, Ceramic, 50 V, [X7R], [20%] 603 muRata Std. C2, C11 C4, C5 Sanyo 20SVP100M 470 pF Capacitor, Ceramic, 50 V, [X7R], [20%] 603 muRata Std. C6 0.047 μF Capacitor, Ceramic, 50 V, [X7R], [20%] 603 muRata Std. C7 10 pF Capacitor, Ceramic, 50 V, [COG], [20%] 603 muRata Std. C8 1500 pF Capacitor, Ceramic, 50 V, [X7R], [20%] 603 muRata Std. D1 12 V Diode, Zener, 12 V, 350 mW SOT23 Diodes, Inc. BZX84C12T Diode, Schottky, 30 A, 30 V SMC On Semi MBRS330T3 D2 D3 Diode Zener, 12 V, 5 mA VMD2 Rohm VDZT2R12B J1,J3 Terminal Block, 4 Pin, 15 A, 5.1 mm 0.8 × 0.35 OST ED2227 J2 Header, 2 pin, 100-mil spacing (36-pin strip) 0.100 × 2 Sullins PTC36SAAN Inductor, SMT, 3.2 A, 0.039 Ω 12.5 × 12.5 mm TDK SLF12575T330M3R2PF PCB 2-Layer PCB 2-Ounce Cu 1.4 × 2.12 × 0.062 HPA164 Q1 Trans, N-Chan Enhancement Switching, 50 mA SOT-143B Phillips BSS83 Q2 MOSFET, P-ch, 30 V, 3.6 A, 75 mΩ SuperSOT-6 Fairchild FDC654P U1 IC, Low Cost Non-Sync Buck Controller SO-8 TI TPS40200D L1 12 V 33 μH R1 10 Ω Resistor, Chip, 1/16 W, 1% 603 Std. Std. R10 100 kΩ Resistor, Chip, , 1/16W, 1% 603 Std. Std. R11 10 kΩ Resistor, Chip, 1/16 W, 1% 603 Std. Std. R12 1 MΩ Resistor, Chip, 1/16 W, 1% 603 Std. Std. R13 49.9 Ω Resistor, Chip, 1/16 W, 1% 603 Std. Std. R2 0.02 Ω Resistor, Chip, 1/16 W, 5% 2010 Std. Std. R3 68.1 kΩ Resistor, Chip, 1/16 W, 1% 603 Std. Std. R4 2.0 kΩ Resistor, Chip, 1/16 W, 1% 603 Std. Std. R5 0Ω Resistor, Chip, 1/16 W, 1% 603 Std. Std. R6 26.7 kΩ Resistor, Chip, 1/16 W, 1% 603 Std. Std. R7 1.0 kΩ Resistor, Chip, 1/16 W, 1% 603 Std. Std. R8 300 kΩ Resistor, Chip, 1/16 W, 1% 603 Std. Std. PCB Plots Figure 45 through Figure 47 show the design of the TPS40200EVM-001 printed circuit board. The design uses 2-layer 2-oz copper and is 1.4 in × 2.3 in. All components are mounted on the top side to allow the user to easily view, probe, and evaluate the TPS40200 control IC in a practical application. Moving components to both sides of the PCB or using additional internal layers can offer additional size reduction for space-constrained applications. Copyright © 2006–2011, Texas Instruments Incorporated 31 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Figure 45. TPS40200EVM-001 Component Placement (Viewed From Top) Figure 46. TPS40200EVM001 Top Copper (Viewed From Top) Figure 47. TPS40200EVM-001 Bottom Copper (X-Ray View From Top) 32 Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Application 2: 18-V to 50-V Input, 16-V Output at 1 A This is an example of using the TPS40200 in a higher voltage application. The output voltage is 16 V at 1 A with an 18-V to 50-V input. Module boards built to this schematic and a test report are available. Test Results The efficiency and load regulation from boards built from this design are shown in Figure 49 and Figure 50. Further information and support material is available. + + Figure 48. Buck Converter: VIN = 18 V to 50 V, VOUT = 16 V at 1 A 100 16.500 VIN = 24 V 16.450 95 Output Voltage - V Efficiency - % 16.400 VIN = 48 V 90 85 80 16.350 VIN = 48 V 16.300 16.250 VIN = 24 V 16.200 75 16.150 70 16.100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Load Current - A 0.8 Figure 49. Efficiency vs Load Copyright © 2006–2011, Texas Instruments Incorporated 0.9 1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Load Current - A 0.8 0.9 1.0 Figure 50. Load Regulation, Two Input Voltage Extremes 33 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Application 3: Wide-Input-Voltage LED Constant-Current Driver This application uses the TPS40200 as a buck controller that drives a string of LED diodes. The feedback point for this circuit is a sense resistor in series with this string. The low 0.7-V reference minimizes power wasted in this resistor and maintains the LED current at a value given by 0.7 V/RSENSE. As the input voltage is varied, the duty cycle changes to maintain the LED current at a constant value, so that the light intensity does not change with large input-voltage variations. + + Figure 51. Wide-Input-Voltage Range LED Driver 100 Efficiency - % 90 80 70 60 50 10.0 15.0 20.0 Input Voltage - V 25.0 30.0 Figure 52. Efficiency vs Input Voltage 34 Copyright © 2006–2011, Texas Instruments Incorporated TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com DESIGN REFERENCES PCB Layout Recommendations R3 R1 Input C5 C3 TPS40200 C6 RSENSE VDD 1 RC 8 C4 Q1 R5 ISEN 2 SS C1 L1 Output 7 R4 GDRV 6 3 COMP C2 D1 C7 C8 Ground GND 4 FB 5 R8 R9 C9 R6 R10 U D G-07045 R3 C5 TPS40200 C3 R1 VDD C4 R5 SS ISEN COMP GDRV FB GND R4 RSENSE Switch node R8 R6 Low current Control Components R9 R10 Q1 C1 High current Power stage components L1 D1 C9 C7 RC C8 C6 Input Output C2 Ground Kelvin Ground Kelvin Voltage Sense Figure 53. PCB Layout Recommendations Copyright © 2006–2011, Texas Instruments Incorporated 35 TPS40200-Q1 SLUS739D – SEPTEMBER 2006 – REVISED JULY 2011 www.ti.com Layout Hints • AC current loops must be kept as short as possible. For the maximum effectiveness from C1, place it near the VDD pin of the controller and design the input ac loop consisting of C1-RSENSE-Q1-D1 to be as short as possible. Excessive high-frequency noise on VDD during switching degrades overall regulation as the load increases. • The output loop A (D1-L1-C2) should also be kept as small as possible. Otherwise, the application’s output noise performance will be degraded. • It is recommended that traces carrying large ac currents not be connected through a ground plane. Instead, use PCB traces on the top layer to conduct the ac current, and use the ground plane as a noise shield. Split the ground plane as necessary to keep noise away from the TPS40200 and noise-sensitive areas, such as feedback resistors R6 and R10. • Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize radiated emissions. • For good output-voltage regulation, Kelvin connections should be brought from the load to R6 and R10. • The trace from the R6-R10 junction to the TPS40200 should be short and kept away from any noise source, such as the SW node. • The gate drive trace should be as close to the power FET gate as possible. The TPS40200 is encapsulated in a standard plastic SOIC-8 package. The typical PCB layout for this package is shown in Figure 54. 3.81 3 5.2 7.4 2.2 1.27 0.6 Dimensions are in millimeters Figure 54. Suggested SOIC-8 PCB Footprint Related Parts • • TPS4007/9 Low-Input Synchronous Buck Controller TL5001 Wide-Input-Range Controller Reference Documents • • • • • • 36 Under the Hood of Low-Voltage DC/DC Converters, SEM1500 Topic 5, 2002 Seminar Series Understanding Buck Power Stages in Switch-Mode Power Supplies, literature number SLVA057 Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400 – 2001 Seminar Series Designing Stable Control Loops, SEM 1400, 2001 Seminar Series http://power.ti.com TPS40K - DC/DC Controller Products Designer Software. This simple design tool supports the TPS40xxx family of controllers. To order a CD from the Product Information Center, request literature number SLU015, TPS40K/SWIFT CD-ROM. Copyright © 2006–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 21-Jan-2011 PACKAGING INFORMATION Orderable Device TPS40200QDRQ1 Status (1) ACTIVE Package Type Package Drawing SOIC D Pins Package Qty 8 2500 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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