TPS65137 www.ti.com SLVS929A – MAY 2010 – REVISED OCTOBER 2012 200mA Dual Output AMOLED Display Power Check for Samples: TPS65137 FEATURES DESCRIPTION • • • • • • • The TPS65137 is designed to provide best in class picture quality for AMOLED displays (Active Matrix Organic Light Emitting Diode) requiring positive and negative voltage supply rails. With its wide input voltage range the device is ideally suited for AMOLED displays, which are used in mobile phones and smart phones. With this device the input voltage can be higher than the positive output voltage and still maintains accurate regulation of VPOS. Using the digital control pin (CTRL) allows adjusting the negative output voltage in digital steps. The TPS65137 uses a novel technology enabling excellent line and load regulation with minimum output voltage ripple by using a LDO post regulator for VPOS. This is required avoiding disturbance of the AMOLED display due to input voltage transients occurring during transmit periods in mobile phones. 1 • • • • • • 2.3 V to 5.5 V Input Voltage Range 1% Output Voltage Accuracy VPOS Excellent Line Transient Regulation Low Noise Operation 200 mA Output Current Fixed 4.63 V Positive Output Voltage Digitally Programmable Negative Output Voltage Down to –5.23V –4.93V Default Value for VNEG Advanced Power Save Mode Short Circuit Protection Thermal Shutdown TPS65137A High impedance output in shutdown 3×3 mm 10 Pin QFN Package APPLICATIONS • Active Matrix OLED Power Supply TYPICAL APPLICATION L1 4.7mH VPOS 4.63V/200mA VIN 2.3V to 5.5V C2 2.2mF C1 4.7mF Enable and Digital OUTN Adjustment VNEG -4.93V/200mA C6 4.7mF C5 4.7mF C4 100nF L2 4.7mH 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2012, Texas Instruments Incorporated TPS65137 SLVS929A – MAY 2010 – REVISED OCTOBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) (2) (2) TA ORDERING P/N PACKAGE MARKING –40°C to 85°C TPS65137A PTTI For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder on ti.com. Contact the factory for the availability of the TPS65137 with output voltage discharge function. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Input voltage range (2) ESD rating UNIT MIN MAX VIN –0.3 7.0 CTRL, SWP, OUTP –0.3 7.0 SWP, OUTP –0.3 7.0 OUTN +0.3 –5.5 CB –0.3 7.0 CT –0.3 3.6 HBM V 2 kV MM 200 V CDM 500 V Continuous total power dissipation See Thermal Information Table Operating junction temperature range TJ –40 150 °C Operating ambient temperature range TA –40 85 °C Storage temperature range Tstg –65 150 °C (1) (2) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 TPS65137 www.ti.com SLVS929A – MAY 2010 – REVISED OCTOBER 2012 THERMAL INFORMATION TPS65137 THERMAL METRIC (1) DSC UNITS 10 Junction-to-ambient thermal resistance (2) θJA 56.5 (3) θJC(top) Junction-to-case(top) thermal resistance θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter θJC(bottom) (1) (2) (3) (4) (5) (6) (7) 65.8 (4) 25.2 (5) Junction-to-case(bottom) thermal resistance 1.0 (6) °C/W 17.9 (7) 2.5 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS (1) MIN NOM MAX UNIT VIN Input voltage range 2.3 5.5 V TA Operating ambient temperature –40 +85 °C TJ Operating junction temperature –40 +125 °C (1) Refer to application section for further information. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 3 TPS65137 SLVS929A – MAY 2010 – REVISED OCTOBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS VIN = 3.5V, EN = VIN, OUTP = 4.63V, OUTN = –4.93V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VIN Input voltage range IQ Operating quiescent current into Vin ISD Shutdown current into Vin UVLO Under-voltage lockout threshold fs Switching frequency 2.3 5.5 0.1 1.0 VIN falling 2.0 VIN rising 2.3 Iout = 100 mA Thermal shutdown Thermal shutdown hysteresis V μA 400 μA V 1.6 MHz 145 °C 10 °C OUTPUT OUTP VPOS Positive output voltage regulation IoutP Output current OUTP VIN = 2.3V to 5.5V, Iload=0mA to 150mA –1% 4.63 200 VIN = 3.7 V, Isw = 200 mA 300 SWP MOSFET rectifier on-resistance VIN = 3.7 V, Isw = 200 mA 350 Ileak Leakage current into OUTP CTRL = GND, VOUTP= 4.6V; TPS65137A ISWP SWP switch current limit VIN = 2.9 V Vdrop LDO Dropout voltage Iout = 100 mA 17 0.9 Line regulation Load regulation V mA SWP MOSFET on-resistance RDS(ON) 1% mΩ 25 uA 1.1 A 300 mV 0 %/V 0.001 %/mA OUTPUT OUTN VNEG Negative output voltage range VNEG Negative output voltage regulation VIN = 2.3V to 5.5V, Iload = 0mA to 150mA; Valid for all voltage steps SWN MOSFET on-resistance VIN = 3.7 V, Isw = 200 mA 400 SWN MOSFET rectifier on-resistance VIN = 3.7 V, Isw = 200 mA 550 ILKG Leakage current out of OUTN CTRL = GND, VOUTN=-5.2V; TPS65137A ISWN SWN switch current limit VIN = 2.9 V RDS(ON) –2.2 –5.2 V –100 +100 mV 19 1.1 Line regulation mΩ 30 1.35 A 0 Load regulation μA %/V 0.001 %/mA CTRL INTERFACE VH Logic high-level voltage VL Logic low-level voltage R Pull down resistor tinit Initialization time tss Softstart time toff Shutdown time period 80 μs thigh Pulse high level time period 2 10 25 μs tlow Pulse low level time period 2 10 25 μs tstore Data storage/accept time period tset OUTN transition time RT CT pin output impedance 4 1.2 150 V 0.4 V 200 860 kΩ 300 400 1 30 30 CT = 100 nF Submit Documentation Feedback 80 20 150 250 μs ms μs ms 500 kΩ Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 TPS65137 www.ti.com SLVS929A – MAY 2010 – REVISED OCTOBER 2012 DEVICE INFORMATION 10 PIN TQFN PACKAGE (TOP VIEW 1 SWN 2 OUTN 3 CTRL 4 CT 5 10 PGND Exposed Thermal Die VIN 9 SWP 8 CB 7 OUTP 6 GND Pin Functions PIN NAME DESCRIPTION NO. I/O VIN 1 I Input supply CT 5 O Sets the settling time for the voltage on Vneg when programmed to a new value CB 8 O Internal boost converter bypass capacitor GND 6 Analog ground PGND 10 Power Ground SWN 2 Switch pin of the negative buck boost converter OUTN 3 O Output of negative buck boost converter OUTP 7 O Output of the boost converter CTRL 4 I Combined enable and output voltage program pin SWP 9 Exposed thermal die Switch pin of the boost converter Connect this pad to analog GND. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 5 TPS65137 SLVS929A – MAY 2010 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE Efficiency versus Output current Figure 1 Efficiency versus Input voltage Figure 2 Efficiency versus Negative voltage Figure 3 Negative output voltage programming Negative output voltage programming Figure 4 Device enabled (CTRL = 400µs high), programmed to –3.0V Figure 5 Light load current operation Figure 6 Nominal load current operation VIN = 3.7V Figure 7 Nominal load current operation VIN = 4.5V Figure 8 Line transient response 150mA Figure 9 Line transient response 100mA Figure 10 Startup Figure 11 Shutdown Figure 12 Short circuit Figure 13 100 90 100 VPOS = 4.63 V, VNEG = -4.93 V, VIN = 4.5 V L = 4.7 mH TDK VLF4012 VPOS = 4.63 V, VNEG = -4.93 V, 95 L = 4.7 mH TDK VLF4012 VIN = 4.2 V 90 IO = 140 mA VIN = 2.5 V VIN = 3 V 70 Efficiency - % Efficiency - % 80 VIN = 3.7 V 60 IO = 100 mA 85 80 75 IO = 10 mA 70 IO = 50 mA 50 65 40 0 50 100 150 200 IO - Output Current - mA 250 300 60 2 Figure 1. EFFICIENCY 6 Submit Documentation Feedback 2.5 3 3.5 4 4.5 5 VIN - Input Voltage - V Figure 2. EFFICIENCY 5.5 6 Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 TPS65137 www.ti.com SLVS929A – MAY 2010 – REVISED OCTOBER 2012 100 95 VIN = 3.7 V, VPOS = 4.63 V, IO = 100 mA, VIN = 3.6 V, VPOS = 4.63 V, Efficiency - % L = 4.7 mH TDK VLF4012 90 VPOS 2 V/div 85 VNEG 2 V/div VNEG = -4.93 V to -3 V, IO = 50 mA, CT = 47 nF 80 10 ms/div 75 70 -5.5 -5 -4.5 -4 -3.5 -3 VNEG - V Figure 3. EFFICIENCY -2.5 -2 Figure 4. NEGATIVE OUTPUT VOLTAGE PROGRAMMING VIN = 3.6 V, VPOS = 4.63 V, VPOS 2 V/div VNEG 2 V/div VCTRL 2 V/div VNEG = -4.93 V to -3 V, RLoad = 600 W, CT = 47 nF VPOS 20 mV/div Vswpos 2 V/div Vswneg 10 V/div Positive Inductor current 200 mA/div VIN = 3.7 V, VPOS = 4.63 V, VNEG = -4.93 V, IO = 20 mA 200 ms/div Figure 5. NEGATIVE OUTPUT VOLTAGE PROGRAMMING (Device enabled (CTRL = 400µs high), programmed to –3.0V) 250 ns/div Figure 6. LIGHT LOAD CURRENT OPERATION VPOS 20 mV/div VPOS 20 mV/div Vswpos 2 V/div Vswpos 2 V/div Vswneg 10 V/div Vswneg 10 V/div Positive Inductor current 200 mA/div VIN = 3.7 V, VPOS = 4.63 V, VNEG = -4.93 V, IO = 150 mA 250 ns/div Figure 7. NOMINAL LOAD CURRENT OPERATION (VIN = 3.7V) Positive Inductor current 200 mA/div VIN = 4.5 V, VPOS = 4.63 V, VNEG = -4.93 V IO = 150 mA 250 ns/div Figure 8. NOMINAL LOAD CURRENT OPERATION (VIN = 4.5V) Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 7 TPS65137 SLVS929A – MAY 2010 – REVISED OCTOBER 2012 www.ti.com VIN = 2.9 V to 3.4 V/50 ms, VPOS = 4.63 V, VIN = 2.9 V to 3.4 V/50 ms, VPOS = 4.63 V, VIN 1 V/div VNEG = -4.93 V, IO = 150 mA VIN 1 V/div VPOS 20 mV/div VPOS 20 mV/div VNEG 50 mV/div VNEG 50 mV/div 100 ms/div Figure 9. LINE TRANSIENT RESPONSE (150mA) VNEG = -4.93 V, IO = 100 mA 100 ms/div Figure 10. LINE TRANSIENT RESPONSE (100mA) VIN = 3.7 V, VPOS = 4.63 V, VNEG = -4.93 V, RLoad = 600 W VNEG 2 V/div VPOS 2 V/div VPOS 2 V/div VIN 2 V/div VNEG 2 V/div VIN 2 V/div Iin 100 mA/div VIN = 3.8 V, VPOS = 4.63 V, VNEG = -4.93 V, RLoad = Open 50 ms/div Figure 12. SHUTDOWN 200 ms/div Figure 11. STARTUP VIN = 3.7 V, VPOS = 4.63 V, VNEG = -4.93 V, VPOS shorted VNEG 2 V/div VNEG VPOS 2 V/div Iout 100 mA/div 20 ms/div Figure 13. SHORT CIRCUIT 8 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 TPS65137 www.ti.com SLVS929A – MAY 2010 – REVISED OCTOBER 2012 FUNCTIONAL BLOCK DIAGRAM CB SWP GND Bias OUTP LDO VIN Gate Drive SS SS PGND Voltage Controlled Oscillator VCO Softstart generation PWM / PFM Control SS Current Sense / Softstart + + Current Sense / Softstart SS PWM / PFM Control Vref + CT + 5 Bit DAC Gate Drive Digital Interface OUTN CTRL GND SWN PGND Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 9 TPS65137 SLVS929A – MAY 2010 – REVISED OCTOBER 2012 www.ti.com DETAILED DESCRIPTION The TPS65137 consists of a boost converter using a LDO as post regulator. The output voltage of the boost converter is regulated to operate the internal LDO above its dropout voltage maintaining best line and load regulation of OUTP. The internal LDO disconnects OUTP during shutdown and allows regulation of the output when the input voltage is higher than OUTP. The LDO minimizes the output voltage ripple of OUTP. The negative output uses a buck boost converter topology operating in DCM (Discontinuous Conduction Mode) providing superior line regulation. In order to adjust the output voltage of the negative converter a digital interface can be used to program the output voltage. To achieve high efficiency over the entire load current range the device reduces the switching frequency with the load current using its internal voltage controlled oscillator (VCO). Since the boost converter output CB is post regulated by the integrated LDO (Low Dropout Regulator) the output voltage ripple is minimized and the line transient response is at its best. Because of this topology the operation mode of the boost converter has minimum effect on the output voltage ripple observed on OUTP. The boost converter, as well as the negative converter operate in peak current mode using the VCO (Voltage Controlled Oscillator) while operating in DCM (Discontinuous Conduction Mode). When entering CCM (Continuous Conduction Mode) the converter operates in peak current control using fixed off time control. POWER SAVE MODE OPERATION In order to maintain high efficiency over the entire load current range the converter reduces its switching frequency as the load current decreases. To maintain a controlled switching frequency a voltage controlled oscillator (VCO) is used. SOFT START AND SHORT CIRCUIT PROTECTION The device has a soft-start implemented limiting inrush current during turn on. The device is also protected against short circuits of the outputs to ground or when the outputs shorted together. This is implemented with two output voltage thresholds determining the device switch current limit and LDO operation shown in Figure 14. Voutp Iswlim= full current limit Boost starts LDO off Voutn Isw lim= 120 mA Voutp Isw lim = 220 mA LDO = 100 mA current limit Voutn Isw lim = 120 mA Voutn = -0.4 V LDO = full current limit Voutn Iswlim= full current limit Voutp = 3 V Voutn = -1 V Figure 14. Soft Start and Short Circuit Thresholds When the device is enabled pulling CTRL pin high then the boost converter and buck converter starts with reduced switch current limit. During this period of time the LDO is turned off. As VNEG reaches –0.4V then the LDO is turned on having a 100mA current limit. The switch current limit of both outputs is increased to 220mA and 120mA. When VPOS reaches 3V and VNEG reaches –1V, then both outputs operate with full current limit. This architecture limits the inrush current during start-up and protects the device during short circuits events. When the positive output is shorted to the negative output then the device cycles between the first and second section of the start-up sequence. By that, the output current cycles between zero and 100mA. This protects the device and avoids excessive power dissipation during short circuit conditions. With this architecture the device is able to start-into full load current once VPOS exceeds 3V and VNEG is lower than –1V. 10 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 TPS65137 www.ti.com SLVS929A – MAY 2010 – REVISED OCTOBER 2012 ENABLE (CTRL pin) The CTRL pin serves two functions. One is the enable and disable of the device, the other is the output voltage programming of the device. If the digital interface is not required the CTRL pin can be used as a standard enable pin for the device. Pulling CTRL high starts the converter operating with its default output voltage on OUTN of –4.93V. DIGITAL INTERFACE (CTRL) The digital interface allows programming the negative output voltage OUTN in digital steps. If the digital output voltage setting is not required then the CTRL pin can also be used as a standard enable pin. In such a case the device will come up with its default output voltage of OUTN of –4.93V. tinit toff tss High CTRL Low Vss VDD Figure 15. CTRL Used as a Standard Device Enable The digital output voltage programming of OUTN is implemented by a simple digital interface with the timing shown in Figure 16. tlow tinit thigh tstore toff tss High CTRL Low tset VSS VDD Figure 16. Digital Interface Using CTRL Once CTRL is pulled high the device will come up with its default voltage of –4.93V. The TPS65137 has a 5 bit DAC implemented with the correspondent output voltage as given in Table 1. The interface counts the rising edges applied to CTRL pin once the device is enable. For example with the timing diagram shown in Figure 16, OUTN is programmed to –4.93V since 4 rising edges are applied. Other output voltages are programmed according to Table 1. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 11 TPS65137 SLVS929A – MAY 2010 – REVISED OCTOBER 2012 www.ti.com Table 1. Programming Table for OUTN BIT/RISING EDGES OUTN (Vss) DAC VALUE BIT/RISING EDGES OUTN(Vss) DAC VALUE Default –4.93 V 00000 16 –3.7 V 10000 1 –5.23 V 00001 17 –3.62 V 10001 2 –5.13 V 00010 18 –3.52 V 10010 3 –5.03 V 00011 19 –3.42 V 10011 4 –4.93 V 00100 20 –3.32 V 10100 5 –4.83 V 00101 21 –3.22 V 10101 6 –4.73 V 00110 22 –3.12 V 10110 7 –4.63 V 00111 23 –3.02 V 10111 8 –4.53 V 01000 24 –2.92 V 11000 9 –4.43 V 01001 25 –2.82 V 11001 10 –4.33 V 01010 26 –2.72 V 11010 11 –4.23 V 01011 27 –2.62 V 11011 12 –4.13 V 01100 28 –2.52 V 11100 13 –4.03 V 01101 29 –2.42 V 11101 14 –3.93 V 01110 30 –2.31 V 11110 15 –3.82 V 01111 31 –2.21 V 11111 Vneg Programming Transition Time tset for OUTN (CT) The TPS65137 allows setting the transition time tset using an external capacitor connected to pin CT. The transition time is the time period required to move OUTN from one voltage level to the next programmed voltage level. When the CT pin is left open then the shortest possible transition time is programmed. When connecting a capacitor to the CT pin then the transition time is given by the R-C time constant. This is given by the output impedance of the CT pin of typically 250kΩ and the external capacitance. Within one τ the output voltage OUTN has reached 70% of its programmed value. An example is given when using 100nF for CT. τ ≈ tset70% = 250 kΩ × CT = 250 kΩ × 100 nF = 25 mS INPUT CAPACITOR SELECTION The device typically requires a 4.7μF ceramic input capacitor. Larger values can be used to lower the input voltage ripple. Table 2. Input Capacitor Selection CAPACITOR COMPONENT SUPPLIER SIZE 4.7 μF/10 V Taiyo Yuden LMK107BJ475 0603 10 μF/10 V Taiyo Yuden LMK212BJ106 0805 10 μF/6.3 V Taiyo Yuden JMK107BJ106 0603 BOOST CONVERTER DESIGN CONSIDERATION, Vpos The positive output consists of a boost converter using a LDO as post regulator. The maximum output current is limited by the minimum current limit of the LDO, of 200mA. The component values and output current are calculated at maximum load current in continuous conduction operation. The typical switching frequency during this operation mode is 1.4MHz. The boost converter duty cycle is: D=1 - VIN ´ η VPOS (1) To calculate the duty cycle, a good estimation for the efficiency, η, is 75% or it can be taken out of the typical curve in Figure 1. In order to calculate the maximum output current of the boost converter for a certain input voltage, the following formula is used: 12 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 TPS65137 www.ti.com SLVS929A – MAY 2010 – REVISED OCTOBER 2012 æ VIN ´ D ö Iout = (1 - D )ç Isw ÷ 2 ´ ¦s ´ L ø è (2) The maximum output current is given at the highest switching frequency of typically 1.4MHz and minimum switch current limit of 0.9A. Equation 3 is used to calculate the switch peak current. Iswpeak = VIN ´ D Iout + 2 ´ ¦s ´ L 1 - D (3) The inductor needs to be rated for this switch peak current to avoid inductor saturation. The boost converter output capacitor is connected to pin CB and a 4.7µF capacitor is sufficient. A 2.2µF capacitor is used on the output VPOS, which is the output of the internal low dropout regulator (LDO). Table 3. Output Capacitor Selection CAPACITOR COMPONENT SUPPLIER SIZE 4.7 μF/10 V Taiyo Yuden LMK107BJ475 0603 2.2 μF/10 V Taiyo Yuden LMK107BJ225 0603 NEGATIVE BUCK BOOST CONVERTER DESIGN CONSIDERATION, Vneg The negative output is generated with a buck boost converter. The component values and output current are calculated at maximum load current in continuous conduction operation. The typical switching frequency during this operation mode is 1.4MHz. The buck boost converter duty cycle is: D= VNEG VIN ´ η + VNEG (4) To calculate the duty cycle a good estimation for the efficiency, η, is 75% or it can be taken out of the typical curve in Figure 1. In order to calculate the maximum output current of the buck boost converter for a certain input voltage, the following formula is used: æ VIN ´ D ö Iout = (1 - D )ç Isw ÷ 2 ´ ¦s ´ L ø è (5) The maximum output current is given at the highest switching frequency of typically 1.4MHz and minimum switch current limit of 1.1A. Equation 6 is used to calculate the switch peak current. Iswpeak = VIN ´ D Iout + 2 ´ ¦s ´ L 1 - D (6) The inductor needs to be rated for this switch peak current to avoid inductor saturation. Refer to Table 4 for possible inductors for this application. A 4.7μF output capacitor is used on the output VNEG. Larger capacitor values can be used to minimize the output voltage ripple. Refer to Table 3 for output capacitor selection. INDUCTOR SELECTION The device is optimized to operate with 4.7uH inductors. Different inductor values will change the converter efficiency and output voltage ripple. A 2.2uH inductor is also a possible solution. Any other inductor values will degrade device performance and stability which is not recommended for this device. Table 4. Inductor Selection INDUCTOR VALUE COMPONENT SUPPLIER DIMENSIONS in mm Isat/DCR 4.7 μH TDK VLF4012 3.7 × 3.5 × 1.2 1.1A/140mΩ Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 13 TPS65137 SLVS929A – MAY 2010 – REVISED OCTOBER 2012 www.ti.com APPLICATION INFORMATION PCB LAYOUT The layout for his device is important to keep the output voltage ripple and output voltage accuracy as low and accurate as possible. The following layout guidelines apply for this device: • Keep the switch note pad for the boost converter and inverter switch as small as possible to avoid coupling into the output. • The ground connection for the inductor of the negative converter needs to be as wide as possible to avoid noise generated by inductor ground currents. • The ground connection of the timing capacitor on pin CT needs to be isolated and directly routed to the GND pin of the device. This is important to avoid noise being coupled into the error amplifier which is internally connected to the CT pin. • Having the ground connection of the boost converter output capacitor and LDO output capacitor in a close connection to the device ground and power pad connection achieves best load regulation. 14 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 TPS65137 www.ti.com SLVS929A – MAY 2010 – REVISED OCTOBER 2012 REVISION HISTORY Changes from Original (May 2010) to Revision A Page • Changed Features 6, 7 and 8 from 4.6V to 4.63V, -5.2V to -5.23V and -4.9V to -4.93V ..................................................... 1 • Changed TYPICAL APPLICATION VPOS from 4.6V/200mA to 4.63V/200mA ...................................................................... 1 • Changed ELECTRICAL CHARACTERISTICS conditions from OUTP=4.6V to OUTP=4.63V and OUTN= -4.9V to 4.93V ..................................................................................................................................................................................... 4 • Changed ELECTRICAL CHARACTERISTICS OUTPUT OUTP VPOS, TYP column from 4.6 to 4.63 ................................. 4 • Changed VPOS from 4.6V to 4.63V and VNEG from -4.9V -4.93V in graphs .......................................................................... 6 • Changed Figure 9 waveform ................................................................................................................................................ 7 • Changed Figure 10 waveform .............................................................................................................................................. 7 • Changed -4.9V. to -4.93V in Digital Interface (CTRL) section ............................................................................................ 11 • Changed values in Table 1 ................................................................................................................................................. 12 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TPS65137 15 PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) TPS65137ADSCR ACTIVE Package Type Package Pins Package Drawing Qty WSON DSC 10 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) CU NIPDAU Level-2-260C-1 YEAR (4/5) -40 to 85 PTTI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65137ADSCR WSON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS65137ADSCR WSON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65137ADSCR WSON DSC 10 3000 367.0 367.0 35.0 TPS65137ADSCR WSON DSC 10 3000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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