UC2825A-Q1 www.ti.com SLUS781 – SEPTEMBER 2007 HIGH-SPEED PWM CONTROLLER FEATURES 1 • • • • • • • • • • Qualified for Automotive Applications Improved Version of the UC3825 PWM Compatible With Voltage-Mode or Current-Mode Control Methods Practical Operation at Switching Frequencies to 1 MHz 50-ns Propagation Delay to Output High-Current Dual Totem-Pole Outputs: 2 A (Peak) Trimmed Oscillator Discharge Current Low 100-μA Startup Current Pulse-by-Pulse Current-Limiting Comparator Latched Overcurrent Comparator With Full-Cycle Restart DESCRIPTION The UC2825A pulse-width modulation (PWM) controller is an improved versions of the standard UC3825. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is specified to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead-time control. Frequency accuracy is improved to 6%. Startup supply current, typically 100 μA, is ideal for off-line applications. The output drivers are redesigned to actively sink current during undervoltage lockout (UVLO) at no expense to the startup current specification. In addition, each output is capable of 2-A peak currents during transitions. BLOCK DIAGRAM 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated UC2825A-Q1 www.ti.com SLUS781 – SEPTEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Functional improvements have also been implemented. The shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. The CLOCK pin has become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing. The UC2825A has dual alternating outputs and the same pin configuration of the UC3825. "A" version parts have UVLO thresholds identical to the original UC3825. See the application report, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers (SLUA125) for detailed technical and application information. ORDERING INFORMATION (1) TJ MAXIMUM DUTY CYCLE UVLO –40°C to 125°C <50% 9.2 V/8.4 V (1) (2) PACKAGE (2) SOIC – DW Reel of 2000 ORDERABLE PART NUMBER UC2825AQDWRQ1 TOP-SIDE MARKING UC2825AQDW For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. PIN ASSIGNMENTS DW PACKAGE (TOP VIEW) INV NI EAOUT CLK/LEB RT CT RAMP SS 2 Submit Documentation Feedback 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VREF VCC OUTB VC PGND OUTA GND ILIM Copyright © 2007, Texas Instruments Incorporated UC2825A-Q1 www.ti.com SLUS781 – SEPTEMBER 2007 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION CLK/LEB 4 O Output of the internal oscillator CT 6 I Timing capacitor connection for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length. EAOUT 3 O Output of the error amplifier for compensation GND 10 ILIM 9 I Input to the current limit comparator INV 1 I Inverting input to the error amplifier NI 2 I Noninverting input to the error amplifier OUTA 11 O High-current totem-pole output A of the on-chip drive stage OUTB 14 O High-current totem-pole output B of the on-chip drive stage PGND 12 RAMP 7 I Noninverting input to the PWM comparator with 1.25-V internal input offset. In voltage-mode operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak current-mode operation, this serves as the slope compensation input. RT 5 I Timing resistor connection for oscillator frequency programming SS 8 I Soft-start input and the maximum duty cycle clamp VC 13 Power supply for the output stage. This pin should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths. VCC 15 Power supply for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths VREF 16 Analog ground return Ground return for the output driver stage O 5.1-V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range unless otherwise noted VALUE VIN Supply voltage VC, VCC 22 V IO Source or sink current, dc OUTA, OUTB 0.5 A IO Source or sink current, pulse (0.5 μs) OUTA, OUTB 2.2 A INV, NI, RAMP –0.3 V to 7 V ILIM, SS –0.3 V to 6 V Analog inputs Power ground PGND ±0.2 V ICLK Clock output current CLK/LEB –5 mA IO(EA) Error amplifier output current EAOUT 5 mA ISS Soft-start sink current SS 20 mA IOSC Oscillator charging current RT TJ Operating virtual junction temperature range –55°C to 150°C Tstg Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 in) from case for 10 s (1) –5 mA 300°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3 UC2825A-Q1 www.ti.com SLUS781 – SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.05 5.1 5.15 V Reference, VREF VO Ouput voltage TJ = 25°C, IO = 1 mA Line regulation 12 V ≤ VCC ≤ 20 V 2 15 mV Load regulation 1 mA ≤ IO ≤ 10 mA 5 20 mV Total output variation Line, load, temperature Temperature stability 5.03 T(min) < TJ < T(max) 0.2 Output noise voltage (1) 10 Hz < f < 10 kHz 50 Long term stability (1) TJ = 125°C, 1000 hours Short circuit current VREF = 0 V (1) 5 30 TJ = 125°C 60 30 5.17 V 0.4 mV/°C μVRMS 25 90 110 mV mA Oscillator fOSC Initial accuracy (1) Total variation (1) TJ = 25°C 375 400 RT = 6.6 kΩ, CT = 220 pF, TJ = 25°C 0.9 1 Line, temperature 350 450 kHz RT = 6.6 kΩ, CT = 220 pF 0.85 1.15 MHz Voltage stability 12 V < VCC < 20 V Temperature stability (1) T(min) < TJ < T(max) kHz 1.1 MHz 1 % ±5 % 3.7 4 V 0 0.2 V Ramp peak 2.6 2.8 3 V Ramp valley 0.7 1 1.25 V 1.6 1.8 2 High-level output voltage, clock Low-level output voltage, clock Ramp valley to peak IOSC 425 Oscillator discharge current TJ = –40°C RT = Open, VCT = 2 V 1.55 9 TJ = 125°C 2 10 8 11 11 V mA Error Amplifier Input offset voltage Input bias current Input offset current 2 10 mV 0.6 3 μA 0.1 1 μA Open loop gain 1 V < VO < 4 V 60 95 dB CMRR Common-mode rejection ratio 1.5 V < VCM < 5.5 V 75 95 dB PSRR Power-supply rejection ratio 12 V < VCC < 20 V 85 110 dB IO(sink) Output sink current VEAOUT = 1 V 1 2.5 mA IO(src) Output source current VEAOUT = 4 V –0.5 –1.3 High-level output voltage IEAOUT = –0.5 mA 4.5 4.7 5 Low-level output voltage IEAOUT = –1 mA 0 0.5 1 Gain bandwidth product f = 200 kHz 6 12 MHz 6 9 V/μs Slew rate (1) (1) 4 mA V V Specified by design Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated UC2825A-Q1 www.ti.com SLUS781 – SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –1 –8 μA 0 % PWM Comparator IBIAS Bias current, RAMP VRAMP = 0 V Minimum duty cycle Maximum duty cycle 85 tLEB Leading edge blanking time RLEB = 2 kΩ, CLEB = 470 pF RLEB Leading edge blanking resistance VCLK/LEB = 3 V VZDC Zero dc threshold voltage, EAOUT VRAMP = 0 V tDELAY Delay-to-output time (2) VEAOUT = 2.1 V, VILIM = 0 V to 2 V step % 300 375 450 ns 8 10 12 kΩ 1.10 1.25 1.4 V 50 80 ns 20 μA Current Limit / Start Sequence / Fault ISS Soft-start charge current VSS Full soft-start threshold voltage IDSCH Restart discharge current ISS Restart threshold voltage IBIAS ILIM bias current ICL Current limit threshold voltage Overcurrent threshold voltage Delay-to-output time, ILIM(1) td VSS= 2.5 V 8 14 4.3 5 100 250 350 μA 0.3 0.5 V 15 A 0.95 1 1.05 1.14 1.2 1.26 50 80 IOUT = 20 mA 0.25 0.4 IOUT = 200 mA 1.2 2.2 IOUT = –20 mA 1.9 2.9 2 3 20 45 ns VSS= 2.5 V VILIM = 0 V to 2 V step VILIM = 0 V to 2 V step V V ns Output Low-level output saturation voltage High-level output saturation voltage tr, tf Rise/fall time (2) IOUT = –200 mA CL = 1 nF V V Undervoltage Lockout (UVLO) Start threshold voltage 8.4 9.2 9.6 V UVLO hysteresis 0.4 0.8 1.2 V 100 300 μA 28 36 mA Supply Current Isu Startup current ICC Input current (2) VC = VCC = VTH = –0.5 V Specified by design Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 5 UC2825A-Q1 www.ti.com SLUS781 – SEPTEMBER 2007 APPLICATION INFORMATION The oscillator is a sawtooth. The rising edge is governed by a current controlled by the RT pin and value of capacitance at the CT pin (CCT). The falling edge of the sawtooth sets dead time for the outputs. Selection of RT should be done first, based on desired maximum duty cycle. CT can then be chosen based on the desired frequency (RT) and DMAX. The design equations are: RT + 3V (10 mA) ǒ1 * DMAXǓ CT + ǒ1.6 ǒR T D MAXǓ fǓ (1) Recommended values for RT range from 1 kΩ to 100 kΩ. Control of DMAX less than 70% is not recommended. IR RT 3V IC = IR CT CLK ID = 10 mA R LEB VTH C Figure 1. Oscillator OSCILLATOR FREQUENCY vs TIMING RESISTANCE MAXIMUM DUTY CYCLE vs TIMING RESISTANCE 100 10 M DMAX - Maximum Duty Cycle - % f - Frequency - Hz 95 1M 100 k 90 85 80 75 10 k 70 1k 10 k RT - Timing Resistance - W Figure 2. 6 Submit Documentation Feedback 100 k 1k 10 k RT - Timing Resistance - W 100 k Figure 3. Copyright © 2007, Texas Instruments Incorporated UC2825A-Q1 www.ti.com SLUS781 – SEPTEMBER 2007 Leading Edge Blanking (LEB) The UC2825A performs fixed-frequency PWM control. The outputs are alternately controlled. During every other cycle, one output is off. Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0% to less than 50%. To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator. On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is controlled by the PWM comparator, current limit comparator, or the overcurrent comparator. Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates the pulse. LEB causes the PWM comparator to be ignored for a fixed amount of time after the start of the pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not require any filtering as result of LEB. To program a LEB period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and the internal 10-kΩ resistor determines the blanked interval. The 10-kΩ resistor has a 10% tolerance. For more accuracy, an external 2-kΩ 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 kΩ with a tolerance of 2.4%. The design equation is: t LEB + 0.5 ǒR ø 10 kWǓ C (2) Values of R less than 2 kΩ should not be used. LEB is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold, the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent faults without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the outputs driven low. For this reason, some noise filtering may be required on the ILIM pin. CT CLK/LEB LEB Ramp Input Blanked Ramp to PWM Figure 4. Leading Edge Blanking Operational Waveforms Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7 UC2825A-Q1 www.ti.com SLUS781 – SEPTEMBER 2007 UVLO, Soft Start, and Fault Management Soft start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error amplifier output is also forced low. While the internal 9-μA source charges the SS pin, the error amplifier output follows until closed loop regulation takes over. Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start capacitor is then discharged by a 250-μA current sink. No more output pulses are allowed until the soft-start capacitor is fully discharged and ILIM is below 1.2 V. At this time, the fault latch resets and the chip executes a soft start. Should the fault latch get set during soft start, the outputs are immediately terminated, but the soft-start capacitor does not discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous fault conditions. 1.2 V FAULT 5.0 V VSS 1.2 V 0.2 V ON PWM OFF Figure 5. Soft-Start and Fault Waveforms Active-Low Outputs During UVLO The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to operate. UDG-95108 Figure 6. Output Voltage vs Output Current 8 Submit Documentation Feedback UDG-95106 Figure 7. Output Voltage and Current During UVLO Copyright © 2007, Texas Instruments Incorporated UC2825A-Q1 www.ti.com SLUS781 – SEPTEMBER 2007 Control Methods Current Mode Voltage Mode UDG-95110 UDG-95109 . Figure 8. Control Methods Synchronization The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the free-running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The pulse width should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge of the CLK/LEB pin can be used to generate a synchronizing pulse for other chips. Note that the CLK/LEB pin no longer accepts an incoming synchronizing signal. UDG-95113 Figure 9. General Oscillator Synchronization Figure 10. Two Unit Interface UDG-95112 Figure 11. Operational Waveforms Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 9 UC2825A-Q1 www.ti.com SLUS781 – SEPTEMBER 2007 High-Current Outputs Each totem pole output can deliver a 2-A peak current into a capacitive load. The output can slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC) and power ground (PGND) pins help decouple the device's analog circuitry from the high-power gate drive noise. The use of 3-A Schottky diodes (1N5120, USD245, or equivalent) (see Figure 13) from each output to both VC and PGND are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of inductive/capacitive load, typical of a MOSFET gate. Schottky diodes must be used because a low forward voltage drop is required. Do not use standard silicon diodes. Although they are single-ended devices, two output drivers are available on the UC2825A. These can be paralleled by the use of a 0.5-Ω (noninductive) resistor connected in series with each output for a combined peak current of 4 A. VC VC 1 nF 10 µF D1 OUT 6.8 W D2 PGND GND D1, D2 = 1N5820 Figure 12. Power MOSFET Drive Circuit Ground Planes Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct operation of the chip. A ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stages. This point is the power ground to which the PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a single point, although this is not necessary if the high di/dt paths are well understood and accounted for. VCC should be bypassed directly to power ground with a good high-frequency capacitor. The sources of the power MOSFET should connect to power ground, as should the return connection for input power to the system and the bulk input capacitor. The output should be clamped with a high-current Schottky diode to both VCC and PGND. Nothing else should be connected to power ground. VREF should be bypassed directly to the signal portion of the ground plane with a good high-frequency capacitor. Low ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog circuitry should, likewise, be bypassed to the signal ground plane. 10 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated UC2825A-Q1 www.ti.com SLUS781 – SEPTEMBER 2007 UDG-95115 Figure 13. Ground Planes Diagram Open-Loop Test Circuit This test fixture is useful for exercising many functions of this device family and measuring their specifications. As with any wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground plane is highly recommended. UC2825A Figure 14. Open-Loop Test Circuit Schematic Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing UC2825AQDWRQ1 ACTIVE SOIC DW Pins Package Eco Plan (2) Qty 16 2000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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